Connector for bare chip test
By designing connectors for bare chip testing, the problem of connection difficulties of bare chips in electrostatic tests is solved, efficient and low-cost electrostatic testing is achieved, and diverse circuit designs and stable connections are supported.
Patent Information
- Application Number
- CN202421399002.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-19
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2034-06-19
AI Technical Summary
In the prior art, the bare chip cannot be connected to the electrostatic simulator before the electrostatic test, and the chip is fragile in the unpackaged stage and is prone to damage, resulting in low testing efficiency and high cost.
A connector for bare chip testing is designed, including a substrate and an insulating cover. The surface of the substrate is equipped with metal clamps and electrical connection points. The insulating cover is equipped with plug-in holes. The electrical connection between the bare chip and the electrostatic simulator is achieved through spring pins and zero-impedance jumpers, and stability is ensured in combination with the downward clamp assembly.
The direct connection between the bare chip and the electrostatic simulator is realized, which reduces the risk of manual welding, improves testing efficiency, reduces costs, and supports diversified circuit testing, enhancing the stability and accuracy of the test.
Smart Images
Figure CN223205603U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip sealing and testing, in particular to a connector for bare chip testing. Background Art
[0002] In the past, electrostatic tests were conducted only after the chips were fully packaged. It was impossible to conduct electrostatic tests directly on unpackaged bare chips. This is because the design channels of current electrostatic simulators are still connected to the packaged chip pins through test boards and fixtures. Furthermore, the bare chips themselves are relatively fragile as the pins have not yet been exposed. Currently, there are no dedicated electrostatic simulator fixtures designed for bare chips. Utility Model Content
[0003] The utility model provides a connector for bare chip testing, which is convenient for connecting the bare chip with an electrostatic simulator.
[0004] In one embodiment, a connector for bare chip testing includes a substrate, a metal clip, and an insulating cover, wherein:
[0005] The substrate surface includes at least one plug-in area, and the plug-in area is fixed with a plurality of the metal clips arranged at intervals;
[0006] The insulating cover is provided above the plug-in area and is provided with a plurality of plug-in holes. A row of plug-in holes corresponds to a row above each metal clip. The row of plug-in holes includes at least one plug-in hole. Any plug-in hole in the same row can be electrically connected to the metal clip below it.
[0007] The substrate is provided with a plurality of electrical connection points, and the plurality of electrical connection points can be electrically connected to the electrostatic simulator when the substrate is placed in the electrostatic simulator.
[0008] Optionally, the connector includes a plurality of plug-in areas arranged in the same direction.
[0009] Optionally, an arrangement direction of the metal clips is perpendicular to an arrangement direction of the plurality of plug-in areas.
[0010] Optionally, the connector further comprises a zero-impedance jumper wire, which is used to connect the metal clips between adjacent plug-in areas in series one by one.
[0011] Optionally, the connector further includes a spring pin header, the spring pin header including a plurality of vertically arranged spring pins, the lower ends of the spring pins being used to pass through the plug-in holes and electrically connect to the metal clip, and the upper ends of the spring pins being used to electrically connect to the bare chip.
[0012] Optionally, the connector further includes a plurality of wires, and the plurality of metal clips in at least one of the plug-in areas are respectively connected to the plurality of electrical connection points via a wire.
[0013] Optionally, the plug-in holes in the plug-in area are further plugged with external circuit elements, which include wires, resistors, capacitors, and inductors.
[0014] Optionally, the connector also includes a press-down clamp assembly, which includes: a screw rod vertically fixed on the opposite side edges of the substrate, and the screw rod is fixed to the substrate through a screw rod fixing seat at the bottom thereof; a clamp cover spanning the plug-in area and connected to the screw rod through a through-hole; and a press-down screw threadedly connected to the screw rod to press the clamp cover downward.
[0015] Optionally, the clamp cover is provided with a through hole for accommodating a bare chip on the packaging board.
[0016] Optionally, positioning holes are provided at corners of the substrate to serve as alignment marks when the substrate is placed on an electrostatic simulator.
[0017] The connector provided by the above-mentioned embodiment of the present invention can serve as a connection medium between a package board with a bare chip and an electrostatic simulator. For COB boards, it can be further equipped with spring pin headers to complete the test without the need for manual soldering of the pin headers, thereby saving labor costs and improving work efficiency. It can also reduce the risk of damage to the bare chip caused by the soldering pin header procedure. At the same time, it is possible to insert additional circuit components in the plug-in area, and realize diversified testing of the bare chip by changing the circuit design. In addition, the downward clamp assembly can ensure that the package board and spring pin headers are pressed tightly against the substrate, improving the stability of the test process. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 Shown is a structural schematic diagram of a connector in one embodiment of the present utility model.
[0019] Figure 2 Shown is a schematic structural diagram of a spring pin header in an embodiment of the present invention.
[0020] Figure 3 Shown is a structural schematic diagram of a connector in another embodiment of the present invention.
[0021] Figure 4 Shown is a structural schematic diagram of the press-down clamp assembly in an embodiment of the present invention.
[0022] Figure 5 It is a schematic structural diagram of the clamp cover in an embodiment of the present invention.
[0023] Component number description
[0024] 1-Baseboard; 2-Positioning hole; 3-Electrostatic simulator channel contact point; 4-Tracking; 5-Screw fixing seat; 6-Screw; 7-Press-down screw; 8-Fixture cover; 9-Spring pin header; 10-Plug-in hole; 11-Zero impedance jumper; 12-First plug-in area; 13-Second plug-in area; 14-Third plug-in area; 15-Fourth plug-in area; 16-Through hole. DETAILED DESCRIPTION
[0025] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.
[0026] For ease of explanation, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged and not to scale. These schematic views are merely illustrative and should not limit the scope of protection of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.
[0027] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.
[0028] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.
[0029] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0030] like Figures 1 to 5As shown, an embodiment of the present invention provides a connector for bare chip testing, comprising:
[0031] The substrate 1 has a surface divided into a plurality of plug-in areas arranged in a longitudinal direction, and each plug-in area is fixed with a plurality of metal clips arranged in a transverse direction;
[0032] The insulating cover is positioned above the plug-in area and defines an array of plug-in holes 10. The number of plug-in holes arranged in the horizontal columns matches the number of metal clips, and the number of plug-in holes arranged in the vertical rows is greater than or equal to one. Any plug-in hole in the same column can achieve electrical connection with the underlying metal clip. The diameter of each plug-in hole 10 is 0.5-2 mm, preferably 1 mm. The spacing between adjacent columns of plug-in holes 10 is 1-5 mm, preferably 2.54 mm. In practice, the insulating cover can be made of plastic or other suitable materials.
[0033] As an example, four plug-in areas are described. Each plug-in area has 32 metal clips arranged horizontally. The insulating covers of the first plug-in area 12 and the third plug-in area 14 each include 32 x 5 plug-in holes 10, i.e., the plug-in holes are divided into 5 rows and 32 columns, each column of plug-in holes 10 corresponds to a metal clip, and 32 columns of plug-in holes 10 correspond to 32 metal clips. Similarly, the insulating plastic covers of the second plug-in area 13 and the fourth plug-in area 15 each include 32 x 4 plug-in holes 10, i.e., the plug-in holes are divided into 4 rows and 32 columns, each column of plug-in holes 10 corresponds to a metal clip, and 32 columns of plug-in holes 10 correspond to 32 metal clips. It should be understood that the number of plug-in areas is not limited to four, but can be fewer or more. The number of metal clips in a single plug-in area is not limited to 32, and can be, for example, 16 or 64. The number of plug-in holes 10 in a column corresponding to a single metal clip is not limited to 4 or 5, and can be, for example, 3 or 6. The above values and arrangements can be flexibly adjusted as needed and are not overly limited here.
[0034] During use, the package plate with the bare chip affixed is placed on top of the insulating cover and electrically connected to the metal clip below. The substrate 1 is then placed on the ESD simulator, electrically connecting the metal clip to the simulator, thereby enabling power supply testing of the bare chip. Furthermore, the substrate 1 has positioning holes at the corners to serve as alignment marks when placing the substrate 1 in the ESD simulator. Once the substrate 1 is in place, the ESD test can begin.
[0035] Specifically, different types of packaging boards have different connection modes with the substrate 1 .
[0036] As an implementation method, Figure 1As shown, the package board is a DIP board (dual in-line package) with a pin header. The DIP board can be directly plugged into the plug-in hole to be electrically connected to the metal clip.
[0037] As another embodiment, Figure 3 As shown, the packaging board is a COB board (Chip On Board). The COB board is electrically connected to the metal clip via a spring pin header 9. In the prior art, the bare chip is packaged quickly so that the pin base on the bare chip is pulled onto the COB board and fixed, and then the pins on the COB board are directly connected to the electrostatic simulator channel. This can also achieve the effect of fixing and protecting the bare chip, and avoid cracking and damage caused by human contact. However, this test method requires manually soldering the pin headers to the pins on the COB board and then connecting them to the electrostatic simulator channel. In addition to consumables and low work efficiency, this method is also prone to the risk of damaging the bare chip. In one embodiment, as Figure 2 As shown, the spring pin header 9 provided in this application includes multiple vertically arranged spring pins. The lower end of the spring pin is used to pass through the plug-in hole to electrically contact the metal clip, and the upper end of the spring pin is formed with a spherical contact point for electrically contacting the bare chip. The middle part of the spring pin is spring-shaped, allowing the pin to expand and contract to a limited extent. The upper end contacts the bare chip PCB board, and the lower end is inserted into the substrate plug-in area. Multiple vertically arranged spring pins are arranged in an array, and the arrangement spacing of the spring pins corresponds to the arrangement spacing of the plug-in hole 10, so that each spring pin can smoothly pass through the plug-in hole 10. As an example, the spacing between adjacent spring pins is 2.54mm, and 32 spring pins form a spring pin header.
[0038] Furthermore, the connector also includes a trace 4, and each metal clip in at least one plug-in area (preferably located on the outermost side) is connected to the electrostatic simulator channel contact point 3 through the trace 4, and forms an electrical connection with the electrostatic simulator through the contact point 3, thereby realizing power supply for the test of the bare chip.
[0039] Furthermore, the connector further comprises a zero impedance jumper 11, which is used to connect the metal clips of adjacent plug-in areas in series, and the metal clips of adjacent plug-in areas connected by the zero impedance jumper 11 are located in the same column. Figure 1 and 3As shown, the metal clips in the same column of the first and second plug-in areas 12 and 13 are connected in series via a zero-impedance jumper 11. This connection allows both plug-in areas to be powered simultaneously, allowing each of the 64 test pin groups, totaling 64 groups, to be connected in series with the ESD simulator channels. Alternatively, the third and fourth plug-in areas 14 and 15 can be connected in series, or all three plug-in areas can be connected in series. This flexibility is achieved based on practical needs and will not be further detailed here.
[0040] In the prior art, when it is necessary to add components and circuits to the periphery of a bare chip, the number of components and circuit complexity to be added is limited due to the area of the COB board. In addition, the existing DIP-type fixtures also encounter the same problem: there is no extra space on the periphery, making it difficult to conduct tests under other special and complex planned circuits, which in turn causes subsequent experimental results to differ from the expected results. To this end, the plug-in holes in the plug-in area provided in this application can also be plugged with additional circuit elements. The additional circuit elements include wires, resistors, capacitors, inductors and other devices, so that the circuit design can be quickly completed in a solder-free manner. Diverse circuit designs can be used to achieve diverse testing of bare chips. At the same time, components will not be damaged when modifying the circuit, achieving a time-saving effect.
[0041] The connector further includes a clamp assembly comprising screws 6 vertically fixed to both sides of the edge of the substrate 1. The screws 6 are secured to the substrate 1 via screw holders 5 at their bottoms. A clamp cover 8 spans the plug-in area and is connected to the screws 6 via through-holes 16. A clamp cover 8 is pressed downward by a clamp screw 7 mounted on the screws 6, thereby pressing the package board and spring pin header 9 against the substrate 1.
[0042] Furthermore, the clamp cover 8 is provided with a through hole to accommodate the bare chip on the packaging board to avoid damage to the bare chip.
[0043] As an example, take one of the above connector embodiments as an example to illustrate its use process: Figure 3 , insert two groups of spring pin headers 9 with 32 spring pins into the first plug-in area 12 and the third plug-in area 14 of the substrate 1 respectively. The plug-in positions and relative distances of the two groups of pin headers can be adjusted according to the sample.
[0044] Place the COB board with the bare chip on the spring pin header 9, pass the through holes 16 in the clamp cover 8 through the screws 6 on both sides and place it on the COB board, tighten the down screws 7 on both sides to tightly combine and fix the clamp cover 8, COB board and spring pin header 9, place the substrate 1 on the electrostatic simulator and align it with the electrostatic simulator PCB test board through the positioning hole 2, then start powering on and performing the electrostatic test.
[0045] If a DIP board is used, it can be directly inserted into the plug-in area of the substrate 1. Then, the substrate 1 is placed on the electrostatic simulator and aligned with the electrostatic simulator PCB test board through the positioning hole 2 to start the electrostatic test.
[0046] Furthermore, whether it is a bare chip COB board with spring pin headers or a DIP board, those who need to add external circuits can utilize plug-in area 12, plug-in area 2 13, plug-in area 3 14, and plug-in area 4 15 of the substrate 1 to freely arrange the placement of components and wires according to the design diagram, achieving a solder-free method and quickly completing circuit design.
[0047] In summary, the connector for bare chip testing provided by the above embodiments of the present invention has one or more of the following beneficial effects:
[0048] 1. Use spring pin headers to achieve solder-free pin headers on COB boards.
[0049] 2. Not limited by the area of COB board or other fixtures, components and wire placement can be freely matched to achieve the purpose of soldering-free and quick completion of circuit design.
[0050] 3. The substrate can be applied to chips of package types such as COB board and DIP board, eliminating the need to redesign the test base and achieving multi-purpose functions.
[0051] 4. The substrate is equipped with contact points with the electrostatic simulator channel, which can easily measure and verify whether the energy output from the machine to the substrate is normal before testing, ensuring the test quality and accuracy.
[0052] The design of this base board can solve the problems encountered in the existing testing of bare chip rapid packaging COB boards. When spring pin headers are not used, it can also support general DIP-style test fixtures. The test socket does not need to be redesigned or modified, achieving the purpose of hardware multi-function.
[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed in the present invention are intended to be covered by the claims of the present invention.
Claims
1. A connector for bare chip testing, characterized in that: It includes a base plate, a metal clip and an insulating cover, wherein: The substrate surface includes at least one plug-in area, and the plug-in area is fixed with a plurality of the metal clips arranged at intervals; The insulating cover is provided above the plug-in area and is provided with a plurality of plug-in holes. A row of plug-in holes corresponds to a row above each metal clip. The row of plug-in holes includes at least one plug-in hole. Any plug-in hole in the same row can be electrically connected to the metal clip below it. The substrate is provided with a plurality of electrical connection points, and the plurality of electrical connection points can be electrically connected to the electrostatic simulator when the substrate is placed in the electrostatic simulator.
2. The connector for bare chip testing according to claim 1, wherein: The connector includes a plurality of plug-in areas arranged along one direction.
3. The connector for bare chip testing according to claim 2, wherein: The arrangement direction of the metal clips is perpendicular to the arrangement direction of the plurality of plug-in areas.
4. The connector for bare chip testing according to any one of claim 1, wherein: The connector further includes a zero-impedance jumper wire for connecting metal clips between adjacent plug-in areas in series one by one.
5. The connector for bare chip testing according to claim 1, wherein: The connector further includes a spring pin header, which includes a plurality of vertically arranged spring pins. The lower ends of the spring pins are used to pass through the plug-in holes and electrically connect to the metal clip, and the upper ends of the spring pins are used to electrically connect to the bare chip.
6. The connector for bare chip testing according to any one of claim 1, characterized in that: The connector further includes a plurality of wirings, and the plurality of metal clips in at least one of the plug-in areas are respectively connected to the plurality of electrical connection points via a wiring.
7. The connector for bare chip testing according to claim 1, wherein: The plug-in holes in the plug-in area are further plugged with external circuit elements, which include wires, resistors, capacitors, and inductors.
8. The connector for bare chip testing according to claim 1, wherein: The connector also includes a press-down clamp assembly, which includes: screws vertically fixed on the opposite side edges of the substrate, and the screws are fixed to the substrate through screw fixing seats at the bottom thereof; a clamp cover spanning the plug-in area and connected to the screws through through holes; and a press-down screw threadedly connected to the screw to press the clamp cover downward.
9. The connector for bare chip testing according to claim 8, wherein: The clamp cover is provided with a through hole for accommodating the bare chip on the packaging board.
10. The connector for bare chip testing according to claim 1, wherein: Positioning holes are provided at the corners of the substrate to serve as alignment marks when the substrate is placed on the electrostatic simulator.