Display device

Abstract

A display device includes: a light emitting element; a first transistor connected between the driving voltage line and the anode electrode of the light emitting element; a second transistor connected between a data line and a gate electrode of the first transistor; a third transistor connected between a source electrode of the first transistor and the driving voltage line; a fourth transistor connected between a drain electrode of the first transistor and an initialization voltage line; and a first capacitor connected between the gate electrode of the first transistor and the gate electrode of the fourth transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived therefrom from Korean Patent Application No. 10-2023-0106705, filed on August 16, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device in which degradation of image quality can be minimized despite degradation of a light emitting element. Background Art

[0004] A head-mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet and focuses in front of the user's eyes at a distance close to the user's eyes. HMDs can implement virtual reality (VR) or augmented reality (AR).

[0005] HMDs use multiple lenses to magnify and display images displayed by a small display device. Therefore, the display device applied to the HMD needs to provide high-resolution images, for example, images with a resolution of 3,000 pixels per inch ("PPI") or higher. To this end, organic light-emitting diodes on silicon ("OLEDoS"), which are small organic light-emitting display devices with high resolution, have been used as display devices applied to HMDs. OLEDoS is a device that displays images by disposing an organic light-emitting diode ("OLED") on a semiconductor wafer substrate on which a complementary metal oxide semiconductor ("CMOS") is disposed. Utility Model Content

[0006] Features of the present disclosure provide a display device in which degradation of image quality can be minimized despite degradation of a light emitting element.

[0007] In an embodiment of the present disclosure, a display device includes: a light-emitting element; a first transistor connected between a driving voltage line and an anode electrode of the light-emitting element; a second transistor connected between a data line and a gate electrode of the first transistor; a third transistor connected between a source electrode of the first transistor and the driving voltage line; a fourth transistor connected between a drain electrode of the first transistor and an initialization voltage line; and a first capacitor connected between the gate electrode of the first transistor and the gate electrode of the fourth transistor.

[0008] In an embodiment, the display device may further include a second capacitor connected between the gate electrode of the first transistor and the source electrode of the first transistor.

[0009] In an embodiment, the display device may further include a third capacitor connected between the gate electrode of the first transistor and the drain electrode of the first transistor.

[0010] In an embodiment, the capacitance of the first capacitor may be greater than the capacitance of the third capacitor, and the capacitance of the third capacitor is greater than the capacitance of the second capacitor.

[0011] In an embodiment, the capacitance of the third capacitor may be 31.3% of the capacitance of the second capacitor, and the capacitance of the first capacitor may be 18.8% of the capacitance of the second capacitor.

[0012] In an embodiment, the display device may further include: a first scan line connected to the gate electrode of the second transistor; an emission control line connected to the gate electrode of the third transistor; and a second scan line connected to the gate electrode of the fourth transistor.

[0013] In an embodiment, in an initialization / writing period, the emission control signal of the emission control line, the first scan signal of the first scan line, and the second scan signal of the second scan line may each have a valid level, in a compensation period, the first scan signal and the second scan signal may each have a valid level, in a bypass period, the emission control signal and the second scan signal may each have a valid level, and the first scan signal may have a non-valid level, and in an emission period, the emission control signal may have a valid level, and the first scan signal and the second scan signal may each have a non-valid level.

[0014] In an embodiment, a previous data voltage may be applied to the data line in the initialization / write period and the compensation period, a current data voltage may be applied to the data line in the emission period, and a transient data voltage converted from the previous data voltage to the current data voltage may be applied to the data line in the bypass period.

[0015] In an embodiment, at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor may include a body electrode connected to the driving voltage line.

[0016] In an embodiment, the initialization voltage of the initialization voltage line may be lower than the driving voltage of the driving voltage line.

[0017] In an embodiment, the display device may further include a common voltage line connected to the cathode electrode of the light emitting element.

[0018] In an embodiment, the initialization voltage of the initialization voltage line may be higher than the common voltage of the common voltage line.

[0019] In an embodiment of the present disclosure, a display device includes: a light-emitting element; a first transistor connected between a driving voltage line and an anode electrode of the light-emitting element; a fourth transistor connected between a drain electrode of the first transistor and an initialization voltage line; and a first capacitor connected between a gate electrode of the first transistor and a gate electrode of the fourth transistor.

[0020] In an embodiment, the display device may further include: a second transistor connected between a data line and the gate electrode of the first transistor; and a third transistor connected between a source electrode of the first transistor and the driving voltage line.

[0021] In an embodiment, the display device may further include a second capacitor connected between the gate electrode of the first transistor and the source electrode of the first transistor.

[0022] In an embodiment, the display device may further include a third capacitor connected between the gate electrode of the first transistor and the drain electrode of the first transistor.

[0023] In an embodiment, the capacitance of the first capacitor may be greater than the capacitance of the third capacitor, and the capacitance of the third capacitor may be greater than the capacitance of the second capacitor.

[0024] In an embodiment, the capacitance of the third capacitor may be 31.3% of the capacitance of the second capacitor, and the capacitance of the first capacitor may be 18.8% of the capacitance of the second capacitor.

[0025] In an embodiment, the display device may further include: a first scan line connected to the gate electrode of the second transistor; an emission control line connected to the gate electrode of the third transistor; and a second scan line connected to the gate electrode of the fourth transistor.

[0026] In an embodiment, in an initialization / writing period, the emission control signal of the emission control line, the first scan signal of the first scan line, and the second scan signal of the second scan line may each have a valid level, in a compensation period, the first scan signal and the second scan signal may each have a valid level, in a bypass period, the emission control signal and the second scan signal may each have a valid level and the first scan signal may have a non-valid level, and in an emission period, the emission control signal may have a valid level and the first scan signal and the second scan signal may each have a non-valid level.

[0027] In an embodiment, a previous data voltage may be applied to the data line in the initialization / write period and the compensation period, a current data voltage may be applied to the data line in the emission period, and a transient data voltage converted from the previous data voltage to the current data voltage may be applied to the data line in the bypass period.

[0028] In an embodiment, at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor may include a body electrode connected to the driving voltage line.

[0029] With the display device according to the present disclosure, even if the light-emitting element degrades, the rate of change of the gate voltage of the first transistor is reduced by the first capacitor, and thus, the amount of luminance reduction can be minimized. Therefore, despite the degradation of the light-emitting element, the degradation of the image quality of the display device can be minimized.

[0030] The effects of the present disclosure are not limited to the above-described effects, and other effects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other advantages and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is an exploded perspective view showing an embodiment of a display device;

[0033] Figure 2 It shows Figure 1 A layout diagram of an embodiment of a display panel shown in FIG;

[0034] Figure 3 is a block diagram illustrating an embodiment of a display device;

[0035] Figure 4 is an equivalent circuit diagram of an embodiment of a first pixel;

[0036] Figure 5 is a layout diagram showing an embodiment of pixels of a display area;

[0037] Figure 6 It is shown along Figure 5 A cross-sectional view of an embodiment of a display device taken along line AA';

[0038] Figure 7 is a perspective view illustrating an embodiment of a head-mounted display ("HMD") device;

[0039] Figure 8 It shows Figure 7 An exploded perspective view of an embodiment of an HMD device;

[0040] Figure 9 is a perspective view showing another embodiment of an HMD device;

[0041] Figure 10 yes Figure 4 A timing diagram of a first scanning signal, a second scanning signal, an emission control signal and an initialization voltage;

[0042] Figure 11 is used to describe Figure 10 FIG. 1 is a diagram illustrating the operation of the display device during an initialization / writing period;

[0043] Figure 12 is used to describe Figure 10 a diagram showing the operation of the display device during a compensation period;

[0044] Figure 13 is used to describe Figure 10 a diagram showing operation of the display device during a bypass period; and

[0045] Figure 14 is used to describe Figure 10 A diagram illustrating the operation of the display device during an emission period. DETAILED DESCRIPTION

[0046] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0047] It will be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0048] Although the terms "first", "second" etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. Terms "first", "second" etc. can also be used to distinguish elements of different categories or groups in this article. For simplicity, the terms "first", "second" etc. can respectively represent "first class (or first group)", "second class (or second group)" etc.

[0049] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to be limiting. As used in this article, unless the content clearly states otherwise, the singular forms "one", "one (person / kind)" and "the (said)" are intended to include the plural forms comprising "at least one (person / kind)". "Or" means "and / or". As used in this article, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the terms "include" and / or "comprise" or "contain" and / or "containing" are used in this specification, it is explained that there are stated features, regions, wholes, steps, operations, elements and / or components, but the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0050] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the accompanying drawings is turned over, an element described as being "on the "lower" side of the other elements will subsequently be oriented as being "on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations depending on the specific orientation of the drawings. Similarly, if the device in one of the accompanying drawings is turned over, an element described as being "below" or "beneath" another element will subsequently be oriented as being "above" the other element. Thus, the exemplary terms "lower" or "beneath" can cover both "upper" and "lower" orientations.

[0051] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable deviation of the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). Terms such as "about" can mean within one or more standard deviations, or within, for example, ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0053] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. The various embodiments may be practiced individually or in combination.

[0054] Hereinafter, predetermined embodiments will be described with reference to the accompanying drawings.

[0055] Figure 1 is an exploded perspective view showing an embodiment of a display device. Figure 2 It shows Figure 1 Layout diagram of an embodiment of a display panel shown in . Figure 3 is a block diagram illustrating an embodiment of a display device.

[0056] Reference Figure 1 、 Figure 2 and Figure 3 , the display device 10 in the embodiment is a device that displays moving images or still images. The display device 10 in the embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players ("PMP"), navigation devices, and ultra-mobile personal computers ("UMPC"). In an embodiment, the display device 10 can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things ("IoT") device. In an alternative embodiment, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display ("HMD") for realizing virtual reality and augmented reality.

[0057] The display device 10 in the embodiment includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 and a driving circuit 450 .

[0058] In a plan view, the display panel 100 may have a shape similar to a quadrilateral shape (e.g., a rectangular shape). In an embodiment, in a plan view, the display panel 100 may have a shape similar to a quadrilateral shape (e.g., a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1). In the display panel 100, for example, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a rounded shape or a right angle with a predetermined curvature. The shape of the display panel 100 in a plan view is not limited to a quadrilateral shape such as a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10 in a plan view may follow the shape of the display panel 100 in a plan view, but the present disclosure is not limited thereto.

[0059] like Figure 3 As shown in , the display panel 100 may include a display area DAA displaying an image and a non-display area NDA not displaying an image.

[0060] The display area DAA may include a plurality of pixels PX, a plurality of scan lines SL1 and SL2 , a plurality of emission control lines EML, and a plurality of data lines DL.

[0061] Each of the plurality of pixels PX includes a light-emitting element that emits light. The plurality of pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2. A plurality of scan lines and a plurality of emission control lines may extend in the first direction DR1 and may be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0062] The plurality of scan lines include a plurality of first scan lines SL1 and a plurality of second scan lines SL2. The plurality of emission control lines EML include a plurality of first emission control lines and a plurality of second emission control lines.

[0063] Multiple unit pixels UPX (refer to Figure 5 ) includes a plurality of pixels PX1, PX2 and PX3 (refer to Figure 6 ). The plurality of pixels PX1, PX2, and PX3 may include a plurality of pixel transistors (eg, Figure 4 The plurality of pixel transistors may be formed by a semiconductor process and disposed on a semiconductor substrate (eg, Figure 6 In an embodiment, for example, a plurality of pixel transistors may be formed as a complementary metal oxide semiconductor ("CMOS").

[0064] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of the plurality of first scan lines SL1, any one of the plurality of second scan lines SL2, any one of the plurality of emission control lines EML, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive a data voltage of the data line DL according to a first scan signal of the first scan line SL1 and can cause the light emitting element to emit light according to the data voltage.

[0065] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0066] The scan driving area SDA may be a region in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 6 shows that the scan driver 610 is provided on the left side of the display area DAA, and the emission driver 620 is provided on the right side of the display area DAA, but the present disclosure is not limited thereto. In an embodiment, for example, both the scan driver 610 and the emission driver 620 may be provided on the left or right side of the display area DAA.

[0067] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors can be formed by a semiconductor process and can be formed on the above-mentioned semiconductor substrate. In an embodiment, for example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed as CMOS.

[0068] The scan driver 610 may include a first scan signal output unit 611 and a second scan signal output unit 612. Each of the first scan signal output unit 611 and the second scan signal output unit 612 may receive a scan timing control signal SCS from the timing controller 400. The first scan signal output unit 611 may generate a first scan signal based on the scan timing control signal SCS from the timing controller 400 and may sequentially output the first scan signal to the first scan line SL1. The second scan signal output unit 612 may generate a second scan signal based on the scan timing control signal SCS and may sequentially output the second scan signal to the second scan line SL2.

[0069] The emission driver 620 may receive the emission timing control signal ECS from the timing controller 400. Also, the emission driver 620 may generate emission control signals according to the emission timing control signal ECS and sequentially output the emission control signals to the emission control lines EML.

[0070] The data driving area DDA may be an area in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors. The plurality of data transistors may be formed by a semiconductor process and may be formed on the semiconductor substrate described above. In an embodiment, for example, the plurality of data transistors may be formed as CMOS.

[0071] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 converts the digital video data DATA into an analog data voltage (also referred to as a data voltage) according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the first scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0072] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer CVL (refer to FIG. Figure 6 ) and a polarizing plate (not shown).

[0073] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is a thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface (e.g., a rear surface) of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer including graphite, silver (Ag), copper (Cu), or aluminum (Al) having relatively high thermal conductivity.

[0074] The circuit board 300 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 1 100 has been shown as being unbent, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be an end opposite to an opposite end of the plurality of pads PD of the circuit board 300 connected to the pad area PDA of the display panel 100 using a conductive adhesive member.

[0075] The driving circuit 450 may include a timing controller 400 and a power supply unit 500 .

[0076] The timing controller 400 can receive digital video data DATA and timing signals from the outside. The timing controller 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 based on the timing signals. The timing controller 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing controller 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0077] The power supply unit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. In an embodiment, for example, the power supply unit 500 may generate a common voltage ELVSS, a driving voltage ELVDD, and an initialization voltage Vint, and supply the common voltage ELVSS, the driving voltage ELVDD, and the initialization voltage Vint to the display panel 100. Figure 4 The common voltage ELVSS, the driving voltage ELVDD, and the initialization voltage Vint are described.

[0078] Each of the timing controller 400 and the power supply unit 500 may be formed as an integrated circuit ("IC") and attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller 400 may be supplied to the display panel 100 through the circuit board 300. The common voltage ELVSS, the driving voltage ELVDD, and the initialization voltage Vint of the power supply unit 500 may be supplied to the display panel 100 through the circuit board 300.

[0079] Figure 4 is an equivalent circuit diagram of an embodiment of a first pixel.

[0080] like Figure 4 As shown in, also refer to Figure 3 and Figure 6 , pixel PX (e.g., Figure 6 The first pixel PX1 shown in FIG can be connected to a first scan line SL1, a second scan line SL2, an emission control line EML, an initialization voltage line VIL, a data line DL, a driving voltage line VDL, and a common voltage line VSL. Here, the common voltage line VSL can be connected to a common electrode (e.g., a cathode electrode) of the light emitting element ED.

[0081] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0082] The pixel circuit PC may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a first capacitor C1 , a second capacitor C2 , and a third capacitor C3 .

[0083] The first transistor T1 (e.g., a driving transistor) may include a gate electrode, a source electrode, a drain electrode, and a body electrode. The first transistor T1 may control a source-drain current (hereinafter, referred to as a driving current) according to a data voltage Vdt applied to the gate electrode. A driving current (e.g., a driving current Isd) flowing through a channel region of the first transistor T1 may be proportional to the square of a difference between a voltage Vsg between the source electrode and the gate electrode and a threshold voltage Vth of the first transistor T1 (Isd=k×(Vsg-Vth)). 2 ). Here, k represents a proportionality coefficient determined by the structure and physical properties of the first transistor T1, Vsg represents a source-gate voltage of the first transistor T1, and Vth represents a threshold voltage of the first transistor T1. A gate electrode of the first transistor T1 may be electrically connected to a first node N1, a source electrode of the first transistor T1 may be electrically connected to a second node N2, a drain electrode of the first transistor T1 may be electrically connected to a third node N3, and a body electrode of the first transistor T1 may be electrically connected to a driving voltage line VDL to receive a driving voltage ELVDD.

[0084] The light-emitting element ED can receive a driving current Isd to emit light. The amount of light emitted or the brightness of the light-emitting element ED can be proportional to the magnitude of the driving current Isd. The light-emitting element ED can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED can be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED can be a micro light-emitting diode. The first electrode of the light-emitting element ED can be connected to a third node N3. The second electrode of the light-emitting element ED can be connected to a common voltage line VSL. The second electrode of the light-emitting element ED can receive a common voltage ELVSS (e.g., a relatively low potential voltage) from the common voltage line VSL.

[0085] The second transistor T2 can be turned on by the first scan signal SS1 of the first scan line SL1 to electrically connect the data line DL and the first node N1 to each other. The gate electrode of the second transistor T2 can be electrically connected to the first scan line SL1, the source electrode of the second transistor T2 can be electrically connected to the data line DL, the drain electrode of the second transistor T2 can be electrically connected to the first node N1, and the body electrode of the second transistor T2 can be electrically connected to the driving voltage line VDL. The data line DL can transmit a data voltage Vdt or a reference voltage Vref.

[0086] The third transistor T3 can be turned on by the emission control signal EM of the emission control line EML to electrically connect the driving voltage line VDL and the second node N2 to each other. A gate electrode of the third transistor T3 can be electrically connected to the emission control line EML, a source electrode of the third transistor T3 can be electrically connected to the driving voltage line VDL, a drain electrode of the third transistor T3 can be electrically connected to the second node N2, and a body electrode of the third transistor T3 can be electrically connected to the driving voltage line VDL.

[0087] The fourth transistor T4 can be turned on by the second scan signal SS2 of the second scan line SL2 to electrically connect the third node N3 and the initialization voltage line VIL to each other. The gate electrode of the fourth transistor T4 can be electrically connected to the second scan line SL2, the source electrode of the fourth transistor T4 can be electrically connected to the third node N3, the drain electrode of the fourth transistor T4 can be electrically connected to the initialization voltage line VIL, and the body electrode of the fourth transistor T4 can be electrically connected to the drive voltage line VDL. The number of initialization voltage lines VIL can be multiple, and the multiple initialization voltage lines VIL can be connected to each other. In an embodiment, for example, the initialization voltage lines VIL can include a plurality of horizontal initialization voltage lines extending along the first direction DR1 and arranged in the second direction DR2, and a plurality of vertical initialization voltage lines extending along the second direction DR2 and arranged along the first direction DR1, and the horizontal initialization voltage lines and the vertical initialization voltage lines can be connected to each other.

[0088] The first capacitor C1 may be electrically connected between the first node N1 and the second node N2. In an embodiment, for example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the second node N2.

[0089] The second capacitor C2 may be electrically connected between the first node N1 and the third node N3. In an embodiment, for example, a first electrode of the second capacitor C2 may be electrically connected to the first node N1, and a second electrode of the second capacitor C2 may be electrically connected to the third node N3.

[0090] The third capacitor C3 may be electrically connected between the first node N1 and the second scan line SL2. In an embodiment, for example, a first electrode of the third capacitor C3 may be electrically connected to the first node N1, and a second electrode of the third capacitor C3 may be electrically connected to the second scan line SL2.

[0091] The third capacitor C3 may have a capacitance greater than that of the second capacitor C2, and the second capacitor C2 may have a capacitance greater than that of the first capacitor C1. In other words, the capacitance of the second capacitor C2 may be greater than that of the first capacitor C1 and less than that of the third capacitor C3.

[0092] In a pixel circuit PC, the capacitance ratio between the first capacitor C1 to the third capacitor C3 is as follows. In an embodiment, for example, when the capacitance of the first capacitor C1 is 100%, the capacitance of the second capacitor C2 can be 31.3%, and the capacitance of the third capacitor C3 can be 18.8%. In other words, based on the capacitance of the first capacitor C1, the capacitance of the second capacitor C2 can be set to 31.3% of the capacitance of the first capacitor C1, and the capacitance of the third capacitor C3 can be set to 18.8% of the capacitance of the first capacitor C1.

[0093] When the first transistor T1 and the third transistor T3 are turned on, the driving current Isd is supplied to the light emitting element ED, so that the light emitting element ED can emit light.

[0094] At least one of the first to fourth transistors T1 to T4 may be a metal oxide semiconductor field effect transistor ("MOSFET"). In an embodiment, each of the first to fourth transistors T1 to T4 may be a P-type MOSFET. In another embodiment, each of the first to fourth transistors T1 to T4 may be an N-type MOSFET. In another embodiment, some of the first to fourth transistors T1 to T4 may be P-type MOSFETs, and the remaining transistors of the first to fourth transistors T1 to T4 may be N-type MOSFETs.

[0095] Figure 4 FIG. 4 shows that the first pixel PX1 includes four transistors T1 to T4 and three capacitors C1, C2 and C3, but it is noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 4 In the embodiment, for example, the number of transistors and capacitors of the first pixel PX1 is not limited to Figure 4 The quantity shown in .

[0096] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be compared with the reference circuit diagram of FIG. Figure 4The equivalent circuit diagram of the first pixel PX1 is substantially the same as that of the first pixel PX1 , and therefore, descriptions of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 are omitted in the present disclosure.

[0097] Figure 5 FIG. 1 is a layout diagram showing an embodiment of pixels in a display area.

[0098] Reference Figure 5 , also refer to Figure 3 and Figure 6 , each of the plurality of pixels PX may include a first emission area EA1 as an emission area of a first pixel PX1, a second emission area EA2 as an emission area of a second pixel PX2, and a third emission area EA3 as an emission area of a third pixel PX3.

[0099] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape in a plan view, such as a quadrilateral shape such as a rectangular shape, a square shape, or a diamond shape. In an embodiment, for example, the first emission area EA1 may have a quadrilateral shape in a plan view (e.g., a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2). In addition, each of the second emission area EA2 and the third emission area EA3 may have a quadrilateral shape in a plan view (e.g., a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2).

[0100] The length of the first emission region EA1 in the first direction DR1 may be smaller than the length of the second emission region EA2 in the first direction DR1, and may be smaller than the length of the third emission region EA3 in the first direction DR1. The length of the second emission region EA2 in the first direction DR1 and the length of the third emission region EA3 in the first direction DR1 may be substantially the same as each other.

[0101] The length of the first emission area EA1 in the second direction DR2 may be greater than the sum of the lengths of the second emission area EA2 and the third emission area EA3 in the second direction DR2. The length of the second emission area EA2 in the second direction DR2 may be greater than the length of the third emission area EA3 in the second direction DR2.

[0102] Despite Figure 5, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 is shown as having a quadrilateral shape in a plan view, but the present disclosure is not limited thereto. In an embodiment, for example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape in a plan view.

[0103] In each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. Furthermore, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the second direction DR2. The area of the first emission area EA1, the area of the second emission area EA2, and the area of the third emission area EA3 may be different from each other.

[0104] The first emission area EA1 can emit light of a first color, the second emission area EA2 can emit light of a second color, and the third emission area EA3 can emit light of a third color. Here, the light of the first color can be light in a blue band, the light of the second color can be light in a green band, and the light of the third color can be light in a red band. In an embodiment, for example, the blue band can refer to a light having a main peak wavelength included in a band of approximately 370 nanometers (nm) to approximately 460 nm, the green band can refer to a light having a main peak wavelength included in a band of approximately 480 nm to approximately 560 nm, and the red band can refer to a light having a main peak wavelength included in a band of approximately 600 nm and approximately 750 nm.

[0105] Figure 5 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may also include four emission areas.

[0106] In addition, the arrangement of the emission regions of the plurality of pixels PX is not limited to Figure 5 In the embodiment, for example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure arranged in the first direction DR1, a diamond arrangement, or a plurality of pixels PX arranged in a plurality of directions. structure or a hexagonal structure in which an emission area having a hexagonal shape is provided in a plan view.

[0107] Figure 6 It is shown along Figure 5 A cross-sectional view of an embodiment of a display device taken along line AA'.

[0108] Reference Figure 6 , also refer to Figure 4 , the display panel 100 may include a semiconductor back panel SBP, a light emitting element back panel EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate.

[0109] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors TRS, a plurality of semiconductor insulating films covering the plurality of pixel transistors TRS, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors TRS. Figure 4 The first to fourth transistors T1 to T4 are described.

[0110] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided in the upper surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the first-type impurities described above. In an embodiment, for example, when the first-type impurities are P-type impurities, the second-type impurities may be N-type impurities. In an alternative embodiment, when the first-type impurities are N-type impurities, the second-type impurities may be P-type impurities.

[0111] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor TRS, a drain region DA corresponding to a drain electrode of the pixel transistor TRS, and a channel region CH disposed between the source region SA and the drain region DA.

[0112] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor TRS may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the opposite side of the gate electrode GE.

[0113] In an embodiment, each of the plurality of well regions WA further includes a first low-concentration impurity region disposed between the channel region CH and the source region SA and a second low-concentration impurity region disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may be a region having an impurity concentration lower than that of the source region SA. The second low-concentration impurity region may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, the length of the channel region CH of each of the pixel transistors TRS may be increased, and thus, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0114] The first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed based on silicon nitride (SiN x ) or silicon oxide (SiO x ) of an inorganic film, but the present disclosure is not limited thereto.

[0115] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be formed based on silicon oxide (SiO x ) of an inorganic film, but the present disclosure is not limited thereto.

[0116] A plurality of contact terminals CTE may be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA of each of the pixel transistors TRS through a hole passing through the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0117] The third semiconductor insulating film SINS3 may be provided on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed based on silicon oxide (SiO x ) of an inorganic film, but the present disclosure is not limited thereto.

[0118] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, the thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0119] The light emitting element back plate EBP may include first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. Furthermore, the light emitting element back plate EBP includes a plurality of interlayer insulating films INS1 to INS10 disposed between the first to sixth metal layers ML1 to ML6.

[0120] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the Figure 4 . The circuit of the first pixel PX1 is shown in FIG. That is, only the first to fourth transistors T1 to T4 are formed in the semiconductor backplane SBP, and the connections between the first to fourth transistors T1 to T4 and the formation of the first, second, and third capacitors C1, C2, and C3 are performed by the first to eighth metal layers ML1 to ML8. Furthermore, the drain region corresponding to the drain electrode of the first transistor T1, the source region corresponding to the source electrode of the fourth transistor T4, and the first electrode of the light-emitting element ED can be connected to each other via the first to eighth metal layers ML1 to ML8.

[0121] A first interlayer insulating film INS1 may be provided on the semiconductor backplane SBP. Each of the first via holes VA1 may pass through the first interlayer insulating film INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be provided on the first interlayer insulating film INS1 and may be connected to the first via holes VA1.

[0122] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second via holes VA2 may pass through the second interlayer insulating film INS2 to be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second via holes VA2.

[0123] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third via holes VA3 may pass through the third interlayer insulating film INS3 to be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third via holes VA3.

[0124] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth via holes VA4 may pass through the fourth interlayer insulating film INS4 to be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth via hole VA4.

[0125] A fifth interlayer insulating film INS5 may be provided on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth via holes VA5 may pass through the fifth interlayer insulating film INS5 to be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be provided on the fifth interlayer insulating film INS5 and may be connected to the fifth via hole VA5.

[0126] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth via holes VA6 may pass through the sixth interlayer insulating film INS6 to be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the sixth via hole VA6.

[0127] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh via holes VA7 may pass through the seventh interlayer insulating film INS7 to be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh via hole VA7.

[0128] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth via holes VA8 may pass through the eighth interlayer insulating film INS8 to be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via hole VA8.

[0129] The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may include substantially the same material as each other or consist of substantially the same material as each other. Each of the first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy thereof, or may consist of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy thereof. The first via hole VA1 to the eighth via hole VA8 may include substantially the same material as each other or consist of substantially the same material as each other. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed as a silicon oxide (SiO x ) of an inorganic film, but the present disclosure is not limited thereto.

[0130] Each of the thicknesses of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than each of the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. Each of the thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be substantially the same as each other. In an embodiment, for example, the thickness of the first metal layer ML1 may be approximately 1360 angstroms. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be approximately And each of the thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6 may be approximately

[0131] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other. In an embodiment, for example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be approximately Each of the thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8 may be approximately

[0132] The ninth interlayer insulating film INS9 may be provided on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed based on silicon oxide (SiO x ) of an inorganic film, but the present disclosure is not limited thereto.

[0133] Each of the ninth via holes VA9 may pass through the ninth interlayer insulating film INS9 to be connected to the exposed eighth metal layer ML8. Each of the ninth via holes VA9 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the ninth via hole VA9 may be approximately

[0134] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the ninth via hole VA9. Each of the first reflective electrodes RL1 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may consist of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0135] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. Each of the second reflective electrodes RL2 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may consist of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, each of the second reflective electrodes RL2 may include or consist of titanium nitride (TiN).

[0136] In the first pixel PX1, the step layer STPL may be provided on the second reflective electrode RL2. The step layer STPL may not be provided in each of the second pixel PX2 and the third pixel PX3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer of the first pixel PX1 to the fourth reflective electrode RL4, so as to facilitate reflection of the light of the first color emitted from the first light emitting layer of the first pixel PX1. The step layer STPL may be formed based on silicon nitride (SiN x ) or silicon oxide (SiO x ) inorganic film, but the present disclosure is not limited thereto. The thickness of the step layer STPL may be approximately

[0137] In the first pixel PX1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the stepped layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. Each of the third reflective electrodes RL3 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0138] At least one of the first reflective electrode RL1 , the second reflective electrode RL2 , and the third reflective electrode RL3 may be omitted.

[0139] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a relatively high reflectivity to facilitate reflection of light. Each of the fourth reflective electrodes RL4 may include aluminum (Al), a stack structure of aluminum and titanium (Ti / Al / Ti), a stack structure of aluminum and indium tin oxide ("ITO") ("ITO / Al / ITO"), silver (Ag), palladium (Pd), an APC alloy as an alloy of copper (Cu), and a stack structure of an APC alloy and ITO ("ITO / APC / ITO"), or may be composed of aluminum (Al), a stack structure of aluminum and titanium (Ti / Al / Ti), a stack structure of aluminum and indium tin oxide ("ITO") ("ITO / Al / ITO"), silver (Ag), palladium (Pd), an APC alloy as an alloy of copper (Cu), and a stack structure of an APC alloy and ITO ("ITO / APC / ITO"), but the present disclosure is not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be approximately 1000 Å.

[0140] The tenth interlayer insulating film INS10 may be provided on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be formed based on silicon oxide (SiO x ) of an inorganic film, but the present disclosure is not limited thereto.

[0141] Each of the tenth via holes VA10 may pass through the tenth interlayer insulating film INS10 to be connected to the exposed fourth reflective electrode RL4. Each of the tenth via holes VA10 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. Due to the step layer STPL, the thickness of the tenth via hole VA10 in the first pixel PX1 may be less than the thickness of the tenth via hole VA10 in each of the second pixel PX2 and the third pixel PX3. In an embodiment, for example, the thickness of the tenth via hole VA10 in the first pixel PX1 may be approximately And the thickness of the tenth via hole VA10 in each of the second pixel PX2 and the third pixel PX3 may be approximately

[0142] The light emitting element layer EMTL may be disposed on the light emitting element backplane EBP. The light emitting element layer EMTL may include light emitting elements ED and a pixel definition layer PDL, each of the light emitting elements ED including a first electrode AND, an intermediate layer IL, and a second electrode CAT. A plurality of trenches TRC may be defined in the light emitting element layer EMTL.

[0143] The first electrode AND of each light-emitting element ED may be disposed on the tenth interlayer insulating film INS10 and may be connected to the tenth via VA10. The first electrode AND of each light-emitting element ED may be connected to the drain area DA or the source area SA of the pixel transistor TRS through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element ED may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, the first electrode AND of each light-emitting element ED may include or be composed of titanium nitride (TiN).

[0144] A pixel-defining film (PDL) may be disposed on a portion of the first electrode AND of each of the light-emitting elements ED. The pixel-defining film (PDL) may cover the edge of the first electrode AND of each of the light-emitting elements ED. The pixel-defining film (PDL) may be used to partition the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0145] The first emission area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0146] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the light emitting elements ED, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be formed based on silicon oxide (SiO x ) inorganic film, but the present disclosure is not limited thereto. The thickness of each of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be approximately

[0147] Each of the plurality of trenches TRC may pass through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In each of the plurality of trenches TRC, the tenth interlayer insulating film INS10 may have a shape in which a portion of the tenth interlayer insulating film INS10 is a trench.

[0148] At least one trench TRC may be provided between the pixels PX1 , PX2 , and PX3 that are adjacent to each other. Figure 6 It has been illustrated that two trenches TRC are defined between the pixels PX1 , PX2 , and PX3 adjacent to each other, but the present disclosure is not limited thereto.

[0149] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0150] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit different lights. In an embodiment, the intermediate layer IL may include, for example, a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked sequentially.

[0151] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0152] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be provided between the first and second intermediate layers IL1 and IL2. A second charge generation layer for supplying charges to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be provided between the second and third intermediate layers IL2 and IL3.

[0153] The first intermediate layer IL1 can be arranged on the first electrode AND and the pixel definition film PDL, and can be arranged on the bottom surface of each of the grooves TRC. Due to the groove TRC, the first intermediate layer IL1 can be disconnected between the adjacent pixels PX1, PX2 and PX3. The second intermediate layer IL2 can be arranged on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 can be disconnected between the adjacent pixels PX1, PX2 and PX3. The third intermediate layer IL3 can be arranged on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 can be disconnected between the adjacent pixels PX1, PX2 and PX3. That is, each of the multiple grooves TRC can be a structure for disconnecting the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EMTL between the adjacent pixels PX1, PX2 and PX3.

[0154] In order to stably disconnect the first, second, and third intermediate layers IL1, IL2, and IL3 of the light-emitting element layer EMTL between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of trenches TRC may be greater than the height of the pixel-defining film PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel-defining film PDL may refer to the length of the pixel-defining film PDL in the third direction DR3.

[0155] In order to disconnect the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2, and PX3, other structures may be provided instead of the trench TRC. In an embodiment, for example, a partition wall having a reversely tapered shape may be provided on the pixel defining film PDL instead of the trench TRC.

[0156] The number of the intermediate layers IL1, IL2 and IL3 emitting different light is not limited to Figure 6In the embodiment, for example, the intermediate layer IL may include two intermediate layers. In this case, either of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be provided between the two intermediate layers, the charge generation layer being used to supply electrons to either intermediate layer and charge to the other intermediate layer.

[0157] Figure 6 It has been shown that the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 are all arranged in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the present disclosure is not limited to this. In an embodiment, for example, the first intermediate layer IL1 may be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third intermediate layer IL3 may be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2 and the third color filter CF3 of the optical layer OPL may be omitted.

[0158] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed in each of the plurality of trenches TRC on the third intermediate layer IL3. The second electrode CAT may include a transparent conductive material ("TCO") capable of transmitting light therethrough (such as ITO or indium zinc oxide ("IZO")) or a semi-transparent conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)), or may be composed of a transparent conductive material ("TCO") capable of transmitting light therethrough (such as ITO or indium zinc oxide ("IZO")) or a semi-transparent conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the second electrode CAT includes or is composed of a semi-transmissive conductive material, the emission efficiency of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be increased by the microcavity.

[0159] The encapsulation layer TFE may be disposed on the light-emitting element layer EMTL. The encapsulation layer TFE may include at least one inorganic film TFE1 or TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EMTL. Furthermore, the encapsulation layer TFE may include at least one organic film TFE2 to protect the light-emitting element layer EMTL from foreign matter such as dust. In embodiments, the encapsulation layer TFE may include, for example, a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0160] The first encapsulating inorganic film TFE1 may be provided on the second electrode CAT, the encapsulating organic film TFE2 may be provided on the first encapsulating inorganic film TFE1, and the second encapsulating inorganic film TFE3 may be provided on the encapsulating organic film TFE2. The first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 may be formed of silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layers are sequentially stacked with one or more inorganic films. The encapsulating organic film TFE2 may include or consist of a monomer. In an alternative embodiment, the encapsulating organic film TFE2 may be an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0161] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL to each other. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0162] The optical layer OPL may include a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0163] The first color filter CF1 may overlap with the first emission area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color (i.e., light in the blue wavelength band) through the first color filter CF1. The blue wavelength band may be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1 through the first color filter CF1.

[0164] The second color filter CF2 may overlap with the second emission area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color (i.e., light in the green wavelength band) through the second color filter CF2. The green wavelength band may be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 may transmit light of the second color in the light emitted from the second emission area EA2 through the second color filter CF2.

[0165] The third color filter CF3 may overlap with the third emission area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color (i.e., light in a red wavelength band) through the third color filter CF3. The red wavelength band may be approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 may transmit light of the third color in the light emitted from the third emission area EA3 through the third color filter CF3.

[0166] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light directed toward the front surface of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0167] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index such that light travels in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0168] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin layer such as a resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may serve as a packaging substrate. When the cover layer CVL is a polymer resin layer such as a resin, the cover layer CVL may be applied directly to the filling layer FIL.

[0169] A polarizing plate may be provided on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing visibility reduction caused by external light reflection. The polarizing plate may include a linear polarizing plate and a phase delay film. In an embodiment, the phase delay film may be, for example, a λ / 4 plate (quarter wavelength plate), but the present disclosure is not limited thereto. However, when visibility due to external light reflection is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0170] Figure 7 is a perspective view illustrating an embodiment of a head-mounted display ("HMD") device. Figure 8 It shows Figure 7 An exploded perspective view of an embodiment of an HMD device.

[0171] Reference Figure 7 and Figure 8 , also refer to Figure 3 The HMD device 1000 in the embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600 and a connector.

[0172] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figures 1 to 6 The display devices 10 described are substantially the same, and thus description of the first display device 10_1 and the second display device 10_2 is omitted.

[0173] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0174] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first and second display devices 10_1 and 10_2 and the control circuit board 1600.

[0175] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0176] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. In an alternative embodiment, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0177] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 may be provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 configured for the user's left eye and a second eyepiece 1220 configured for the user's right eye. Figure 7 and Figure 8 12 and 1220 are shown as being separately provided, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one eyepiece.

[0178] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0179] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be kept in a state where they are respectively placed on the user's left eye and right eye. When the display device housing 1100 is implemented to have a light weight and a relatively small size, the HMD device 1000 may include Figure 9The eyeglass frame shown in FIG. 1 is not a headband 1300 .

[0180] In addition, the HMD device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus ("USB") terminal, a display port, or a high-definition multimedia interface ("HDMI") terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a wireless fidelity ("WiFi") module, or a Bluetooth module.

[0181] Figure 9 is a perspective view showing another embodiment of an HMD device.

[0182] Reference Figure 9 In another embodiment, the HMD device 1000_1 may be a glasses-type display device in which the display device housing 1200_1 is implemented as a lightweight and relatively small-sized display device. The HMD device 1000_1 in another embodiment may include a display device 10_3, a left eyeglass 1010, a right eyeglass 1020, a support frame 1030, eyeglass frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and the display device housing 1200_1.

[0183] The display device housing 1200_1 may include a display device 10_3, an optical member 1060, and an optical path conversion member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060, converted in the optical path by the optical path conversion member 1070, and provided to the user's right eye through the right-eye lens 1020. Thus, the user may view an augmented reality image in which a virtual image displayed on the display device 10_3 through his / her right eye and a real image viewed through the right-eye lens 1020 are combined with each other.

[0184] Figure 9 1030, but the present disclosure is not limited thereto. In an embodiment, for example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the user's left eye. In an alternative embodiment, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both his / her left and right eyes.

[0185] Figure 10 yes Figure 4A timing diagram of the first scan signal, the second scan signal, the emission control signal and the initialization voltage.

[0186] Reference Figure 10 , also refer to Figure 1 and Figure 4 , as in Figure 10 In the example shown in , the display device 10 may operate based on an initialization / writing period P1 , a compensation period P2 , a bypass period P3 , and an emission period P4 .

[0187] The initialization / write period P1, the compensation period P2, the bypass period P3, and the emission period P4 may correspond to one horizontal period 1H. In other words, one horizontal period 1H may include the initialization / write period P1, the compensation period P2, the bypass period P3, and the emission period P4. Here, the horizontal period 1H may refer to a period for driving pixels (e.g., pixels of a row) arranged along a horizontal direction (e.g., a first direction DR1). Here, pixels of a row may refer to a plurality of pixels commonly connected to one scan line (e.g., a first scan line SL1) and respectively connected to a plurality of different data lines DL.

[0188] The first scan signal SS1, the second scan signal SS2, and the emission control signal EM may each have an active level or an inactive level in each cycle. Here, the active level of each of the signals SS1, SS2, and EM may refer to a voltage level that can turn on the transistor to which the signal is applied. In other words, the signal at the active level may have a voltage value higher than the threshold voltage of the corresponding transistor. In an embodiment, for example, Figure 4 As shown in , when each of the transistors T1 to T4 is a P-type transistor, the active level of each of the signals SS1, SS2, and EM may refer to a relatively low level. The inactive level of each of the signals SS1, SS2, and EM may refer to a voltage level that can turn off the corresponding transistor. In other words, the signal of the inactive level may have a voltage value lower than the threshold voltage of the corresponding transistor. In an embodiment, for example, as Figure 4 As shown in , when each of the transistors T1 to T4 is a P-type transistor, the inactive level of each of the signals SS1, SS2, and EM may refer to a relatively high level. When each of the transistors T1 to T4 is an N-type transistor, the active level of each of the signals SS1, SS2, and EM may refer to a relatively high level, and the inactive level of each of the signals SS1, SS2, and EM may refer to a relatively low level.

[0189] During the initialization / write period P1, the emission control signal EM, the first scan signal SS1, and the second scan signal SS2 may each have an active level. Furthermore, during such an initialization / write period P1, a data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage having a predetermined grayscale (or brightness) for displaying an image. In this case, the data voltage Vdt during such an initialization / write period P1 may be a data voltage Vdt1 of a previous horizontal period (hereinafter referred to as previous data voltage Vdt1).

[0190] In the compensation period P2, the first scan signal SS1 and the second scan signal SS2 may each have an active level. In addition, in the compensation period P2, the previous data voltage Vdt1 may be applied to the data line DL.

[0191] In the bypass period P3, the emission control signal EM and the second scan signal SS2 may each have an active level, and the first scan signal SS1 may have an inactive level. In addition, in the bypass period P3, the data voltage Vdt of the data line DL may be a transient data voltage Vtrs that changes (or transitions) from the previous data voltage Vdt1 to the current data voltage Vdt2.

[0192] During the emission period P4, the emission control signal EM may have an active level, and the first scan signal SS1 and the second scan signal SS2 may each have an inactive level. Furthermore, during the emission period P4, a data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage having a predetermined grayscale (or brightness) for displaying an image. In this case, the data voltage Vdt during such an emission period P4 may be a data voltage Vdt2 of the current horizontal period (also referred to herein as current data voltage Vdt2).

[0193] The above-mentioned initialization voltage Vint may be maintained at a constant level during all periods including the initialization / write period P1, the compensation period P2, the bypass period P3, and the emission period P4. In an embodiment, for example, the initialization voltage Vint may be a direct current ("DC") voltage that always has a constant level regardless of the period. Here, the initialization voltage Vint may be, for example, a DC voltage that is higher than the common voltage ELVSS and lower than the driving voltage ELVDD.

[0194] Will refer to Figures 10 to 14 The operation of the display device in the embodiment of the present disclosure is described. Figures 11 to 14 In FIG, the transistor surrounded by a relatively thick circle is a transistor in the on state, and the transistor surrounded by a gray dotted circle is a transistor in the off state. Figures 11 to 14 The arrows in the figure indicate the flow of current.

[0195] First, refer to Figure 10 and Figure 11 The operation of the display device in the initialization / writing period P1 is described.

[0196] Figure 11 is used to describe Figure 10 FIG4 is a diagram illustrating the operation of the display device during the initialization / writing period.

[0197] like Figure 10 and Figure 11 As shown in , in the initialization / write period P1, the emission control signal EM, the first scan signal SS1, and the second scan signal SS2 may each have an active level. In addition, in the initialization / write period P1, the previous data voltage Vdt1 may be applied to the data line DL.

[0198] The first scan signal SS1 having an active level may be applied to the gate electrode of the second transistor T2 through the first scan line SL1. Thus, the second transistor T2 may be turned on.

[0199] The second scan signal SS2 having an active level may be applied to the gate electrode of the fourth transistor T4 through the second scan line SL2 , and thus the fourth transistor T4 may be turned on.

[0200] The emission control signal EM having an active level may be applied to the gate electrode of the third transistor T3 through the emission control line EML. Thus, the third transistor T3 may be turned on.

[0201] The first transistor T1 may be turned on by the previous data voltage Vdt1 .

[0202] The second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on during the initialization / write period P1, and accordingly, the gate electrode (e.g., the first node N1) of the first transistor T1, the source electrode (e.g., the second node N2) of the first transistor T1, and the drain electrode (e.g., the third node N3) of the first transistor T1 can be initialized. In an embodiment, for example, the previous data voltage Vdt1 from the data line DL can be applied to the first node N1, which is the gate electrode of the first transistor T1, through the turned-on second transistor T2. In addition, the driving voltage ELVDD from the driving voltage line VDL can be applied to the second node N2, which is the source electrode of the first transistor T1, through the turned-on third transistor T3. In addition, the initialization voltage Vint from the initialization voltage line VIL can be applied to the third node N3, which is the drain electrode of the first transistor T1, through the turned-on fourth transistor T4. Therefore, the corresponding voltages of the gate electrode of the first transistor T1, the source electrode of the first transistor T1, and the drain electrode of the first transistor T1 can be initialized. In an embodiment, for example, the gate electrode of the first transistor T1 may be initialized to the previous data voltage Vdt1, the source electrode of the first transistor T1 may be initialized to the driving voltage ELVDD, and the drain electrode of the first transistor T1 (or the anode electrode of the light emitting element ED) may be initialized to the initialization voltage Vint.

[0203] In addition, a current path may be formed between the driving voltage line VDL and the initialization voltage line VIL through the turned-on first transistor T1, and the voltages at the source and drain electrodes of the first transistor T1 may be initialized by the current flowing along the current path.

[0204] Next, we will refer to Figure 10 and Figure 12 The operation of the display device in the compensation period P2 is described.

[0205] Figure 12 is used to describe Figure 10 A diagram illustrating operation of a display device during a compensation period.

[0206] like Figure 10 and Figure 12 As shown in , in the compensation period P2, the first scan signal SS1 and the second scan signal SS2 may each have an active level, and the emission control signal EM may have an inactive level. In addition, in the compensation period P2, the previous data voltage Vdt1 may be applied to the data line DL.

[0207] The first scan signal SS1 having an active level may be applied to the gate electrode of the second transistor T2 through the first scan line SL1. Thus, the second transistor T2 may be turned on.

[0208] The second scan signal SS2 having an active level may be applied to the gate electrode of the fourth transistor T4 through the second scan line SL2 , and thus the fourth transistor T4 may be turned on.

[0209] The emission control signal EM having a non-active level may be applied to the gate electrode of the third transistor T3 through the emission control line EML. Therefore, the third transistor T3 may be turned off.

[0210] The first transistor T1 may be turned on by the previous data voltage Vdt1 .

[0211] During the compensation period P2, the threshold voltage of the first transistor T1 may be stored in the first capacitor C1. In an embodiment, for example, the threshold voltage of the first transistor T1 may be stored in the first capacitor C1 in a source follower manner. In this case, the voltage of the second node N2 may be, for example, a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the previous data voltage Vdt1. During such a compensation period P2, the source electrode and the body electrode of the first transistor T1 are electrically connected to each other, and therefore, the voltage between the body electrode and the source electrode of the first transistor T1 (hereinafter referred to as the body-source voltage) may be 0. In this way, the body-source voltage of the first transistor T1 is 0 during the compensation period P2, and therefore, the ability to compensate for the threshold voltage Vth of the first transistor T1 during the compensation period P2 may be improved.

[0212] Next, we will refer to Figure 10 and Figure 13 The operation of the display device in the bypass period P3 is described.

[0213] Figure 13 is used to describe Figure 10 A diagram showing the operation of the display device during the bypass period.

[0214] like Figure 10 and Figure 13 As shown in , in the bypass period P3, the emission control signal EM and the second scan signal SS2 may each have an active level, and the first scan signal SS1 may have an inactive level. In addition, in the bypass period P3, the data voltage Vdt of the data line DL may be a transient data voltage Vtrs that changes (or transitions) from the previous data voltage Vdt1 to the current data voltage Vdt2.

[0215] The first scan signal SS1 having an inactive level may be applied to the gate electrode of the second transistor T2 through the first scan line SL1. Thus, the second transistor T2 may be turned off.

[0216] The second scan signal SS2 having an active level may be applied to the gate electrode of the fourth transistor T4 through the second scan line SL2 , and thus the fourth transistor T4 may be turned on.

[0217] The emission control signal EM having an active level may be applied to the gate electrode of the third transistor T3 through the emission control line EML. Thus, the third transistor T3 may be turned on.

[0218] The first transistor T1 may be turned on by the previous data voltage Vdt1 .

[0219] During the bypass period P3, the first scan signal SS1 may be changed (or transitioned) from an active level to an inactive level, and thus, the second transistor T2 may be turned on for a short time. In this case, there may be a problem in which an abnormal drive current generated by the transient data voltage Vtrs of the data line DL may be supplied to the light-emitting element ED. Therefore, to prevent such a problem, the fourth transistor T4 may be turned on during such a bypass period P3 to prevent the abnormal drive current generated by the transient data voltage Vtrs from being applied to the light-emitting element ED. In an embodiment, for example, the abnormal drive current generated by the transient data voltage Vtrs may be bypassed to the initialization voltage line VIL through the turned-on fourth transistor T4.

[0220] Next, we will refer to Figure 10 and Figure 14 The operation of the display device in the emission period P4 is described.

[0221] Figure 14 is used to describe Figure 10 A diagram illustrating the operation of the display device during an emission period.

[0222] like Figure 10 and Figure 14 As shown in FIG, in the emission period P4, the emission control signal EM may have an active level, and the first and second scan signals SS1 and SS2 may each have an inactive level. In addition, in the emission period P4, the current data voltage Vdt2 may be applied to the data line DL.

[0223] The first scan signal SS1 having an inactive level may be applied to the gate electrode of the second transistor T2 through the first scan line SL1. Thus, the second transistor T2 may be turned off.

[0224] The second scan signal SS2 having an inactive level may be applied to the gate electrode of the fourth transistor T4 through the second scan line SL2. Thus, the fourth transistor T4 may be turned off.

[0225] The emission control signal EM having an active level may be applied to the gate electrode of the third transistor T3 through the emission control line EML. Thus, the third transistor T3 may be turned on.

[0226] The first transistor T1 may be turned on by the current data voltage Vdt2 .

[0227] A current path from the driving voltage line VDL to the common voltage line VSL may be formed by the turned-on third transistor T3 and the first transistor T1, and a driving current may flow through the current path. Such a driving current is supplied to the light emitting element ED, and the light emitting element ED may emit light by the driving current.

[0228] In the embodiment, even if a change in the voltage of the anode electrode (e.g., the third node N3) (hereinafter referred to as the anode voltage) occurs due to degradation of the light emitting element ED (e.g., a change in the anode voltage that increases in the positive polarity direction), the total capacitance of all capacitors is reduced by the third capacitor C3, and therefore, the change in the voltage of the gate electrode of the first transistor T1 can be reduced. This will be described in detail with reference to the following equation:

[0229] <Equation 1>

[0230] VG1'=(Cc1 / (Cc1+Cc2))×ΔVS+(Cc2 / (Cc1+Cc2))×ΔVA+VG1

[0231] <Equation 2>

[0232] VG2'=VG2+ΔVA×(Cc1 / (Cc1+Cc2+Cc3))+(Cc3 / (Cc1+Cc2+Cc3))×ΔVEB.

[0233] VG1′ and VG1 in Equation 1 refer to the voltage of the gate electrode of the first transistor T1 (hereinafter referred to as the gate voltage) in the pixel including the first capacitor C1 and the second capacitor C2 (for example, the pixel not including the third capacitor C3), VG1 is the gate voltage of the first transistor T1 in a state without the rate of change of the anode voltage, and VG1′ is the gate voltage of the first transistor T1 in a state reflecting the rate of change of the anode voltage.

[0234] In addition, VG2' and VG2 in Equation 2 refer to the voltage of the gate electrode of the first transistor T1 (hereinafter referred to as the gate voltage) in the pixel including the first capacitor C1, the second capacitor C2 and the third capacitor C3 (for example, the pixel also including the third capacitor C3), VG2 is the gate voltage of the first transistor T1 in a state without the rate of change of the anode voltage, and VG2' is the gate voltage of the first transistor T1 in a state reflecting the rate of change of the anode voltage.

[0235] In addition, in Equation 1 and Equation 2, Cc1 may refer to the capacitance of the first capacitor C1, Cc2 may refer to the capacitance of the second capacitor C2, and Cc3 may refer to the capacitance of the third capacitor C3, ΔVS may refer to the rate of change of the voltage of the source electrode of the first transistor T1 (hereinafter referred to as the source voltage), ΔVA may refer to the rate of change of the anode voltage, and ΔVEB may refer to the rate of change of the voltage of the second scan signal SS2.

[0236] According to Equations 1 and 2, the magnitude of VG1' can have a value of approximately 33% of the magnitude of Cc2 / (Cc1+Cc2), and the magnitude of VG2' can have a value of approximately 12.5% of the magnitude of Cc2 / (Cc1+Cc2+Cc3). In other words, as in the embodiment, the gate voltage of the first transistor T1 in the pixel that also includes the third capacitor C3 is lower than the gate voltage of the first transistor T1 in the pixel that does not include the third capacitor C3. When the gate voltage of the first transistor T1 increases when the light-emitting element ED degrades, the drive current provided by the first transistor T1 can decrease. Therefore, when the light-emitting element ED degrades, the amount of brightness reduction of the pixel including the third capacitor C3 can be less than the amount of brightness reduction of the pixel that does not include the third capacitor C3. Therefore, even if the light-emitting element ED degrades, the brightness reduction rate of the display device in the embodiment including the third capacitor C3 is minimized, so that image quality can be improved.

[0237] It will be understood by those skilled in the art that the present disclosure may be implemented in other predetermined forms without changing the technical spirit or essential features of the present disclosure. Therefore, it will be understood that the above-described embodiments are illustrative and not restrictive in all aspects. It will be understood that the scope of the present disclosure is defined by the claims rather than the above detailed description, and that all modifications and variations derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, characterized in that: The display device includes: Light-emitting element; a first transistor connected between a driving voltage line and the anode electrode of the light emitting element; a second transistor connected between the data line and the gate electrode of the first transistor; a third transistor connected between the source electrode of the first transistor and the driving voltage line; a fourth transistor connected between the drain electrode of the first transistor and an initialization voltage line; and A first capacitor is connected between the gate electrode of the first transistor and the gate electrode of the fourth transistor.

2. The display device according to claim 1, wherein The display device further includes a second capacitor connected between the gate electrode of the first transistor and the source electrode of the first transistor.

3. The display device according to claim 2, wherein: The display device further includes a third capacitor connected between the gate electrode of the first transistor and the drain electrode of the first transistor.

4. The display device according to claim 3, wherein: The capacitance of the first capacitor is greater than the capacitance of the third capacitor, and The capacitance of the third capacitor is greater than the capacitance of the second capacitor.

5. The display device according to claim 4, wherein: The capacitance of the third capacitor is 31.3% of the capacitance of the second capacitor, and The capacitance of the first capacitor is 18.8% of the capacitance of the second capacitor.

6. The display device according to claim 1, wherein The display device further includes: a first scan line connected to the gate electrode of the second transistor; an emission control line connected to the gate electrode of the third transistor; and A second scan line is connected to the gate electrode of the fourth transistor.

7. The display device according to claim 6, wherein: In the initialization / writing period, the emission control signal of the emission control line, the first scan signal of the first scan line, and the second scan signal of the second scan line each have an active level. During the compensation period, the first scanning signal and the second scanning signal each have an active level, In the bypass period, the emission control signal and the second scan signal each have an active level, and the first scan signal has an inactive level, and In an emission period, the emission control signal has an active level, and the first scan signal and the second scan signal each have an inactive level.

8. The display device according to claim 7, wherein: applying a previous data voltage to the data line in the initialization / writing period and the compensation period, In the emission period, a current data voltage is applied to the data line, and In the bypass period, a transient data voltage transitioning from the previous data voltage to the current data voltage is applied to the data line.

9. The display device according to claim 1, wherein At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a body electrode connected to the driving voltage line.

10. The display device according to claim 1, wherein An initialization voltage of the initialization voltage line is lower than a driving voltage of the driving voltage line.

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