Display device

Abstract

A display device includes: a first pixel electrode on a substrate; a pixel defining layer on the substrate and exposing the first pixel electrode; a first light emitting layer on the first pixel electrode; a first common electrode on the first light emitting layer; a first bank on the pixel defining layer; a second bank on the first bank and including a side surface protruding more than a side surface of the first bank; and a third bank on upper and lower surfaces of the second bank.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0137794 filed in the Korean Intellectual Property Office on October 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in one or more suitable forms. For example, the display device is applied to one or more suitable electronic devices, such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and / or an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light. Therefore, the light emitting display device can display an image without a backlight unit that provides light to the display panel.

[0005] Recently, display devices have been applied to eyeglass-like devices for providing virtual reality and augmented reality. To be applied to eyeglass-like devices, the display device is implemented in a relatively small size of 2 inches or less. However, in order to have a relatively high resolution, the display device should have a relatively high pixel density. For example, the display device can have a high pixel density of 400 pixels per inch (PPI) or more.

[0006] When a display device is implemented in a relatively small size but has a relatively high pixel density as described above, it is difficult to implement a separate light emitting element in each emission area through a mask process because the area of the emission area in which the light emitting element is arranged and provided is reduced. Utility Model Content

[0007] One or more aspects of embodiments of the present disclosure are directed to a display device in which a separate light emitting element can be formed in each emission region without a mask process.

[0008] One or more aspects of the embodiments of the present disclosure relate to a display device in which a difference in light emission between pixels (eg, a difference in brightness between light emitting elements) is reduced.

[0009] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure provided herein.

[0010] According to one or more embodiments of the present disclosure, a display device includes: a first pixel electrode, which is (for example, arranged on) a substrate; a pixel defining layer, which is (for example, arranged on) the substrate and exposes the first pixel electrode; a first light-emitting layer, which is (for example, arranged on) the first pixel electrode; a first common electrode, which is (for example, arranged on) the first light-emitting layer; a first embankment, which is (for example, arranged on) the pixel defining layer; a second embankment, which is (for example, arranged on) the first embankment and includes a side surface that protrudes more than the side surface of the first embankment; and a third embankment, which is (for example, arranged on) the upper and lower surfaces of the second embankment.

[0011] The third bank may have a thickness of about 5 nanometers (nm) to about 100 nm.

[0012] A thickness of the third bank on (eg, disposed on) the upper surface of the second bank and a thickness of the third bank on (eg, disposed on) the lower surface of the second bank may be different from each other.

[0013] In one or more embodiments, the display device may further include (eg, disposed on) a first inorganic layer on the third bank and the first common electrode.

[0014] The third bank may completely cover the second bank.

[0015] The third bank may contact at least a portion of the lower surface of the second bank.

[0016] The third bank may include a hydrophobic material.

[0017] The third bank may be a self-assembled monolayer.

[0018] The third bank may include fluorine (F).

[0019] The third bank may include an —O-bond or an —S-bond (eg, an —O-metal bond or an —S-metal bond) on a surface of the second bank.

[0020] The second embankment may include a second lower embankment on (e.g., disposed on) the first embankment and a second upper embankment on (e.g., disposed on) the second lower embankment, the second upper embankment may include gold (Au), and the third embankment may include -S- bonds on a surface of the second upper embankment.

[0021] In one or more embodiments, the display device may further include a first covering layer between the first common electrode and the first inorganic layer.

[0022] One end and the other end of the first common electrode may contact the first bank.

[0023] In one or more embodiments, the display device may further include: a second pixel electrode, on (for example, arranged on) the substrate and spaced apart and / or separated from the first pixel electrode; a second light-emitting layer, on (for example, arranged on) the second pixel electrode; a second common electrode, on (for example, arranged on) the second light-emitting layer and spaced apart and / or separated from the first common electrode; and a second inorganic layer, on (for example, arranged on) the second common electrode and the second embankment and spaced apart and / or separated from the first inorganic layer.

[0024] In one or more embodiments, the display device may further include: a first light-emitting pattern, between the third embankment and the first inorganic layer and including the same material as the first light-emitting layer; and a first electrode pattern, between the first light-emitting pattern and the first inorganic layer and including the same material as the first common electrode.

[0025] According to one or more embodiments of the present disclosure, a display device may include: a first pixel electrode, on (e.g., disposed on) a substrate; a pixel defining layer, on (e.g., disposed on) the substrate and exposing the first pixel electrode; a first light-emitting layer, on (e.g., disposed on) the first pixel electrode; a first common electrode, on (e.g., disposed on) the first light-emitting layer; a first embankment, on (e.g., disposed on) the pixel defining layer; a second embankment, on (e.g., disposed on) the first embankment and including a side surface that protrudes more than a side surface of the first embankment; and a third embankment, on (e.g., disposed on) the second embankment and including fluorine (F).

[0026] The third bank may be on (eg, disposed on) an upper surface and a side surface of the second bank.

[0027] The third bank may include a hydrophobic material.

[0028] In one or more embodiments, the third bank may include an —O-bond or an —S-bond (eg, an —O-metal bond or an —S-metal bond) on a surface of the second bank.

[0029] In one or more embodiments, the third bank may form an -OP- bond or an -O-Si- bond with a surface of the second bank.

[0030] The display device according to one or more embodiments may include a third bank (e.g., disposed on) the second bank to prevent or reduce the penetration of the etchant into the light-emitting element during the etching process. Damage to the light-emitting element by the etching solution and / or moisture is prevented or reduced, and thus, brightness differences between the light-emitting elements can be reduced.

[0031] However, the effects and advantages of the present disclosure are not limited to the aforementioned effects and advantages, and include one or more appropriate other effects and advantages in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this disclosure. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. These and / or other aspects will become clearer and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0034] Figure 2 is viewed from one side of the display device according to one or more embodiments Figure 1 A cross-sectional view of a display device;

[0035] Figure 3 is a plan view showing an arrangement of a light emitting element, a lower inorganic encapsulation layer, and a third bank in a display area of a display device according to one or more embodiments of the present disclosure;

[0036] Figure 4 is a cross-sectional view of a portion of a display device according to one or more embodiments of the present disclosure;

[0037] Figure 5 According to one or more embodiments of the present disclosure Figure 4 An enlarged view of area A1;

[0038] Figure 6 is an enlarged view of a first emission region of a display device according to one or more embodiments of the present disclosure;

[0039] Figure 7 is an enlarged view of a first emission region of a display device according to one or more embodiments of the present disclosure;

[0040] Figure 8 is an enlarged view of a first emission region of a display device according to one or more embodiments of the present disclosure;

[0041] Figure 9is a cross-sectional view illustrating penetration of an etchant into a light emitting element in a display device not including a third bank according to one or more embodiments of the present disclosure;

[0042] Figure 10 is a cross-sectional view illustrating prevention of penetration of moisture in a display device including a third bank according to one or more embodiments of the present disclosure; and

[0043] Figure 11 According to one or more embodiments of the present disclosure Figure 5 Schematic cross-sectional view of the self-assembled monolayer in area A2. DETAILED DESCRIPTION

[0044] The advantages and features of the present disclosure and the methods for achieving them may be more readily understood by referring to the following detailed description and accompanying drawings of the embodiments. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art, and the present disclosure will be limited only by the appended claims.

[0045] It will be understood that when an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer or on an intervening element or layer. Conversely, “directly on” may mean that there are no additional intervening elements or layers between the element or layer and the other element or layer. Similarly, when an element or layer is referred to as being “below” another element or layer or to the “left” or “right” of another element or layer, the element or layer may be directly adjacent to the other element or layer or adjacent to an intervening element or layer. In this disclosure, like reference numerals refer to like elements throughout, and for the sake of brevity, a repeated description thereof may not be provided.

[0046] It will be understood that although the terms first, second, third, etc. may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element in question could be named the second element without departing from the teachings of the present disclosure.

[0047] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view of a display device 10 according to one or more embodiments of the present disclosure.

[0049] refer to Figure 1, the display device 10 according to one or more embodiments may be included in an electronic device to provide an image displayed by the electronic device. The electronic device may refer to any electronic device that provides a display screen. Non-limiting examples of electronic devices may include televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smart phones, tablet personal computers (PCs), electronic watches, smart glasses, smart watches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and video cameras, all of which provide one or more display screens.

[0050] The shape of the display device 10 can be modified in various ways. For example, in one or more embodiments, the display device 10 can have a shape similar to a rectangle having short sides in the first direction DR1 and long sides in the second direction DR2. Each corner where the short sides extending in the first direction DR1 intersect with the long sides extending in the second direction DR2 can be rounded to have a curvature. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, each corner can be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and can also be a shape similar to other polygons, a circle, or an ellipse.

[0051] In one or more embodiments, the display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (refer to FIG. Figure 2 ).

[0052] The display panel 100 may include a main area MA and a sub-area SBA.

[0053] The main area MA may include a display area DA and a non-display area NDA, the display area DA including pixels that display an image, and the non-display area NDA being arranged around the display area DA (e.g., surrounding the display area DA). The display area DA may be configured to emit light from a plurality of emission areas or a plurality of opening areas. For example, in one or more embodiments, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0054] For example, in one or more embodiments, each of the multiple self-luminous elements may include but is not limited to at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode.

[0055] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit of light emission, and the self-luminous elements may be pixels. The scan lines may supply scan signals received from a scan driver to the pixels. The data lines may supply data voltages received from the display driver 200 to the pixels. The power lines may supply power supply voltages received from the display driver 200 to the pixels.

[0056] The non-display area NDA may be an area outside the display area DA (e.g., surrounding or around the display area DA). The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a scan driver that supplies scan signals to scan lines and fan-out lines connecting the display driver 200 and the display area DA.

[0057] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, curled, etc. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction DR3 (third direction DR3). The sub-area SBA may include a display driver 200 and a pad unit connected to the circuit board 300. In some embodiments, the sub-area SBA may not be provided, and the display driver 200 and the pad unit may be provided in the non-display area NDA.

[0058] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines. The display driver 200 may supply power voltages to the power lines and supply scan control signals to the scan driver. The display driver 200 may be formed as an integrated circuit and may be mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, in some embodiments, the display driver 200 may be disposed and provided in the sub-area SBA and may overlap with the main area MA in the thickness direction DR3 (third direction DR3) by bending the sub-area SBA. In some embodiments, the display driver 200 may be mounted on the circuit board 300.

[0059] The circuit board 300 may be attached to the pad unit of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0060] Figure 2 is viewed from one side of the display device according to one or more embodiments Figure 1sectional view of the display device 10. For example, Figure 2 Shown in folded state Figure 1 One side of the display device 10.

[0061] refer to Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0062] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, in some embodiments, the substrate SUB may include a polymer resin such as polyimide (PI), but the embodiments of the present disclosure are not limited thereto. In one or more embodiments, the substrate SUB may include a glass material or a metal material.

[0063] The thin film transistor layer TFTL may be (e.g., disposed on) the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include scan lines, data lines, power lines, scan control lines, fan-out lines connecting the display driver 200 and the data lines, and leads connecting the display driver 200 and the pad unit. Each thin film transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in some embodiments, when the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0064] The thin film transistor layer TFTL may be (e.g., disposed in) the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, scan lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be (e.g., disposed in) the display area DA. The scan control lines and fan-out lines of the thin film transistor layer TFTL may be (e.g., disposed in) the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be (e.g., disposed in) the sub-area SBA.

[0065] The light-emitting element layer EML may be (e.g., disposed on) the thin film transistor layer TFTL. The light-emitting element layer EML may include a plurality of light-emitting elements, each of which includes a first electrode, a second electrode, a light-emitting layer for emitting light, and a pixel-defining layer defining a pixel. The light-emitting elements of the light-emitting element layer EML may be (e.g., disposed) in the display area DA.

[0066] In one or more embodiments, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively. The holes and electrons may then recombine with each other in the organic light-emitting layer to emit light.

[0067] In one or more embodiments, each light emitting element may include a quantum dot light emitting diode having a quantum dot light emitting layer, an inorganic light emitting diode having an inorganic semiconductor, or a micro light emitting diode.

[0068] The thin film encapsulation layer TFEL may cover the upper surface and side surfaces of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EML.

[0069] The color filter layer CFL may be (e.g., disposed on) the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the plurality of color filters may selectively transmit light of a specific wavelength and block, reduce, or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of light from outside the display device 10, thereby reducing reflected light caused by the external light. Therefore, the color filter layer CFL may prevent or reduce color distortion caused by reflection of external light.

[0070] Since the color filter layer CFL is directly on (eg, disposed on) the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0071] In some embodiments, the display device 10 may further include an optical device. The optical device may be configured to transmit or receive light in the infrared, ultraviolet, or visible light bands. For example, in one or more embodiments, the optical device may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0072] Figure 3 is a plan view of a portion of the display device 10 according to one or more embodiments. Figure 3 is a plan view illustrating the arrangement of the light emitting elements ED1 to ED3 , the lower inorganic encapsulation layers TL1 to TL3 , and the third bank BN3 in the display area DA of the display device 10 according to one or more embodiments of the present disclosure.

[0073] refer to Figure 3 , the third bank BN3 may cover the display area DA but partially expose the display area DA. Figure 3 The dotted area in the figure may be formed in an area exposed by the third bank BN3 and the light-emitting elements ED1 to ED3 may be provided in the openings. The lower inorganic encapsulation layers TL1 to TL3 may be provided on the third bank BN3 to cover the boundary portion of the openings and may cover the light-emitting elements ED1 to ED3 in the openings.

[0074] exist Figure 3 In the embodiment, the exposed areas not covered by the third bank BN3 are circular. However, these areas may also have polygonal shapes, such as triangles, quadrilaterals, or hexagons. In some embodiments, the shapes of the lower inorganic encapsulation layers TL1 to TL3 covering the exposed areas and the portions around the exposed areas may also be changed accordingly. A portion of the lower inorganic encapsulation layers TL1 to TL3 may be arranged and provided at a level higher than the third bank BN3, and the light-emitting elements ED1 to ED3 may be arranged and provided at a level lower than the third bank BN3.

[0075] In one or more embodiments, the light emitting elements ED1 to ED3 may be Type or kind (e.g., diamond type or kind) arrangement. is a registered trademark of Samsung Display Co., Ltd. For example, in one or more embodiments, the first light-emitting element ED1 and the third light-emitting element ED3 may be spaced apart and / or separated from each other in the first direction DR1, and may be alternately arranged in the first direction DR1 and the second direction DR2. Each second light-emitting element ED2 may be spaced apart and / or separated from other adjacent second light-emitting elements ED2 in the first direction DR1 and the second direction DR2. The second light-emitting element ED2 and the first light-emitting element ED1 or the second light-emitting element ED2 and the third light-emitting element ED3 may be alternately arranged along any one direction in a plane formed by the first direction DR1 and the second direction DR2 (for example, in a plan view). The shape and arrangement of the area not covered by the third embankment BN3 and the light-emitting elements ED1 to ED3 are not limited to Figure 3 The shape and arrangement of the .

[0076] Figure 4 is a cross-sectional view of a portion of the display device 10 according to one or more embodiments of the present disclosure. For example, Figure 4 yes Figure 3 Cross-sectional view of part II'. Figure 4 Cross sections of a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL are shown.

[0077] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0078] The first buffer layer BF1 may be (eg, disposed on) the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing or reducing the penetration of air and / or moisture. For example, in some embodiments, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0079] The bottom metal layer BML may be (e.g., disposed on) the first buffer layer BF1. For example, each of the plurality of bottom metal layers BML may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0080] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing or reducing the penetration of air and / or moisture. For example, in some embodiments, the second buffer layer BF2 may include a plurality of inorganic layers stacked alternately.

[0081] The thin film transistor TFT may be (e.g., disposed on) the second buffer layer BF2. The thin film transistor TFT may constitute a pixel circuit of each of the plurality of pixels. For example, each of the plurality of thin film transistors TFT may be a driving transistor or a switching transistor of the pixel circuit. Each of the plurality of thin film transistors TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0082] The semiconductor layer ACT may be (e.g., disposed) on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the thickness direction DR3 and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made conductive to form a source electrode SE and a drain electrode DE.

[0083] The gate electrode GE may be (eg, disposed on) the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction DR3 with the gate insulating layer GI interposed therebetween.

[0084] The gate insulating layer GI may be (e.g., disposed on) the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0085] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may communicate with the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0086] The capacitor electrode CPE may be (eg, disposed on) the first interlayer insulating layer ILD1 , overlap the gate electrode GE in the thickness direction DR3 , and form a capacitor with the capacitor electrode CPE and the gate electrode GE and the first interlayer insulating layer ILD1 therebetween.

[0087] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may communicate with the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0088] The first connection electrode CNE1 may be (e.g., disposed) on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be embedded in a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0089] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0090] The second connection electrode CNE2 may be (e.g., disposed) on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the corresponding pixel electrodes AE1 to AE3 of the light emitting element ED. The second connection electrode CNE2 may be embedded in a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0091] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1 to AE3 of the light emitting element ED pass.

[0092] The light-emitting element layer EML may be (e.g., disposed on) the thin film transistor layer TFTL. The light-emitting element layer EML may include light-emitting elements ED, a pixel defining layer PDL, a capping layer CAP (CAP1 to CAP3), and a bank structure BNS. The light-emitting element ED may include pixel electrodes AE1 to AE3, light-emitting layers EL1 to EL3, and common electrodes CE1 to CE3.

[0093] Figure 5 According to one or more embodiments of the present disclosure Figure 4 The first emission area EA1 (specifically, Figure 4 Magnified view of area A1).

[0094] Apart from Figure 4 In addition, reference Figure 5 , the display device 10 (reference Figure 3 ) may be included in (eg, disposed in) the display area DA (reference Figure 3 ) in a plurality of emission areas EA1 to EA3. The emission areas EA1 to EA3 may include areas where light is emitted from light emitting elements ED1 to ED3 including sequentially stacked pixel electrodes AE1 to AE3, light emitting layers EL1 to EL3, and common electrodes CE1 to CE3, and passes through a color filter layer CFL in a third direction DR3. The emission areas EA1 to EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced and / or separated from each other and emit light of the same color or different colors.

[0095] In one or more embodiments, the first to third emission areas EA1 to EA3 may have the same area or size. For example, in some embodiments, in the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have substantially the same area. However, the embodiments of the present disclosure are not limited thereto. In the display device 10, the first to third emission areas EA1 to EA3 may also have different areas or sizes. For example, in some embodiments, the area of the second emission area EA2 may be larger than the area of the first emission area EA1 and the area of the third emission area EA3, and the area of the third emission area EA3 may be larger than the area of the first emission area EA1. The intensity of light emitted from each of the emission areas EA1 to EA3 may vary according to the area of the emission area EA1, EA2, or EA3, and the color of the image displayed in the display device 10 may be controlled or selected by adjusting the area of each of the emission areas EA1 to EA3. Figure 4In the embodiment of FIG. 5 , the emission areas EA1 to EA3 have substantially the same area. However, the embodiments of the present disclosure are not limited thereto.

[0096] In the display device 10, one first emission area EA1, one second emission area EA2, and one third emission area EA3 adjacent to each other may form a pixel group. A pixel group may include emission areas EA1 to EA3 that emit light of different colors to present a white grayscale. However, the embodiments of the present disclosure are not limited thereto, and the combination of emission areas EA1 to EA3 constituting a pixel group may be modified differently and appropriately according to the arrangement of the emission areas EA1 to EA3 and the color of the light emitted from the emission areas EA1 to EA3.

[0097] A plurality of openings formed in the embankment structure BNS of the light emitting element layer EML may be defined along the boundary of the embankment structure BNS. The first embankment BN1, the second embankment BN2, and the third embankment BN3 of the embankment structure BNS may surround the emission areas EA1 to EA3. Each opening may include a corresponding one of the first to third emission areas EA1 to EA3.

[0098] In one or more embodiments, the display device 10 may include a plurality of light-emitting elements ED1 to ED3 disposed / provided in different emission areas EA1 to EA3. The light-emitting elements ED1 to ED3 may include a first light-emitting element ED1 disposed in (e.g., disposed in) a first emission area EA1, a second light-emitting element ED2 disposed in (e.g., disposed in) a second emission area EA2, and a third light-emitting element ED3 disposed in (e.g., disposed in) a third emission area EA3.

[0099] The light-emitting elements ED1 to ED3 may respectively include pixel electrodes AE1 to AE3, light-emitting layers EL1 to EL3 and common electrodes CE1 to CE3. The light-emitting elements ED1 to ED3 arranged / provided in different emission areas EA1 to EA3 may be used to emit light of different colors according to the materials of the light-emitting layers EL1 to EL3. For example, in one or more embodiments, the first light-emitting element ED1 in (for example, arranged in) the first emission area EA1 may be used to emit a red first light having a peak wavelength of 610 nanometers (nm) to 650 nm, the second light-emitting element ED2 in (for example, arranged in) the second emission area EA2 may be used to emit a green second light having a peak wavelength of 510 nm to 550 nm, and the third light-emitting element ED3 in (for example, arranged in) the third emission area EA3 may be used to emit a blue third light having a peak wavelength of 440 nm to 480 nm. The first emission area EA1 to the third emission area EA3 constituting a pixel group may include light-emitting elements ED1 to ED3 that emit light of different colors to present a white grayscale. In some embodiments, the light-emitting layers EL1 to EL3 may include two or more materials that emit light of different colors, so that one light-emitting layer may emit mixed light. For example, in some embodiments, the light-emitting layers EL1 to EL3 may include a red light-emitting material and a green light-emitting material to emit yellow light, or may include a red light-emitting material, a green light-emitting material, and a blue light-emitting material to emit white light (e.g., combined white light).

[0100] The pixel electrodes AE1 to AE3 may be (e.g., disposed) on the second passivation layer PAS2. The pixel electrodes AE1 to AE3 may be (e.g., disposed) in the emission areas EA1 to EA3, respectively. The pixel electrodes AE1 to AE3 may include a first pixel electrode AE1 disposed in (e.g., disposed) the first emission area EA1, a second pixel electrode AE2 disposed in (e.g., disposed) the second emission area EA2, and a third pixel electrode AE3 disposed in (e.g., disposed) the third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart and / or separated from each other on the second passivation layer PAS2.

[0101] The pixel electrodes AE1 to AE3 may be electrically connected to the corresponding drain electrodes DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2. The first to third pixel electrodes AE1 to AE3 may be insulated from one another by a pixel defining layer PDL covering edges of the pixel electrodes AE1 to AE3 that are spaced apart and / or separated from one another.

[0102] Pixel electrodes AE1 to AE3 may include a transparent electrode material and / or a conductive metal material. The metal material may be at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), and titanium (Ti). The transparent electrode material may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In some embodiments, pixel electrodes AE1 to AE3 may have a multilayer structure of a transparent electrode material and a conductive metal material.

[0103] The pixel defining layer PDL may be on (e.g., disposed on) the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1 to AE3. The pixel defining layer PDL may be disposed on the entire surface of the second passivation layer PAS2, but may (e.g., may only) cover the side surfaces of the pixel electrodes AE1 to AE3 and the residual pattern RP to partially expose the upper surfaces of the pixel electrodes AE1 to AE3. For example, the pixel defining layer PDL may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly on (e.g., disposed on) the first pixel electrode AE1.

[0104] The pixel defining layer (PDL) may include an inorganic insulating material and may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer.

[0105] According to one or more embodiments, the pixel defining layer PDL may be on (e.g., disposed on) the pixel electrodes AE1 to AE3, but may be spaced apart and / or separated from the upper surfaces of the pixel electrodes AE1 to AE3. The pixel defining layer PDL may partially overlap with the upper surfaces of the pixel electrodes AE1 to AE3 in the thickness direction DR3 of the substrate SUB, but may not directly contact the upper surfaces of the pixel electrodes AE1 to AE3, and a residual pattern RP may be provided between the pixel defining layer PDL and the pixel electrodes AE1 to AE3. However, the pixel defining layer PDL may directly contact the side surfaces of the pixel electrodes AE1 to AE3. The side surface of the pixel defining layer PDL may protrude more toward the emission areas EA1 to EA3 than the side surface of the second embankment BN2.

[0106] The residual pattern RP may be (e.g., disposed) on an edge of each of the pixel electrodes AE1 to AE3. Due to the residual pattern RP, the pixel defining layer PDL may not directly contact the upper surface of the pixel electrodes AE1 to AE3. The residual pattern RP may be formed when a sacrificial layer disposed on the pixel electrodes AE1 to AE3 is partially removed during a process of manufacturing the display device 10. The residual pattern RP may include a metal or oxide semiconductor material. In the drawings (e.g., Figures 4 to 10), the side surface of the residual pattern RP facing the emission areas EA1 to EA3 is more recessed than the side surface of the pixel defining layer PDL. However, the embodiments of the present disclosure are not limited thereto. The side surface of the residual pattern RP may also be aligned with the side surface of the pixel defining layer PDL, or may protrude more toward the emission areas EA1 to EA3 than the side surface of the pixel defining layer PDL. The side surface of the pixel defining layer PDL may be the outermost surface facing the emission areas EA1 to EA3.

[0107] The light-emitting layers EL1 to EL3 may be (e.g., disposed on) the pixel electrodes AE1 to AE3. In one or more embodiments, the light-emitting layers EL1 to EL3 may be organic light-emitting layers made of an organic material and may be formed on the pixel electrodes AE1 to AE3 by a deposition process. Each of the light-emitting layers EL1 to EL3 may have a multilayer structure, and hole injection materials, hole transport materials, light-emitting materials, electron transport materials, and / or electron injection materials may form corresponding layers. When the thin film transistor TFT applies a set or predetermined voltage to the corresponding pixel electrodes AE1 to AE3 of the light-emitting elements ED1 to ED3 and the common electrodes CE1 to CE3 of the light-emitting elements ED1 to ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, and may then recombine with each other in the light-emitting layers EL1 to EL3 to emit light.

[0108] The light-emitting layers EL1 to EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged and provided in different emission areas EA1 to EA3. The first light-emitting layer EL1 may be on (for example, arranged on) the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be on (for example, arranged on) the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be on (for example, arranged on) the third pixel electrode AE3 in the third emission area EA3. The light-emitting layers EL1 to EL3 may be used to emit light of different colors, or one light-emitting layer EL1, EL2, or EL3 may be used to emit mixed light. In some embodiments, the first light-emitting layer EL1 may be used to emit red light, the second light-emitting layer EL2 may be used to emit green light, and the third light-emitting layer EL3 may be used to emit blue light. In some embodiments, the first light-emitting layer EL1 may be used to emit yellow light as a mixture of red light and green light, and the second light-emitting layer EL2 may be used to emit blue light. In some embodiments, the first light-emitting layer EL1 may be used to emit white light as a mixture of red light, green light, and blue light.

[0109] The light-emitting layers EL1 to EL3 may be disposed on (e.g., disposed on) an upper surface of the pixel-defining layer PDL. In some embodiments, the light-emitting layers EL1 to EL3 may be disposed in a space between the pixel electrodes AE1 to AE3 and the pixel-defining layer PDL. In some embodiments, the light-emitting layers EL1 to EL3 may contact the pixel-defining layer PDL, the residual pattern RP, and the corresponding pixel electrodes AE1 to AE3.

[0110] The common electrodes CE1 to CE3 may be disposed on (e.g., arranged on) the corresponding light-emitting layers EL1 to EL3. The common electrodes CE1 to CE3 may include a transparent conductive material to allow light generated by the light-emitting layers EL1 to EL3 to pass therethrough. The common electrodes CE1 to CE3 may receive a common voltage or a low-potential voltage. When the pixel electrodes AE1 to AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1 to CE3 receive a low-potential voltage, a potential difference may be formed between the pixel electrodes AE1 to AE3 and the common electrodes CE1 to CE3. Thus, the light-emitting layers EL1 to EL3 may be configured to emit light.

[0111] The common electrodes CE1 to CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, respectively disposed in different emission areas EA1 to EA3. The first common electrode CE1 may be on (e.g., disposed in) the first light-emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be on (e.g., disposed in) the second light-emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be on (e.g., disposed in) the third light-emitting layer EL3 in the third emission area EA3. The first to third common electrodes CE1 to CE3 may be spaced apart and / or separated from each other.

[0112] The cover layers CAP1 to CAP3 may be disposed on the common electrodes CE1 to CE3, respectively. The cover layers CAP1 to CAP3 may include an organic or inorganic insulating material to cover the light emitting elements ED1 to ED3. The cover layers CAP1 to CAP3 may prevent or reduce damage to the light emitting elements ED1 to ED3 by external air. In one or more embodiments, the capping layers CAP1 to CAP3 may include an organic material such as N,N′-bis(naphthalene-1-yl)-N,N′-bis(phenyl)-2,2′-dimethylbenzidine (α-NPD), N,N′-bis(naphthalene-1-yl)-N,N′-bis(phenyl)-benzidine (NPB), N,N′-bis(3-methylphenyl)-N,N′-bis(phenyl)-benzidine (TPD), 4,4′,4″-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine (m-MTDATA), tris(8-hydroxyquinoline)aluminum (Alq3) and / or copper(II) phthalocyanine (CuPc), or may include an inorganic material such as lithium fluoride (LiF), aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0113] The capping layers CAP1 to CAP3 may include a first capping layer CAP1, a second capping layer CAP2, and a third capping layer CAP3 respectively disposed and provided in different emission areas EA1 to EA3. The first to third capping layers CAP1 to CAP3 may be spaced apart and / or separated from each other.

[0114] The display device 10 may include (e.g., disposed on) a dam structure BNS on the pixel defining layer PDL. The dam structure BNS may have a structure in which first to third dams BN1 to BN3, each made of different materials, are sequentially stacked. The dam structure BNS may include a plurality of openings having emission areas EA1 to EA3 and may overlap with a light blocking layer BM, which will be described later. The light-emitting elements ED1 to ED3 of the display device 10 may overlap with the openings of the dam structure BNS.

[0115] The bank structure BNS may include a first bank BN1 , a second bank BN2 , and a third bank BN3 sequentially stacked on the pixel defining layer PDL.

[0116] The first bank BN1 may be (e.g., disposed on) the pixel defining layer PDL. The side surface of the first bank BN1 may be more recessed than the side surface of the pixel defining layer PDL in a direction opposite to the direction toward the emission areas EA1 to EA3 (direction directly away from the emission areas EA1 to EA3). The side surface of the first bank BN1 may be more recessed than the side surface of the second bank BN2, which will be described later, in a direction opposite to the direction toward the emission areas EA1 to EA3.

[0117] According to one or more embodiments, the first bank BN1 may include a metal material. In one or more embodiments, the first bank BN1 may include aluminum (Al) or an aluminum (Al) alloy.

[0118] In one or more embodiments, the thickness of the first bank BN1 may be 4000 angstroms. to When the above range is satisfied, the light emitting layers EL1 to EL3 and the common electrodes CE1 to CE3 separated from each other may be formed by a deposition and etching process instead of a mask process.

[0119] According to one or more embodiments, the common electrodes CE1 to CE3 may directly contact the side surface of the first bank BN1. One end and the other end of each of the common electrodes CE1 to CE3 may contact the side surface of the first bank BN1. The common electrodes CE1 to CE3 of different light-emitting elements ED1 to ED3 may directly contact the first bank BN1, and the first bank BN1 may include a metal material. Therefore, the common electrodes CE1 to CE3 may be electrically connected to each other through the first bank BN1.

[0120] The light-emitting layers EL1 to EL3 may directly contact the side surfaces of the first bank BN1. The contact area between the common electrodes CE1 to CE3 and the side surfaces of the first bank BN1 may be greater than the contact area between the light-emitting layers EL1 to EL3 and the side surfaces of the first bank BN1. The common electrodes CE1 to CE3 may be disposed over a larger area of the side surfaces of the first bank BN1, or may be positioned higher on the side surfaces of the first bank BN1 than the light-emitting layers EL1 to EL3. Because the common electrodes CE1 to CE3 of different light-emitting elements ED1 to ED3 are electrically connected via the first bank BN1, it is advantageous for the common electrodes CE1 to CE3 to contact a larger area of the first bank BN1.

[0121] The second bank BN2 may be disposed on the first bank BN1. The second bank BN2 may include a tip TIP protruding from the first bank BN1. The side surface of the second bank BN2 may protrude further toward the emission areas EA1 to EA3 than the side surface of the first bank BN1.

[0122] Because the side surface of the second bank BN2 protrudes more toward the emission areas EA1 to EA3 than the side surface of the first bank BN1 , an undercut structure of the first bank BN1 may be formed under each tip end TIP of the second bank BN2 .

[0123] In the display device 10 according to one or more embodiments, because the embankment structure BNS includes a tip TIP protruding toward the emission areas EA1 to EA3, the light-emitting layers EL1 to EL3 and the common electrodes CE1 to CE3 that are spaced apart and / or separated from each other can be formed by a deposition and etching process rather than a mask process. In some embodiments, different layers can be formed separately in different emission areas EA1 to EA3 even by a deposition process. For example, even when the light-emitting layers EL1 to EL3 and the common electrodes CE1 to CE3 of the light-emitting elements ED1 to ED3 are formed by a deposition process that does not utilize a mask, the deposited material may not be connected between the emission areas EA1 to EA3, but may be separated by the tip TIP of the second embankment BN2 with the embankment structure BNS interposed therebetween. After the material for forming a specific layer is formed on the entire surface of the display device 10, the layer formed in the undesired area can be removed by etching. Through this process, different layers can be formed separately in different emission areas EA1 to EA3. In the display device 10, different light emitting elements ED1 to ED3 can be formed in the emission areas EA1 to EA3 through deposition and etching processes without using a mask process, unnecessary components can be omitted from the display device 10, and the non-display area NDA (refer to FIG. Figure 1 ) area.

[0124] The side profile of the bank structure BNS may be a structure (e.g., shape) formed during the etching process due to a difference in etching rates between the first bank BN1 and the second bank BN2, which may be made of different materials. According to one or more embodiments, the second bank BN2 may include a material having a slower etching rate than the first bank BN1, and the first bank BN1 may be further etched during the etching process to expose the lower surface of the tip TIP of the second bank BN2 and form an undercut under each tip TIP of the second bank BN2.

[0125] The second bank BN2 may include a metal material different from the metal material of the first bank BN1. The metal material of the second bank BN2 may be a material that is removed together with the metal material of the first bank BN1 by dry etching, but is not etched by wet etching or is etched at a much slower etching rate than the etching rate of the first bank BN1. In one or more embodiments, the first bank BN1 may include aluminum (Al) or an aluminum (Al) alloy, and the second bank BN2 may include titanium (Ti) or a titanium (Ti) alloy.

[0126] The tip TIP of the second bank BN2 may overlap with the common electrodes CE1 to CE3, the light-emitting layers EL1 to EL3, and / or the pixel-defining layer PDL in a thickness direction DR3 perpendicular to the substrate SUB. One end and the other end of each of the common electrodes CE1 to CE3 may overlap with the second bank BN2 in the thickness direction DR3 of the substrate SUB. The maximum vertical distance from the substrate SUB to each of the common electrodes CE1 to CE3 may be less than the maximum vertical distance from the substrate SUB to the second bank BN2.

[0127] The third bank BN3 may be (e.g., disposed on) the second bank BN2. The third bank BN3 may completely cover the upper surface of the second bank BN2 and may cover the side surfaces of the second bank BN2. In some embodiments, the third bank BN3 may also be (e.g., disposed on) the lower surface of the second bank BN2.

[0128] Figure 6 is the first emission area EA1 (specifically, corresponding to the first emission area EA2 of the display device according to one or more embodiments of the present disclosure) Figure 4 An enlarged view of area A1 (area A1_1). Figure 7 is the first emission area EA1 (specifically, corresponding to the first emission area EA2 of the display device according to one or more embodiments of the present disclosure) Figure 4 An enlarged view of area A1 (area A1_2).

[0129] Figure 6 and Figure 7 and Figure 5 The difference is that the third bank BN3_1 or BN3_2 is also (e.g., disposed on) the lower surface of the second bank BN2. The third bank BN3_1 or BN3_2 may also be formed on the lower surface of the tip TIP of the second bank BN2. The third bank BN3_1 or BN3_2 may contact at least a portion of the lower surface of the second bank BN2.

[0130] In one or more embodiments, Figure 6 As shown in , the third bank BN3_1 may be provided on a portion of the lower surface of the second bank BN2, and may not be provided on the other portion. On the lower surface of each tip TIP of the second bank BN2, the third bank BN3_1 may be provided in a region adjacent to the emission area EA1, EA2, or EA3, and may not be provided in a region adjacent to the side surface of the first bank BN1. In one or more embodiments, as Figure 7 As shown in FIG, the third bank BN3_2 may completely cover the lower surface of the tip TIP of the second bank BN2.

[0131] After forming the undercut structure of the first bank BN1, the third bank BN3 may be formed by a wet coating process or a vacuum thermal evaporation process performed on the second bank BN2. The formation position and area of the third bank BN3 may be adjusted in the coating process or the evaporation process.

[0132] Figure 8 is the first emission area EA1 (specifically, corresponding to the first emission area EA2 of the display device according to one or more embodiments of the present disclosure) Figure 4 An enlarged view of area A1 (area A1_3). Figure 8 and Figure 5 The difference is that the second bank BN2_1 has a multi-layer structure. The second bank BN2_1 may include a second lower bank BN2a (e.g., disposed on) the first bank BN1 and a second upper bank BN2b (e.g., disposed on) the second lower bank BN2a. The second upper bank BN2b may include a different material from the second lower bank BN2a and may include a material having excellent or suitable adhesion to the third bank BN3, thereby improving the durability of the display panel. In one or more embodiments, the second lower bank BN2a may include titanium (Ti), and the second upper bank BN2b may include gold (Au).

[0133] In one or more embodiments, the thickness of the third bank BN3 may be about 5 nm to about 100 nm. Within this range, the third bank BN3 may be smoothly formed and may have an excellent or suitable moisture permeability effect. The third bank BN3 may be disposed on the upper surface, side surface and / or lower surface of the second bank BN2. Here, the thickness of the third bank BN3 may remain constant or may vary according to the position. In some embodiments, the thickness of the third bank BN3 on (e.g., disposed on) the upper surface of the second bank BN2 and the thickness of the third bank BN3 on (e.g., disposed on) the lower surface of the second bank BN2 may be different from each other. In the coating or deposition process for forming the third bank BN3, the thickness of the third bank BN3 may be adjusted according to the position.

[0134] In some embodiments, after sequentially stacking the first light-emitting layer EL1 / first light-emitting pattern ELP1, the first common electrode CE1 / first electrode pattern CEP1, the first capping layer CAP1 / first capping pattern CPP1, and the first inorganic layer TL1, a mask can be formed to cover the first emission area EA1 and the portion surrounding the first emission area EA1. The first inorganic layer TL1, the first capping layer CAP1, the first common electrode CE1, and the first light-emitting layer EL1 can then be sequentially removed in the area not covered by the mask. Removal of the first light-emitting pattern ELP1 can be performed by wet etching.

[0135] Figure 9is a cross-sectional view illustrating penetration of an etchant into a light emitting element in a display device not including a third bank according to one or more embodiments of the present disclosure. Figure 10 1 is a cross-sectional view illustrating how moisture is prevented from penetrating in a display device including a third bank according to one or more embodiments of the present disclosure. Figure 9 When the third bank BN3 is not provided on the second bank BN2 as shown in FIG, when removing the first light-emitting pattern ELP1, the etchant may penetrate between the second bank BN2 and the first light-emitting pattern ELP1 to reach the light-emitting element ED1 below the tip TIP of the second bank BN2. The penetration of the etchant may cause degradation and damage to the first light-emitting element ED1 and may cause dark spots in the display panel.

[0136] In contrast, when Figure 10 When the third bank BN3 is provided on the second bank BN2, the third bank BN3 can prevent or reduce the penetration of the etchant at the interface with the first light emitting pattern ELP1. Since the etchant does not reach the first light emitting element ED1, damage to the light emitting element ED1 can be prevented or reduced, and the brightness difference between the light emitting elements ED1 to ED3 can be reduced.

[0137] The third bank BN3 may be hydrophobic by including a hydrophobic material (eg, by including or having a hydrophobic portion). The hydrophobic material included in the third bank BN3 may prevent or reduce etchant from penetrating the interface between the first light emitting pattern ELP1 and the third bank BN3.

[0138] The third bank BN3 may be a self-assembled monolayer. In one or more embodiments, the third bank BN3 may be a perfluorinated self-assembled monolayer and may include fluorine (F).

[0139] Figure 11 According to one or more embodiments of the present disclosure Figure 5 Schematic cross-sectional view of the self-assembled monolayer in area A2. Figure 11 Schematically illustrates one or more embodiments of the present disclosure. Figure 5 The cross section of region A2, i.e., the interface between the second bank BN2 and the third bank BN3. The self-assembled monolayer of the third bank BN3 is an organic assembly formed by adsorbing molecular components from a solution or a gas phase. The self-assembled monolayer may include self-assembled monomolecules, each of which includes a head group HG attached to the surface of the second bank BN2, an end group TG at the end, and a chain CHN connecting the head group HG and the end group TG. A plurality of self-assembled monomolecules each including a head group HG, a chain CHN, and an end group TG may be aligned to form a layer. Figure 11 The self-assembled single molecules can not only be used in Figure 5 display device, and can be applied to Figures 6 to 8display device.

[0140] The head group HG of the third bank BN3 can be a portion attached to the second bank BN2 below the third bank BN3 and can include an -O- bond or an -S- bond (e.g., an -O- metal bond or an -S- metal bond). In other words, the third bank BN3 can be connected to the second bank BN2 via an -O- bond or an -S- bond (e.g., an -O- metal bond or an -S- metal bond). In one or more embodiments, the head group HG of the third bank BN3 can form an -OP- bond or an -O-Si- bond with the surface of the second bank BN2. For example, the head group HG can include one of the following structures. In these structures, the wavy line is the position connected to the second bank BN2, the dotted line is the position connected to the chain CHN, Ar is an aromatic hydrocarbon ring or an aromatic heterocycle, and can be substituted by a substituent.

[0141]

[0142] The chain CHN of the third bank BN3 may include a carbon-carbon skeleton and may include a carbonyl group or an amine bond. The number of carbon atoms in the chain CHN may be 2 to 20. One or more hydrogen atoms included in the chain CHN may be substituted with fluorine (F).

[0143] The terminal group TG of the third bank BN3 may determine the surface properties of the third bank BN3. When the terminal group TG is a hydrophobic group such as fluorine (F), the surface of the third bank BN3 may be hydrophobic.

[0144] In one or more embodiments, a single molecule including a head group HG, a chain CHN, and an end group TG may have a molecular weight of 500 to 2000. In one or more embodiments, a single molecule may include a skeleton of an aromatic hydrocarbon ring or an aromatic heterocyclic ring.

[0145] In one or more embodiments, the single molecule may include at least one of an alkanethiols (e.g., alkylthiols), alkylsiloxanes, and alkanesphosphonic acids (e.g., alkylphosphonic acids). In one or more embodiments, the single molecule may include (e.g., be) one of the following structures. In these structures, hydrogen may be replaced by fluorine (F).

[0146]

[0147] In one or more embodiments, reference Figure 8 The second bank BN2_1 may have a multilayer structure including a second upper bank BN2b made of gold (Au), and the third bank BN3 may be connected to the second bank BN2 through an -S- bond. Gold (Au) may undergo a self-assembly reaction with alkylthiol, and the third bank BN3 may include an -S- bond on the surface of the second upper bank BN2b.

[0148] refer to Figure 4 , the display device 10 (reference Figure 1 ) may include trace patterns TRP1 to TRP3 on the bank structure BNS, the trace patterns TRP1 to TRP3 being traces of the deposition process. The trace patterns TRP1 to TRP3 may include light emitting patterns ELP1 to ELP3, electrode patterns CEP1 to CEP3, and capping patterns CPP1 to CPP3, and may be provided on the third bank BN3 to surround the emission areas EA1 to EA3.

[0149] The trace patterns TRP1 to TRP3 may be traces formed when the deposited material is separated by the tip TIP of the embankment structure BNS without being connected to the light-emitting layers EL1 to EL3, the common electrodes CE1 to CE3, and the cover layers CAP1 to CAP3 in the emission areas EA1 to EA3. When the light-emitting material is completely deposited, the light-emitting layers EL1 to EL3 are formed within the openings, and the light-emitting patterns ELP1 to ELP3 are formed on the embankment structure BNS. The light-emitting patterns ELP1 to ELP3 may be separated from the light-emitting layers EL1 to EL3 by the tip TIP of the embankment structure BNS. The common electrodes CE1 to CE3 / electrode patterns CEP1 to CEP3 and the cover layers CAP1 to CAP3 / cover patterns CPP1 to CPP3 may also be separated by the tip TIP, and their traces may remain on the embankment structure BNS. In other words, the trace patterns TRP1 to TRP3 may be the result of patterning performed around the emission areas EA1 to EA3 or the openings.

[0150] The display device 10 according to one or more embodiments may include a plurality of light emitting patterns ELP1 to ELP3 including the same material as the light emitting layers EL1 to EL3 and disposed on the bank structure BNS. Since the light emitting layers EL1 to EL3 are formed by depositing a material over the entire surface of the display device 10, the material forming the light emitting layers EL1 to EL3 may be deposited on the bank structure BNS except for the emission areas EA1 to EA3.

[0151] For example, in one or more embodiments, the display device 10 may include (e.g., disposed on) the embankment structure BNS, light-emitting patterns ELP1 to ELP3. The light-emitting patterns ELP1 to ELP3 may include (e.g., disposed on) the third embankment BN3 of the embankment structure BNS, a first light-emitting pattern ELP1, a second light-emitting pattern ELP2, and a third light-emitting pattern ELP3.

[0152] The first light-emitting pattern ELP1 may include the same material as the first light-emitting layer EL1 of the first light-emitting element ED1. The second light-emitting pattern ELP2 may include the same material as the second light-emitting layer EL2 of the second light-emitting element ED2, and the third light-emitting pattern ELP3 may include the same material as the third light-emitting layer EL3 of the third light-emitting element ED3. Each of the light-emitting patterns ELP1 to ELP3 may be formed in a process that forms the corresponding light-emitting layer EL1, EL2, or EL3 including the same material as the corresponding light-emitting pattern ELP1, ELP2, or ELP3. The light-emitting patterns ELP1 to ELP3 may be disposed adjacent to the emission areas EA1 to EA3, respectively, in which the light-emitting layers EL1 to EL3 are disposed.

[0153] The display device 10 according to one or more embodiments may include a plurality of electrode patterns CEP1 to CEP3 that include the same material as the common electrodes CE1 to CE3 and are disposed on (e.g., disposed on) the bank structure BNS. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be disposed directly on the first light-emitting pattern ELP1, the second light-emitting pattern ELP2, and the third light-emitting pattern ELP3, respectively. The arrangement relationship between the electrode patterns CEP1 to CEP3 and the light-emitting patterns ELP1 to ELP3 may be the same as the arrangement relationship between the light-emitting layers EL1 to EL3 of the light-emitting elements ED1 to ED3 and the common electrodes CE1 to CE3.

[0154] In one or more embodiments, the display device 10 may include (e.g., disposed on) cover patterns CPP1 to CPP3 on the embankment structure BNS. The first cover pattern CPP1, the second cover pattern CPP2, and the third cover pattern CPP3 may be disposed directly on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, respectively. The arrangement relationship between the cover patterns CPP1 to CPP3 and the electrode patterns CEP1 to CEP3 may be the same as the arrangement relationship between the common electrodes CE1 to CE3 and the cover layers CAP1 to CAP3.

[0155] The thin film encapsulation layer TFEL may be disposed on (e.g., disposed on) the light-emitting elements ED1 to ED3 and the embankment structure BNS, and may cover the light-emitting elements ED1 to ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic layer to prevent or reduce the penetration of oxygen and / or moisture into the light-emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust.

[0156] In one or more embodiments, the thin film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1 , an organic encapsulation layer TFE2 , and an upper inorganic encapsulation layer TFE3 , which are sequentially stacked.

[0157] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include at least one inorganic insulating material. The inorganic insulating material may include or be selected from at least one (e.g., one or more) of silicon oxide, silicon nitride, and silicon oxynitride, and / or may be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide.

[0158] The organic encapsulation layer TFE2 may include a polymer material. Non-limiting examples of polymer materials may include acrylic resins, epoxy resins, polyimide, and polyethylene. For example, in some embodiments, the organic encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate and / or polyacrylic acid. The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0159] The lower inorganic encapsulation layer TFE1 may be (e.g., disposed on) the light-emitting elements ED1 to ED3, the trace patterns TRP1 to TPR3, and the embankment structure BNS. The lower inorganic encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 disposed to correspond to different emission areas EA1 to EA3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material to cover the light-emitting elements ED1 to ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent or reduce damage to the light-emitting elements ED1 to ED3 by external air.

[0160] Because the lower inorganic encapsulation layer TFE1 (TL1 to TL3) can be formed by chemical vapor deposition (CVD), the lower inorganic encapsulation layer TFE1 can be formed along the step of the layer on which the lower inorganic encapsulation layer TFE1 is deposited. For example, each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can also form a thin layer under the undercut formed by the tip TIP of the embankment structure BNS. The lower inorganic encapsulation layers TL1 to TL3 can be disposed on the light-emitting elements ED1 to ED3, the electrode patterns CEP1 to CEP3, and the embankment structure BNS. The first inorganic layer TL1 can be disposed along the side surfaces of the first light-emitting element ED1, the first cover layer CAP1, and the first embankment BN1 adjacent to the first common electrode CE1 to cover them. In some embodiments, the first inorganic layer TL1 can pass through the side surfaces of the second embankment BN2 and the third embankment BN3 to cover the first light-emitting pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CPP1.

[0161] The first inorganic layer TL1 may not overlap with the second opening and the third opening and may be provided only in the first opening and on the first light-emitting element ED1 and the embankment structure BNS surrounding the first light-emitting element ED1. The second inorganic layer TL2 may not overlap with the first opening and the third opening and may be provided only in the second opening and on the second light-emitting element ED2 and the embankment structure BNS surrounding the second light-emitting element ED2. The third inorganic layer TL3 may not overlap with the first opening and the second opening and may be provided only in the third opening and on the third light-emitting element ED3 and the embankment structure BNS surrounding the third light-emitting element ED3.

[0162] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. The first, second, and third inorganic layers TL1, TL2, and TL3 may be spaced apart and / or separated from one another on the bank structure BNS. Therefore, a portion of the third bank BN3 may not overlap with the first to third inorganic layers TL1 to TL3, and a portion of the upper surface of the third bank BN3 may be exposed in the space between the first to third inorganic layers TL1 to TL3 without being covered by the first to third inorganic layers TL1 to TL3. The exposed upper surface of the third bank BN3 may directly contact the organic encapsulation layer TFE2 of the thin-film encapsulation layer TFEL.

[0163] The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have substantially the same or similar boundaries as the first to third trace patterns TRP1 to TRP3, respectively, and may have a larger area than the openings or emission areas EA1 to EA3 of the embankment structure BNS. By adjusting the process of removing / etching the electrode patterns CEP1 to CEP3 and the light-emitting patterns ELP1 to ELP3 of the trace patterns TRP1 to TRP3, the trace patterns TRP1 to TRP3 may be made to have a boundary line located inside the lower inorganic encapsulation layers TL1 to TL3. For example, the trace patterns TRP1 to TRP3 may have a boundary line closer to the emission areas EA1 to EA3 than the lower inorganic encapsulation layers TL1 to TL3.

[0164] The organic encapsulating layer TFE2 may be on (eg, disposed on) the third bank BN3 and the lower inorganic encapsulating layers TL1 to TL3 . A portion of the organic encapsulating layer TFE2 may contact the third bank BN3 .

[0165] The upper inorganic encapsulation layer TFE3 may be (eg, disposed on) the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0166] The light blocking layer BM may be (e.g., disposed on) the thin film encapsulation layer TFEL. The light blocking layer BM may include a plurality of holes OPT1 to OPT3 that overlap with the emission areas EA1 to EA3, respectively. For example, the first hole OPT1 may overlap with the first emission area EA1. The second hole OPT2 may overlap with the second emission area EA2, and the third hole OPT3 may overlap with the third emission area EA3. The area or size of the holes OPT1 to OPT3 may be larger than the area or size of the emission areas EA1 to EA3, respectively. Because the holes OPT1 to OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1 to EA3, the user can see the light emitted from the emission areas EA1 to EA3 not only from the front of the display device 10 but also from the side of the display device 10.

[0167] The light blocking layer BM may include a light absorbing material. For example, in one or more embodiments, the light blocking layer BM may include an inorganic black pigment and / or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black. However, the embodiments of the present disclosure are not limited thereto. The light blocking layer BM may prevent or reduce color mixing by preventing or reducing the intrusion of visible light between the first emission area EA1 to the third emission area EA3, thereby improving the color gamut of the display device 10.

[0168] The display device 10 may include a plurality of color filters CF1 to CF3 in (e.g., arranged in) the emission areas EA1 to EA3. The color filters CF1 to CF3 may be arranged to correspond to the emission areas EA1 to EA3, respectively. For example, the color filters CF1 to CF3 may be arranged on a light blocking layer BM including holes OPT1 to OPT3 corresponding to the emission areas EA1 to EA3. The holes OPT1 to OPT3 of the light blocking layer BM may be formed to overlap with the emission areas EA1 to EA3 or the openings of the embankment structure BNS, and may form a light output area through which light emitted from the emission areas EA1 to EA3 is output. The color filters CF1 to CF3 may respectively have an area larger than the area of the holes OPT1 to OPT3 of the light blocking layer BM. The color filters CF1 to CF3 may respectively completely cover the light output area formed by the holes OPT1 to OPT3.

[0169] The color filters CF1 to CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different emission areas EA1 to EA3, respectively. Each of the color filters CF1 to CF3 may include a colorant such as a dye and / or pigment that absorbs light in a wavelength band other than light in a specific wavelength band, and may be arranged to correspond to the color of light emitted from a corresponding one of the emission areas EA1 to EA3. For example, in some embodiments, the first color filter CF1 may be a red filter that overlaps with the first emission area EA1 and transmits only red first light. The second color filter CF2 may be a green filter that overlaps with the second emission area EA2 and transmits only green second light, and the third color filter CF3 may be a blue filter that overlaps with the third emission area EA3 and transmits only blue third light.

[0170] Each of the color filters CF1 to CF3 may be spaced apart and / or separated from other adjacent color filters CF1 to CF3 on the light blocking layer BM. The color filters CF1 to CF3 may respectively cover the holes OPT1 to OPT3 of the light blocking layer BM and may have an area larger than the area of the holes OPT1 to OPT3. However, each of the color filters CF1 to CF3 may have an area large enough to be spaced apart and / or separated from the other color filters CF1 to CF3 on the light blocking layer BM. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, each of the color filters CF1 to CF3 may also partially overlap with the adjacent color filters CF1 to CF3. In these embodiments, the portions of different color filters CF1 to CF3 that do not overlap with the emission areas EA1 to EA3 may overlap with each other on the light blocking layer BM, which will be described later. Because the color filters CF1 to CF3 overlap with each other in the display device 10, the intensity of reflected light caused by external light can be reduced. Furthermore, the color of the reflected light caused by the external light may be controlled or selected by adjusting the arrangement, shape, and / or area of the color filters CF1 to CF3 in a plan view.

[0171] An overcoat layer OC may be provided on the color filters CF1 to CF3 to flatten the upper ends of the color filters CF1 to CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0172] The display device according to one or more embodiments includes a third bank (e.g., disposed on) the second bank. Therefore, it is possible to prevent or reduce the penetration of the etchant into the light-emitting element during the etching process. Because damage to the light-emitting element due to the etchant or moisture can be prevented or reduced, the brightness difference between the light-emitting elements can be reduced.

[0173] However, the effects and advantages of the present disclosure are not limited to those set forth herein. The above and other effects and advantages of the present disclosure will become more apparent to those skilled in the art by referring to the appended claims.

[0174] In the present disclosure, it will be understood that the terms “include,” “comprising,” or “having” specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0175] As used herein, the singular forms "a," "an," "one," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure."

[0176] As used herein, the terms "substantially," "approximately," or similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values that one of ordinary skill in the art will recognize. As used herein, "approximately" is inclusive of the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0177] Any numerical range recorded in this article is intended to include all sub-ranges of the same numerical precision included in the range of the record. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 recorded and the maximum value 10.0 recorded (and including the endpoint values), that is, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, for example, 2.4 to 7.6. Any maximum numerical limit recorded in this article is intended to include all smaller numerical limits included therein, and any minimum numerical limit recorded in this disclosure is intended to include all larger numerical limits included therein. Therefore, the applicant reserves the right to amend this disclosure (including claims) to explicitly describe any sub-range included in the range clearly recorded in this article.

[0178] According to the light-emitting elements, display devices, electronic devices, electronic equipment or any other related devices or components of the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software or a combination of software, firmware and hardware. For example, the various components of the device can be formed in an integrated circuit (IC) chip or in separate IC chips. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads that run on one or more processors, in one or more computing devices, execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using a standard storage device (e.g., random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., a compact disc read-only memory (CD-ROM) or a flash drive, etc.). In addition, it should be appreciated by those skilled in the art that, without departing from the scope of the embodiments of the present disclosure, the functions of the various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices.

[0179] While the present disclosure has been particularly shown and described with reference to the embodiments thereof, it will be understood by those skilled in the art that one or more suitable changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. A display device, characterized in that: The display device includes: a first pixel electrode on the substrate; a pixel defining layer on the substrate and exposing the first pixel electrode; a first light-emitting layer, on the first pixel electrode; a first common electrode, on the first light-emitting layer; a first bank on the pixel defining layer; a second bank on the first bank and including a side surface that protrudes more than a side surface of the first bank; and The third bank is on the upper surface and the lower surface of the second bank.

2. The display device according to claim 1, wherein The thickness of the third bank is 5 nanometers to 100 nanometers.

3. The display device according to claim 2, wherein: A thickness of the third bank on the upper surface of the second bank and a thickness of the third bank on the lower surface of the second bank are different from each other.

4. The display device according to claim 1, wherein The display device further includes a first inorganic layer on the third bank and the first common electrode.

5. The display device according to claim 1, wherein The third bank completely covers the second bank.

6. The display device according to claim 1, wherein The third bank contacts at least a portion of the lower surface of the second bank.

7. The display device according to claim 1, wherein The third bank is a self-assembled monolayer.

8. The display device according to claim 4, wherein: The display device further includes a first covering layer between the first common electrode and the first inorganic layer.

9. The display device according to claim 1, wherein One end and the other end of the first common electrode contact the first bank.

10. The display device according to claim 4, wherein The display device further includes: a second pixel electrode on the substrate and spaced apart from the first pixel electrode; a second light-emitting layer, on the second pixel electrode; a second common electrode on the second light emitting layer and spaced apart from the first common electrode; and A second inorganic layer is on the second common electrode and the second bank and is spaced apart from the first inorganic layer.

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