Display device

Abstract

The display device may include: a display area in which pixels are disposed, and a non-display area corresponding to an area separated from the display area; the pixel circuit layer comprises a pixel circuit; a first electrode disposed on the pixel circuit layer; an insulating layer having at least a portion exposing the first electrode; a second electrode disposed in the display area; and a connection electrode integrally formed with the second electrode, the connection electrode being disposed in the non-display area. The insulating layer includes: a first insulating layer disposed in the display area; and a second insulating layer disposed in the non-display area. The second insulating layer is in contact with at least a portion of the connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0006170 filed on January 15, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connecting medium between users and information has increased.

[0005] The display device may include a display area in which pixels for displaying an image are provided and a non-display area that is a region separate from the display area. In addition, the display device may include an electrode (e.g., a cathode electrode) for supplying power to the pixel, and the electrode of the display device may be deposited in a portion of the display area and the non-display area of the display device.

[0006] When electrodes of a display device are not properly deposited, the electrodes may be disconnected, and power may not be supplied to the pixels. Utility Model Content

[0007] The embodiment provides a display device capable of reducing the risk that an electrode (eg, a cathode electrode) will be disconnected.

[0008] According to one aspect of the present disclosure, a display device is provided including: a display area and a non-display area, pixels are arranged in the display area, and the non-display area corresponds to an area separated from the display area; a pixel circuit layer including a pixel circuit; a first electrode arranged on the pixel circuit layer; an insulating layer having at least a portion exposing the first electrode; a second electrode arranged in the display area; and a connecting electrode formed integrally with the second electrode, the connecting electrode being arranged in the non-display area, wherein the insulating layer includes: a first insulating layer arranged in the display area; and a second insulating layer arranged in the non-display area, and wherein the second insulating layer is in contact with at least a portion of the connecting electrode.

[0009] The display device may further include a metal layer disposed in the non-display area, the metal layer being disposed on the pixel circuit layer. In a plan view, at least a portion of the second insulating layer may overlap at least another portion of the metal layer. The second insulating layer may expose a top surface of the metal layer. An end portion of the second insulating layer may contact the connection electrode.

[0010] The connection electrode may be in contact with at least a portion of a top surface of the metal layer.

[0011] The metal layer may include at least one of Al, Ag, and Cu.

[0012] The metal layer may have to The thickness is within the range of .

[0013] The insulating layer may include a lower layer and an upper layer disposed on the lower layer. At least a portion of the insulating layer may extend from the display area to the non-display area.

[0014] The lower layer may include: a first lower layer; and a second lower layer disposed on the first lower layer. The upper layer may include: a first upper layer; a second upper layer disposed on the first upper layer; and a third upper layer disposed on the second upper layer.

[0015] Each of the first lower layer, the second lower layer, the first upper layer, the second upper layer, and the third upper layer may include silicon oxide (SiO x ) and silicon nitride (SiN x Each of the first lower layer, the second lower layer, the first upper layer, the second upper layer and the third upper layer may have to The thickness is within the range of .

[0016] At least a portion of the second insulating layer may be connected to at least a portion of the first insulating layer so that at least a portion of the insulating layer is disposed in the display region and the non-display region.

[0017] The pixel circuit layer may include: a first protective layer; and a second protective layer disposed on the first protective layer. The second protective layer may be disposed on the uppermost portion of the pixel circuit layer. At least a portion of the second insulating layer may be in contact with the second protective layer.

[0018] At least a portion of the second insulating layer may cover a side surface of the metal layer.

[0019] The pixel circuit layer may include: a contact hole penetrating at least a portion of the pixel circuit layer; a first conductive layer disposed in the display area; and a second conductive layer disposed in the non-display area. The metal layer may be electrically connected to the second conductive layer through the contact hole.

[0020] According to another aspect of the present disclosure, a display device is provided including: a display area in which pixels are set and a non-display area corresponding to an area separated from the display area; a pixel circuit layer including a pixel circuit; a first power line and a second power line electrically connected to the pixel circuit; a first electrode arranged on the pixel circuit layer; an insulating layer having at least a portion exposing the first electrode; a second electrode arranged in the display area; and a metal layer arranged on the pixel circuit layer in the non-display area, wherein the insulating layer includes: a first insulating layer arranged in the display area; and a second insulating layer arranged in the non-display area, wherein the second insulating layer contacts at least a portion of the metal layer, and wherein the non-display area includes a contact area, and the second power line and the connecting electrode are electrically connected to each other in the contact area.

[0021] The display device may further include a connecting electrode integrally formed with the second electrode, the connecting electrode being disposed in the non-display area. The connecting electrode may contact at least a portion of the top surface of the metal layer. The contact areas may include: a first contact area disposed on a first side of the display area; a second contact area disposed on a second side of the display area; a third contact area disposed on a third side of the display area; and a fourth contact area disposed on a fourth side of the display area.

[0022] The metal layer may include at least one of Al, Ag and Cu. to The contact region may include: a fifth contact region disposed between the first contact region and the second contact region; and a sixth contact region disposed between the third contact region and the fourth contact region.

[0023] The insulating layer may include a lower layer and an upper layer disposed on the lower layer. The lower layer may include: a first lower layer; and a second lower layer disposed on the first lower layer. The upper layer may include: a first upper layer; a second upper layer disposed on the first upper layer; and a third upper layer disposed on the second upper layer. The contact area may surround at least a portion of the display area.

[0024] Each of the first lower layer, the second lower layer, the first upper layer, the second upper layer, and the third upper layer may include silicon oxide (SiO x ) and silicon nitride (SiN x ) and having at least one of to The thickness is within the range of .

[0025] At least a portion of the second insulating layer may be connected to at least a portion of the first insulating layer so that at least a portion of the insulating layer is disposed in the display area and the non-display area. At least a portion of the second insulating layer may overlap at least another portion of the metal layer in a plan view.

[0026] The pixel circuit layer may include: a contact hole penetrating at least a portion of the pixel circuit layer; a first conductive layer disposed in the display area; and a second conductive layer disposed in the non-display area. The metal layer may be electrically connected to the second conductive layer through the contact hole.

[0027] The non-display area may surround at least a portion of the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the accompanying drawings, the size, thickness, and dimensions of elements may be exaggerated for ease of description and clarity. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may be present. Like reference numerals refer to like elements throughout.

[0030] Figures 1 to 3 is a schematic plan view illustrating a display device according to an embodiment constructed in accordance with the principles of the present disclosure.

[0031] Figure 4 and Figure 5 It shows Figure 1 Schematic plan view of an embodiment of a pixel shown in FIG.

[0032] Figure 6 It is along Figure 1 Schematic cross-sectional view of the display device taken along line AA′ shown in FIG.

[0033] Figure 7 It shows Figure 6 An enlarged schematic cross-sectional view of the lower layer and the upper layer shown in FIG.

[0034] Figure 8A and Figure 8B It shows Figure 6 sectional view of an embodiment of a light emitting structure included in a light emitting element shown in .

[0035] Figure 9 It is along Figure 1 Schematic cross-sectional view of the display device taken along line BB′ shown in FIG.

[0036] Figure 10 According to another embodiment, Figure 1Schematic cross-sectional view of the display device taken along line BB′ shown in FIG.

[0037] Figure 11 is a schematic block diagram illustrating an electrical connection structure of a light emitting element according to an embodiment.

[0038] Figure 12 is a schematic block diagram illustrating a display system according to an embodiment.

[0039] Figure 13 It shows Figure 12 Schematic perspective view of an application example of the display system shown in . DETAILED DESCRIPTION

[0040] The present disclosure can be applied to various variations and different shapes, so only specific examples are described in detail. However, the examples are not limited to specific shapes, but apply to all variations and equivalent materials and replacements. The included drawings are shown in a manner where the figures are enlarged for better understanding.

[0041] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be named as the "second" element. Unless the context clearly indicates otherwise, as used herein, the singular is intended to include the plural.

[0042] It will also be understood that when used in this specification, the terms "comprise" and / or "include" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, a statement that an element, such as a layer, region, substrate, or plate, is placed "on" or "over" another element refers not only to the case where the element is placed "directly" "on" or "directly over" the other element, but also to the case where another element is embedded between the element and the other element. Conversely, a statement that an element, such as a layer, region, substrate, or plate, is placed "under" or "below" another element refers not only to the case where the element is placed "directly" "under" or "directly under" the other element, but also to the case where another element is embedded between the element and the other element.

[0043] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within a range of ±30%, ±20%, ±10%, or ±5% of the stated value.

[0044] The term "and / or" includes all combinations that can be defined by one or more related configurations. For example, "A and / or B" can be understood to mean "A, B, or A and B".

[0045] For the purposes of this disclosure, the phrase "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0046] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an ideal or overly formal sense.

[0047] The present disclosure generally relates to a display device. Hereinafter, a display device according to an embodiment will be described with reference to the accompanying drawings.

[0048] Figures 1 to 3 is a schematic plan view illustrating a display device according to an embodiment constructed in accordance with the principles of the present disclosure.

[0049] Reference Figure 1 The display device DD is configured to emit light. The display device DD includes a light emitting element LD (see Figure 6). In some embodiments, the display device DD may be provided in various shapes. For example, the display device DD may be formed in a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In an embodiment, the first direction DR1 may be a row direction of the pixels PXL. The second direction DR2 may be a column direction of the pixels PXL. The third direction DR3 may be a display direction of the display device DD (i.e., a thickness direction of the display device DD). In some embodiments, the display device DD may be applied to a smart phone, a notebook computer, a tablet personal computer (PC), a wearable device (e.g., a head-mounted device, a smart watch, and smart glasses, etc.), a television, or a vehicle infotainment system, etc., and may also be applied to various embodiments in addition thereto.

[0050] The display device DD may include a base layer BSL and pixels PXL disposed on the base layer BSL. The display device DD may further include a driving circuit (eg, a scan driver and a data driver), lines, pads, and the like for driving the pixels PXL.

[0051] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may correspond to an area separated from the display area DA. The non-display area NDA may surround at least a portion of the display area DA.

[0052] The base layer BSL may form a base member of the display device DD. The base layer BSL may be a rigid substrate or a rigid film, or a flexible substrate or a flexible film. For example, the base layer BSL may be a rigid substrate made of glass or tempered glass. As another example, the base layer BSL may include a flexible material and may be a flexible substrate (or film) made of a plastic material or a metal material, or include at least one insulating layer. However, the material and / or properties of the base layer BSL are not particularly limited.

[0053] In some embodiments, the base layer BSL may be substantially transparent. The term "substantially transparent" may imply that light can be transmitted at a certain or higher transmittance. In another embodiment, the base layer BSL may be translucent or opaque. Furthermore, in some embodiments, the base layer BSL may include a reflective material.

[0054] In some embodiments, the base layer BSL may be provided as a silicon substrate. In some embodiments, the base layer BSL may include a silicon wafer substrate formed using a semiconductor process. The base layer BSL may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium and / or silicon germanium. The base layer BSL may be provided from a bulk wafer, an epitaxial layer, silicon on insulator (SOI) or semiconductor on insulator (SeOI), etc. In another embodiment, the base layer BSL may include a glass substrate. In yet another embodiment, the base layer BSL may include a polyimide (PI) substrate.

[0055] The display area DA may correspond to an area where the pixels PXL are disposed. The non-display area NDA may correspond to an area where no pixels PXL are disposed. Driving circuits, lines, and pads connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0056] In some embodiments, the pixel PXL (or sub-pixel SPX) may be arranged in a stripe structure or However, the embodiments described herein are not necessarily limited thereto.

[0057] In some embodiments, the pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. At least one first sub-pixel SPX1, at least one second sub-pixel SPX2, and at least one third sub-pixel SPX3 may form a pixel unit capable of emitting light of various colors. Figure 1 , each pixel PXL is shown to include three sub-pixels SPX1, SPX2, and SPX3, ie, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. However, the embodiments described herein are not limited thereto.

[0058] In some embodiments, the sub-pixel SPX may have a rectangular, square, or diamond planar shape. Figure 1 As shown in FIG, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. As another example, the subpixel SPX may have a square or diamond planar shape including sides having the same length in the first direction DR1 and the second direction DR2.

[0059] In some embodiments, the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be substantially the same, but the embodiment is not limited thereto. For example, at least one of the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be different from the other of the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3. As another example, any two of the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be substantially the same, and the other of the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be different from the two of the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3. As another example, the areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be different from each other.

[0060] The non-display area NDA may include a contact area CTA. The contact area CTA may be a region for supplying a current to one electrode (eg, the second electrode CE (see FIG. 1 )) of the light emitting element LD. Figure 6 ))Connection electrode CE2 (see Figure 9 ) and a line (eg, a second power line PL2 (see FIG. 2 ) connected to the pixel PXL) provided in the non-display area NDA. Figure 11 For example, the contact area CTA may be a region in which the connection electrode CE2 for supplying power to one electrode (e.g., the second electrode CE) of the light emitting element LD and a line (e.g., the second power line PL2) connected to the pixel PXL provided in the non-display area NDA are physically in contact with each other.

[0061] The contact area CTA may include one or more areas spaced apart from each other in a plan view.The number of the one or more areas forming the contact area CTA is not particularly limited.

[0062] According to the embodiment (see Figure 1 ), the contact area CTA may include a first contact area CTA1, a second contact area CTA2, a third contact area CTA3 and a fourth contact area CTA4.

[0063] The first contact area CTA1 may be disposed at a first side (e.g., the upper right end) of the non-display area NDA and the display area DA. The second contact area CTA2 may be disposed at a second side (e.g., the lower right end) of the non-display area NDA and the display area DA. The third contact area CTA3 may be disposed at a third side (e.g., the lower left end) of the non-display area NDA and the display area DA. The fourth contact area CTA4 may be disposed at a fourth side (e.g., the upper left end) of the non-display area NDA and the display area DA.

[0064] According to the embodiment (see Figure 2 ), the contact area CTA' may include a first contact area CTA1', a second contact area CTA2', a third contact area CTA3', a fourth contact area CTA4', a fifth contact area CTA5' and a sixth contact area CTA6'.

[0065] The first contact area CTA1' may be set at a first side (e.g., the upper right end) of the non-display area NDA and the display area DA. The second contact area CTA2' may be set at a second side (e.g., the lower right end) of the non-display area NDA and the display area DA. The third contact area CTA3' may be set at a third side (e.g., the lower left end) of the non-display area NDA and the display area DA. The fourth contact area CTA4' may be set at a fourth side (e.g., the upper left end) of the non-display area NDA and the display area DA. The fifth contact area CTA5' may be set at a fifth side (e.g., the right center) of the non-display area NDA and the display area DA. The sixth contact area CTA6' may be set at a sixth side (e.g., the left center) of the non-display area NDA and the display area DA.

[0066] Figure 2 The contact area CTA' shown in FIG can have a Figure 1 However, the embodiment is not limited thereto, and the area of the contact area CTA may vary in different implementations.

[0067] According to the embodiment (see Figure 3 ), the contact area CTA may include a single area. For example, the contact area CTA may be formed as a single area. The contact area CTA may surround at least a portion of the display area DA. In some embodiments, the contact area CTA may have a shape corresponding to an edge portion of the display area DA.

[0068] Figure 4 and Figure 5 It shows Figure 1 Schematic plan view of an embodiment of a pixel shown in FIG. Figure 4 and Figure 5The structure of the pixel PXL according to the embodiment is described.

[0069] Reference Figure 4 The first subpixel SPX1 may be arranged in the first direction DR1 with any one of the second subpixel SPX2 and the third subpixel SPX3, and arranged in the second direction DR2 with the other of the second subpixel SPX2 and the third subpixel SPX3. For example, the first subpixel SPX1 may be arranged in the first direction DR1 with the second subpixel SPX2, and may be arranged in the second direction DR2 with the third subpixel SPX3.

[0070] In some embodiments, the third subpixel SPX3 may be adjacent to the first subpixel SPX1 and the second subpixel SPX2 along the second direction DR2. In some embodiments, the areas of the first subpixel SPX1 and the second subpixel SPX2 may be substantially the same, and the area of the third subpixel SPX3 may be different from each of the areas of the first subpixel SPX1 and the second subpixel SPX2. For example, the area of the third subpixel SPX3 may be larger than each of the areas of the first subpixel SPX1 and the second subpixel SPX2.

[0071] Reference Figure 5 Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a hexagonal (or regular hexagonal) planar shape. In some embodiments, two adjacent sides of the six sides of each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may face sides of an adjacent subpixel SPX.

[0072] Figure 6 It is along Figure 1 Schematic cross-sectional view of the display device taken along line AA′ shown in FIG. Figure 6 It may be a drawing showing a cross-sectional view in the display area DA of the display device DD. Figure 7 It shows Figure 6 An enlarged schematic cross-sectional view of the lower layer and the upper layer shown in FIG. Figure 8A and Figure 8B It shows Figure 6 sectional view of an embodiment of a light emitting structure included in a light emitting element shown in FIG. Figure 6 、 Figure 7 、 Figure 8A and Figure 8B The display area DA in the display device DD is described.

[0073] Reference Figure 6 , a base layer BSL and a pixel circuit layer PCL disposed on the base layer BSL may be provided.

[0074] The base layer BSL may be a base member of the display device DD described above. The base layer BSL may include a silicon wafer substrate formed using a semiconductor process. For example, the base layer BSL may include silicon, germanium, and / or silicon germanium. Accordingly, the display device DD may be designated as an organic light-emitting diode (OLED) on silicon (OLEDoS) display device.

[0075] The pixel circuit layer PCL may include a transistor layer TL, a first protection layer PVL1 , and a second protection layer PVL2 .

[0076] The transistor layer TL may be disposed on the base layer BSL. The base layer BSL and the transistor layer TL may include circuit elements of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. For example, the base layer BSL and the transistor layer TL may include a transistor T_SP1 of the first sub-pixel SPX1, a transistor T_SP2 of the second sub-pixel SPX2, and a transistor T_SP3 of the third sub-pixel SPX3. The transistor T_SP1 of the first sub-pixel SPX1 may be any one of a plurality of transistors included in the sub-pixel circuit of the first sub-pixel SPX1, the transistor T_SP2 of the second sub-pixel SPX2 may be any one of a plurality of transistors included in the sub-pixel circuit of the second sub-pixel SPX2, and the transistor T_SP3 of the third sub-pixel SPX3 may be any one of a plurality of transistors included in the sub-pixel circuit of the third sub-pixel SPX3.

[0077] In some embodiments, the transistor may comprise a complementary metal oxide semiconductor (CMOS) circuit element. Figure 6 , for clear and brief description, one of the multiple transistors of each sub-pixel is shown, and other circuit elements are omitted for brevity and clarity.

[0078] The transistor T_SP1 of the first subpixel SPX1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0079] The source region SRA and the drain region DRA may be provided in the base layer BSL. A well WL formed by an ion implantation process may be provided in the base layer BSL, and the source region SRA and the drain region DRA may be provided in the well WL to be spaced apart from each other. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0080] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and be disposed in the transistor layer TL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0081] One or more layers included in the transistor layer TL may include an insulating layer and a conductive pattern disposed between the insulating layers, and the conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain area DRA via a drain connection portion DRC penetrating the one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source area SRA via a source connection portion SRC penetrating the one or more insulating layers.

[0082] Each of the transistor T_SP2 of the second subpixel SPX2 and the transistor T_SP3 of the third subpixel SPX3 may be configured identically to the transistor T_SP1 of the first subpixel SPX1 .

[0083] As such, the base layer BSL and the transistor layer TL may include circuit elements of each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 .

[0084] The first protective layer PVL1 may be provided on the transistor layer TL. The first protective layer PVL1 covers the transistor layer TL and may have a completely flat surface. The first protective layer PVL1 is configured to flatten the step difference on the transistor layer TL. The first protective layer PVL1 may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the embodiment is not limited thereto.

[0085] On the first protection layer PVL1, the (1_1)th conductive layer SL1_1, the (1_2)th conductive layer SL1_2, and the (1_3)th conductive layer SL1_3 are respectively provided in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Each of the (1_1)th conductive layer SL1_1, the (1_2)th conductive layer SL1_2, and the (1_3)th conductive layer SL1_3 can contact a circuit element provided in the transistor layer TL through a via hole penetrating the first protection layer PVL1.

[0086] In the embodiments described herein, the first conductive layer SL1 is a conductive layer disposed in the display area DA and may supply an electrical signal to the first electrode AE of the light emitting element LD.

[0087] In order to flatten the step differences between the (1_1)th conductive layer SL1_1, the (1_2)th conductive layer SL1_2, and the (1_3)th conductive layer SL1_3, a second protective layer PVL2 may be provided over the (1_1)th conductive layer SL1_1, the (1_2)th conductive layer SL1_2, and the (1_3)th conductive layer SL1_3. The second protective layer PVL2 completely covers the (1_1)th conductive layer SL1_1, the (1_2)th conductive layer SL1_2, the (1_3)th conductive layer SL1_3, and the first protective layer PVL1, and has a flat surface.

[0088] In some embodiments, the second protective layer PVL2 may be a via layer including vias (e.g., first vias VIA1, second vias VIA2, and third vias VIA3) for electrically connecting the light emitting element LD and the first conductive layer SL1 to each other, and a via for electrically connecting the connection electrode CE2 (see FIG. Figure 9 ) and the second conductive layer SL2 (see Figure 9 ) contact holes CNT electrically connected to each other (see Figure 9 In some embodiments, the second protection layer PVL2 may be disposed at an outermost portion (or an uppermost portion) of the pixel circuit layer PCL and planarize a surface of the pixel circuit layer PCL.

[0089] The light emitting element layer LDL may be disposed on the second protective layer PVL2. The light emitting element layer LDL may include a first electrode AE, a lower layer IL, an upper layer PDL, a light emitting structure EMS, and a second electrode CE.

[0090] The first electrode AE may be disposed on the second protective layer PVL2. The first electrodes AE1 to AE3 may include a (1_1)th electrode AE1, a (1_2)th electrode AE2, and a (1_3)th electrode AE3. The (1_1)th electrode AE1, the (1_2)th electrode AE2, and the (1_3)th electrode AE3, which overlap with the (1_1)th conductive layer SL1_1, the (1_2)th conductive layer SL1_2, and the (1_3)th conductive layer SL1_3, respectively, may be disposed on the second protective layer PVL2. The (1_1)th electrode AE1 may be connected to the (1_1)th conductive layer SL1_1 through a first via hole VIA1 penetrating the second protective layer PVL2. The (1_2)th electrode AE2 may be connected to the (1_2)th conductive layer SL1_2 through a second via hole VIA2 penetrating the second protective layer PVL2. The (1_3)th electrode AE3 may be connected to the (1_3)th conductive layer SL1_3 through a third via hole VIA3 penetrating the second protective layer PVL2.

[0091] In an embodiment, each of the (1_1)th electrode AE1, the (1_2)th electrode AE2, and the (1_3)th electrode AE3 may be an anode electrode of the light emitting element LD. The (1_1)th electrode AE1, the (1_2)th electrode AE2, and the (1_3)th electrode AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the embodiment is not limited thereto. For example, the (1_1)th electrode AE1, the (1_2)th electrode AE2, and the (1_3)th electrode AE3 may include at least one of Al, Ag, and Cu, and further include at least one of indium tin oxide (ITO), titanium (Ti), and titanium nitride (TiN).

[0092] In some embodiments, the first electrode AE may have a single-layer structure including at least one of Al, Ag, and Cu. In some embodiments, the first electrode AE may have a three-layer structure in which a layer including at least one of Al, Ag, and Cu is stacked on a layer including at least one of indium tin oxide (ITO), titanium (Ti), and titanium nitride (TiN), and a layer including at least one of indium tin oxide (ITO), titanium (Ti), and titanium nitride (TiN) is stacked on the layer including at least one of Al, Ag, and Cu. However, embodiments are not limited thereto, and the first electrode AE may include a metal having high reflectivity.

[0093] The insulating layer 100 may be disposed on portions of the first electrode AE and the second protective layer PVL2. The insulating layer 100 may include a lower layer IL and an upper layer PDL. However, the embodiment is not limited thereto, and in some embodiments, the lower layer IL may be omitted.

[0094] The lower layer IL may be disposed below the upper layer PDL. Hereinafter, in the embodiments described herein, a lower direction is defined as an opposite direction of the third direction DR3, and an upper direction is defined as the third direction DR3.

[0095] The lower layer IL and the upper layer PDL may include an opening OP exposing a portion of the first electrode AE. The lower layer IL and the upper layer PDL may be pixel defining layers defining an emission area, and the opening OP may define an emission area of each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3.

[0096] Reference Figure 7 Combined with Figure 6 In an embodiment, the lower IL and the upper PDL may include one or more inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x) and silicon nitride (SiN x For example, the lower layer IL may include a first lower layer IL1 and a second lower layer IL2 sequentially stacked, and each of the first lower layer IL1 and the second lower layer IL2 may include silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of.

[0097] For example, the upper layer PDL may include a first upper layer PDL1, a second upper layer PDL2, and a third upper layer PDL3 sequentially stacked on the lower layer IL, and each of the first upper layer PDL1, the second upper layer PDL2, and the third upper layer PDL3 may include silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of the following. However, the embodiment is not limited thereto, and the number of layers constituting the lower layer IL and the number of layers constituting the upper layer PDL may vary. For example, in some embodiments, the lower layer IL may be omitted, and the upper layer PDL may include a first upper layer PDL1, a second upper layer PDL2, and a third upper layer PDL3. As another example, in some embodiments, the upper layer PDL may be formed as a single layer including the first upper layer PDL1 or a double layer including the first upper layer PDL1 and the second upper layer PDL2.

[0098] In some embodiments, each of the first lower layer IL1, the second lower layer IL2, the first upper layer PDL1, the second upper layer PDL2, and the third upper layer PDL3 may have a thickness of about 100 nm. to approximately The thickness is within the range of .

[0099] A spacer SPR may be provided in a boundary area BDA between sub-pixels adjacent to each other.

[0100] The spacer SPR may cause a discontinuous portion to be formed in the light emitting structure EMS in the boundary area BDA. For example, the light emitting structure EMS may be cut or bent by the spacer SPR in the boundary area BDA.

[0101] The spacer SPR may be provided in or on the upper PDL and the lower IL. The upper PDL and the lower IL may include one or more trenches TRCH1 and TRCH2 as the spacer SPR in the boundary area BDA. In an embodiment, as shown in FIG. Figure 6 As shown in FIG, one or more trenches TRCH1 and TRCH2 may penetrate the upper layer PDL and the lower layer IL and partially penetrate the second protective layer PVL2. However, embodiments are not limited thereto.

[0102] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first void VD1 and the second void VD2 may be formed in the light emitting structure EMS in the boundary area BDA. Some layers stacked in the light emitting structure EMS may be cut or bent by the first void VD1 and the second void VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be cut in the first void VD1 and the second void VD2. Thus, due to the first trench TRCH1 and the second trench TRCH2, portions of the light emitting structure EMS included in the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be at least partially separated from each other.

[0103] exist Figure 6 , the first voids VD1 and the second voids VD2 are shown to be formed in the light emitting structure EMS in the boundary area BDA. However, this is merely illustrative, and embodiments are not limited thereto. For example, a concave valley may be formed in the light emitting structure EMS in the boundary area BDA. The discontinuities formed in the light emitting structure EMS may vary depending on the shapes of the first trench TRCH1 and the second trench TRCH2.

[0104] In some embodiments, the light emitting structure EMS may be formed by a process such as vacuum deposition or inkjet printing. The same material as the light emitting structure EMS may be located on the bottom surfaces of the first and second trenches TRCH1 and TRCH2 adjacent to the first protective layer PVL1.

[0105] The light emitting structure EMS may be disposed on the first electrode AE exposed by the opening OP. The light emitting structure EMS fills the opening OP and may be completely disposed within the first, second, and third subpixels SPX1, SPX2, and SPX3.

[0106] The light-emitting structure EMS may be at least partially cut off or bent by the partition SPR in the boundary area BDA. Accordingly, during operation of the display device DD, current leaking from each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 through the layers included in the light-emitting structure EMS to subpixels adjacent to each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be reduced. Consequently, the light-emitting element LD may operate with relatively high reliability.

[0107] Reference Figure 8A In some embodiments, the light emitting structure EMS may have a series structure in which the first light emitting structure EU1 and the second light emitting structure EU2 are stacked. Figure 6 Each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 is configured substantially identically.

[0108] Each of the first and second light-emitting structures EU1 and EU2 may include a light-generating layer that generates light according to an applied current. The first light-emitting structure EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting structure EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0109] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a hole buffer layer and an electron blocking layer. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0110] Each of the first electron transport unit (ETU1) and the second electron transport unit (ETU2) may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first electron transport unit (ETU1) and the second electron transport unit (ETU2) may further include an electron buffer layer and a hole blocking layer. The first electron transport unit (ETU1) and the second electron transport unit (ETU2) may have the same configuration or different configurations.

[0111] A connection layer, which may be provided in the form of a charge generation layer CGL, may be provided between the first light-emitting structure EU1 and the second light-emitting structure EU2 to connect the first light-emitting structure EU1 and the second light-emitting structure EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-type dopant layer and an n-type dopant layer. For example, the p-type dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-type dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or any combination thereof. However, embodiments are not limited thereto.

[0112] In embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can generate light of different colors. The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2, respectively, can be mixed together to be observed as white light. For example, the first light-emitting layer EML1 can generate blue light, and the second light-emitting layer EML2 can generate yellow light. In embodiments, the second light-emitting layer EML2 can include a structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. The red light and the green light can be mixed together to provide yellow light. An intermediate layer configured to perform the function of transporting holes and / or the function of blocking the transport of electrons can be further provided between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0113] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color.

[0114] In the above, although the embodiment of the light emitting structure EMS having a series structure in which the first light emitting structure EU1 and the second light emitting structure EU2 are stacked has been illustrated, the embodiment is not limited thereto. Figure 8B Combined with Figure 6 , the light emitting structure EMS' may be a series structure in which the first to third light emitting structures EU1' to EU3' are stacked. The light emitting structure EMS' may be Figure 6 Each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 is configured substantially identically.

[0115] Each of the first to third light-emitting structures EU1' to EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting structure EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting structure EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting structure EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0116] In some embodiments, each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration or different configurations.

[0117] In some embodiments, each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0118] The first charge generation layer CGL1' may be disposed between the first light emitting structure EU1' and the second light emitting structure EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting structure EU2' and the third light emitting structure EU3'.

[0119] In an embodiment, the first to third light-emitting layers EML1' to EML3' may generate light of different colors. The light emitted from the first to third light-emitting layers EML1' to EML3' may be mixed together to be observed as white light. For example, the first light-emitting layer EML1' may generate blue light, the second light-emitting layer EML2' may generate green light, and the third light-emitting layer EML3' may generate red light.

[0120] In other embodiments, at least two light-emitting layers among the first to third light-emitting layers EML1 ′ to EML3 ′ may generate light of the same color.

[0121] In some embodiments, each of the first to third light-emitting elements LD1 to LD3 may include a light-emitting structure. The light-emitting structures included in the first to third light-emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light-emitting structure of the first light-emitting element LD1 may emit red light, the light-emitting structure of the second light-emitting element LD2 may emit green light, and the light-emitting structure of the third light-emitting element LD3 may emit blue light. Figure 6 Unlike that shown in , portions of the light emitting structure EMS corresponding to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be separated from each other, and each of the portions of the light emitting structure EMS corresponding to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be disposed in the opening OP of the upper PDL. In some embodiments of the present invention, at least one of the color filters CF1 to CF3 may be omitted.

[0122] The second electrode CE may be provided on the light emitting structure EMS. The second electrode CE may be a cathode electrode of the light emitting element LD. The second electrode CE may be provided in common in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The second electrode CE may function as a semi-reflective mirror that allows light emitted from the light emitting structure EMS to partially transmit therethrough and allows light emitted from the light emitting structure EMS to partially reflect therefrom.

[0123] The (1_1)th electrode AE1, the portion of the light emitting structure EMS overlapping with the (1_1)th electrode AE1, and the portion of the second electrode CE overlapping with the (1_1)th electrode AE1 may constitute a first light emitting element LD1. The (1_2)th electrode AE2, the portion of the light emitting structure EMS overlapping with the (1_2)th electrode AE2, and the portion of the second electrode CE overlapping with the (1_2)th electrode AE2 may constitute a second light emitting element LD2. The (1_3)th electrode AE3, the portion of the light emitting structure EMS overlapping with the (1_3)th electrode AE3, and the portion of the second electrode CE overlapping with the (1_3)th electrode AE3 may constitute a third light emitting element LD3.

[0124] The thin film encapsulation layer TFE may be provided over the second electrode CE. The thin film encapsulation layer TFE may prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0125] The optically functional layer OFL may be disposed on the thin film encapsulation layer TFE. In embodiments, the optically functional layer OFL may be attached to the thin film encapsulation layer TFE via an adhesive layer APL. For example, the optically functional layer OFL may be separately manufactured and attached to the thin film encapsulation layer TFE via the adhesive layer APL. The adhesive layer APL may also function to protect underlying layers including the thin film encapsulation layer TFE.

[0126] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3, respectively. The first to third color filters CF1 to CF3 may allow light having different wavelength ranges to pass therethrough. For example, the first to third color filters CF1 to CF3 may allow red, green, and blue light to pass therethrough, respectively.

[0127] In an embodiment, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0128] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3, respectively. The first to third lenses LS1 to LS3 may output light emitted from the first to third light-emitting elements LD1 to LD3 along desired paths, thereby improving luminous efficiency.

[0129] An overcoat layer OC may be provided on the lens array LA. The overcoat layer OC may cover the optical functional layer OFL, the thin film encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the layers below the overcoat layer OC from foreign matter such as dust or moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer OC may include an epoxy resin, but the embodiment is not limited thereto. The overcoat layer OC may have a refractive index lower than that of the lens array LA.

[0130] A cover window CW may be disposed on the overcoat layer OC. The cover window CW is configured to protect layers beneath the cover window CW. The cover window CW may have a refractive index higher than that of the overcoat layer OC. The cover window CW may comprise glass, but embodiments are not limited thereto. For example, the cover window CW may be encapsulation glass configured to protect components disposed beneath the cover window CW. In other embodiments, the cover window CW may be omitted.

[0131] Figure 9 It is along Figure 1 , a schematic cross-sectional view of the display device taken along line BB' shown in FIG. Figure 9 A cross-sectional view of the display device DD in the display area DA and the non-display area NDA is shown. Figure 9 , for clarity and simplicity of description, only the base layer BSL, the pixel circuit layer PCL, and the light emitting element layer LDL are shown. Figure 10 According to another embodiment, Figure 1 Schematic cross-sectional view of the display device taken along line BB′ shown in FIG.

[0132] In the following, reference will be made to Figures 9 and 10 Components provided in the non-display area NDA of the display device DD according to the embodiment are described.

[0133] Reference Figure 9The display device DD may include a connection electrode CE2 disposed in the non-display area NDA. The connection electrode CE2 may be connected to the second electrode CE disposed in the display area DA. The connection electrode CE2 may be formed integrally with the second electrode CE disposed in the display area DA. For example, the connection electrode CE2 may be a cathode electrode disposed in the non-display area NDA. The connection electrode CE2 may be formed using the same process as the second electrode CE disposed in the display area DA. For example, the second electrode CE may be deposited using the same process as the connection electrode CE2 and may include the same material as the connection electrode CE2.

[0134] The light emitting element layer LDL may further include a metal layer ML. The metal layer ML may be disposed on the pixel circuit layer PCL (or the second protective layer PVL2 ). The metal layer ML may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2 ).

[0135] The metal layer ML may contact the first electrode AE (see FIG. Figure 6 ) are formed by the same process. For example, the metal layer ML can be deposited by the same process as the first electrode AE and include the same material as the first electrode AE. For example, the metal layer ML can include at least one of Al, Ag, and Cu, and further include at least one of indium tin oxide (ITO), titanium (Ti), and titanium nitride (TiN).

[0136] In some embodiments, the metal layer ML may have a single-layer structure including at least one of Al, Ag, and Cu. In some embodiments, the metal layer ML may have a three-layer structure in which a layer including at least one of Al, Ag, and Cu is stacked on a layer including at least one of indium tin oxide (ITO), titanium (Ti), and titanium nitride (TiN), and a layer including at least one of indium tin oxide (ITO), titanium (Ti), and titanium nitride (TiN) is stacked on the layer including at least one of Al, Ag, and Cu. However, embodiments are not limited thereto, and the metal layer ML may include a metal having high reflectivity.

[0137] At least a portion of the metal layer ML may contact at least a portion of the connection electrode CE2. At least a portion of a top surface of the metal layer ML may contact at least a portion of the connection electrode CE2. The metal layer ML may be electrically connected to the connection electrode CE2.

[0138] The metal layer ML may have a to approximately The metal layer ML may have a thickness in the range of about to approximately and reduces the risk that the connection electrode CE2 will be disconnected.

[0139] The second protection layer PVL2 (or the pixel circuit layer PCL) may further include a second conductive layer SL2 and a contact hole CNT disposed in the non-display area NDA.

[0140] The second conductive layer SL2 may be aligned with the first conductive layer SL1 (see FIG. Figure 6 For example, the second conductive layer SL2 may be deposited by the same process as the first conductive layer SL1, and accordingly, the second conductive layer SL2 and the first conductive layer SL1 may have the same material.

[0141] The second conductive layer SL2 may be electrically connected to the second electrode CE. The second conductive layer SL2 may be electrically connected to the metal layer ML, and the metal layer ML may be electrically connected to the connection electrode CE2. The connection electrode CE2 may be electrically connected to the second electrode CE. Accordingly, the second conductive layer SL2 may enable the second power line PL2 (see FIG. 1 ) to be electrically connected to the second power line PL2. Figure 11 ) and the second electrode CE are electrically connected to each other. This will be referred to later. Figure 11 describe.

[0142] The contact hole CNT may include a first contact hole CNT1 and a second contact hole CNT2. In some embodiments, a plurality of contact holes CNT may be provided. For example, six contact holes CNT may be formed. However, the number of contact holes CNT is not limited thereto. In some embodiments, the number of contact holes CNT may vary.

[0143] The contact hole CNT may connect the metal layer ML and the pixel circuit layer PCL (eg, the second conductive layer SL2 ) to each other while penetrating at least a portion of the second protection layer PVL2 (or the pixel circuit layer PCL).

[0144] The contact hole CNT may include a conductive material. The contact hole CNT may be filled with a conductive material. For example, the contact hole CNT may include tungsten (W). The contact hole CNT may include a conductive material and electrically connect the metal layer ML and the second conductive layer SL2 to each other. The second electrode CE may be electrically connected to the second conductive layer SL2 through the metal layer ML.

[0145] Because the second electrode CE is connected to the second conductive layer SL2 via the metal layer ML, the display device DD according to this embodiment can prevent the risk of the second electrode CE being disconnected. Experimentally, the surface of the contact hole CNT is not substantially flat in the contact area CTA, and therefore, a step difference may be formed. In the absence of the metal layer ML, the second electrode CE is formed on an uneven surface. Consequently, the second electrode CE may be disconnected in the contact area CTA.

[0146] In contrast, in the display device DD according to the embodiment, the metal layer ML is disposed on the contact hole CNT, thereby providing a substantially flat surface. Accordingly, the risk that the second electrode CE will be disconnected in the contact area CTA can be reduced.

[0147] The insulating layer 100 may be disposed in the display area DA and the non-display area NDA. Hereinafter, the lower layer IL and the upper layer PDL disposed in the display area DA are defined as a first insulating layer, and the lower layer IL and the upper layer PDL disposed in the non-display area NDA are defined as a second insulating layer.

[0148] At least a portion of the second insulating layer may be connected to at least a portion of the first insulating layer. For example, at least a portion of the second insulating layer may be connected to at least a portion of the first insulating layer, so that at least a portion of the insulating layer 100 is formed in the display area DA and the non-display area NDA. For example, the first lower layer IL1 may be formed in the display area DA and the non-display area NDA. The first lower layer IL1 may extend from the display area DA to the non-display area NDA.

[0149] At least a portion of the second insulating layer may be in contact with at least a portion of the metal layer ML. At least a portion of the second insulating layer may be in contact with a side surface of the metal layer ML. In a plan view, at least a portion of the second insulating layer may overlap with at least a portion of the metal layer ML. At least a portion of the second insulating layer may expose the top surface of the metal layer ML. At least a portion of the second insulating layer in contact with at least a portion of the metal layer ML may be the first lower layer IL1.

[0150] For example, the first lower layer IL1 may be in contact with at least a portion of the metal layer ML. The first lower layer IL1 may be in contact with the side surface of the metal layer ML. The first lower layer IL1 may cover the side surface of the metal layer ML. The first lower layer IL1 may be in contact with at least a portion of the top surface of the metal layer ML. The first lower layer IL1 may cover at least a portion of the top surface of the metal layer ML. In a plan view, at least a portion of the first lower layer IL1 may overlap with at least a portion of the metal layer ML. An end portion (or edge) of the first lower layer IL1 may be in contact with the metal layer ML.

[0151] At least a portion of the second insulating layer may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2). For example, the first lower layer IL1 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2). The first lower layer IL1 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the non-display area NDA. In the display device DD according to the embodiment, at least a portion of the second insulating layer may be provided on the pixel circuit layer PCL (or the second protective layer PVL2) in the electrode deposition area S, and accordingly, the risk of the second electrode CE being disconnected may be reduced.

[0152] The first lower layer IL1 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the electrode deposition region S. At least a portion of the second insulating layer may be disposed on a bottom portion of at least a portion of the connection electrode CE2. For example, the first lower layer IL1 may be disposed on a bottom portion of the connection electrode CE2 in the electrode deposition region S. At least a portion of the first lower layer IL1 may be in contact with at least a portion of the connection electrode CE2.

[0153] Experimentally, when the second insulating layer is not provided in the electrode deposition area S, the connection electrode CE2 may be directly deposited on the pixel circuit layer PCL in the electrode deposition area S. Due to the step difference of the surface of the pixel circuit layer PCL, the connection electrode CE2 may not be properly deposited (for example, the connection electrode CE2 may not be deposited in a partial area) and may be disconnected in the electrode deposition area S. On the other hand, in the display device DD according to the embodiment, since at least a portion of the second insulating layer is provided on the pixel circuit layer PCL in the electrode deposition area S, the step difference of the surface of the pixel circuit layer PCL can be reduced, and the risk of disconnection of the connection electrode CE2 can be reduced.

[0154] The first lower layer IL1, the second lower layer IL2, the first upper layer PDL1, the second upper layer PDL2, and the third upper layer PDL3 may have end portions that are inconsistent with each other. For example, the insulating layer 100 may have a stepped end portion. However, the embodiment is not limited thereto, and at least some of the first lower layer IL1, the second lower layer IL2, the first upper layer PDL1, the second upper layer PDL2, and the third upper layer PDL3 may have end portions that are consistent with each other.

[0155] In the above, although Figure 9 illustratively shows an embodiment in which the first lower layer IL1 extends from the display area DA to the non-display area NDA, but the embodiment is not limited thereto.

[0156] For example, refer to Figure 10 , the second lower layer IL2 may extend from the display area DA to the non-display area NDA. The second lower layer IL2 may cover the first lower layer IL1 in the display area DA.

[0157] At least a portion of the second insulating layer that contacts at least a portion of the metal layer ML may be the second lower layer IL2. The second lower layer IL2 may contact at least a portion of the metal layer ML. The second lower layer IL2 may contact a side surface of the metal layer ML. The second lower layer IL2 may cover a side surface of the metal layer ML. The second lower layer IL2 may contact a top surface of the metal layer ML. The second lower layer IL2 may cover at least a portion of the top surface of the metal layer ML. In a plan view, at least a portion of the second lower layer IL2 may overlap with at least a portion of the metal layer ML. An end portion (or edge) of the second lower layer IL2 may contact the metal layer ML.

[0158] The second lower layer IL2 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2). The second lower layer IL2 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the non-display area NDA. The second lower layer IL2 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the electrode deposition area S. The second lower layer IL2 may be disposed on the bottom of the connection electrode CE2 in the electrode deposition area S. At least a portion of the second lower layer IL2 may be in contact with at least a portion of the connection electrode CE2.

[0159] In the above, although Figure 9 and Figure 10 , a portion of the lower layer IL extends from the display area DA to the non-display area NDA, but the embodiment is not limited thereto. In some embodiments, one of the first upper layer PDL1, the second upper layer PDL2, and the third upper layer PDL3 may extend from the display area DA to the non-display area NDA.

[0160] For example, the first upper layer PDL1 may extend from the display area DA to the non-display area NDA. The first upper layer PDL1 may cover the lower layer IL in the display area DA.

[0161] At least a portion of the second insulating layer that contacts at least a portion of the metal layer ML may be the first upper layer PDL1. The first upper layer PDL1 may contact at least a portion of the metal layer ML. The first upper layer PDL1 may contact the side surface of the metal layer ML. The first upper layer PDL1 may cover the side surface of the metal layer ML. The first upper layer PDL1 may contact at least a portion of the top surface of the metal layer ML. In a plan view, at least a portion of the first upper layer PDL1 may overlap with at least a portion of the metal layer ML. An end portion (or edge) of the first upper layer PDL may contact the metal layer ML.

[0162] The first upper layer PDL1 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2). The first upper layer PDL1 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the non-display area NDA. The first upper layer PDL1 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the electrode deposition area S. The first upper layer PDL1 may be disposed on the bottom of the connection electrode CE2 in the electrode deposition area S. At least a portion of the first upper layer PDL1 may be in contact with at least a portion of the connection electrode CE2.

[0163] In some embodiments, the second upper layer PDL2 may extend from the display area DA to the non-display area NDA. The second upper layer PDL2 may cover the first upper layer PDL1 and the lower layer IL in the display area DA.

[0164] At least a portion of the second insulating layer that contacts at least a portion of the metal layer ML may be the second upper layer PDL2. The second upper layer PDL2 may contact at least a portion of the metal layer ML. The second upper layer PDL2 may contact the side surface of the metal layer ML. The second upper layer PDL2 may cover the side surface of the metal layer ML. The second upper layer PDL2 may contact at least a portion of the top surface of the metal layer ML. The second upper layer PDL2 may cover at least a portion of the top surface of the metal layer. In a plan view, at least a portion of the second upper layer PDL2 may overlap with at least a portion of the metal layer ML. An end portion (or edge) of the second upper layer PDL2 may contact the metal layer ML.

[0165] The second upper layer PDL2 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2). The second upper layer PDL2 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the non-display area NDA. The second upper layer PDL2 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the electrode deposition area S. The second upper layer PDL2 may be disposed on the bottom of the connection electrode CE2 in the electrode deposition area S. At least a portion of the second upper layer PDL2 may be in contact with at least a portion of the connection electrode CE2.

[0166] In some embodiments, the third upper layer PDL3 may extend from the display area DA to the non-display area NDA.The third upper layer PDL3 may cover the second upper layer PDL2, the first upper layer PDL1, and the lower layer IL.

[0167] At least a portion of the second insulating layer that contacts at least a portion of the metal layer ML may be the third upper layer PDL3. The third upper layer PDL3 may contact at least a portion of the metal layer ML. The third upper layer PDL3 may contact the side surface of the metal layer ML. The third upper layer PDL3 may cover the side surface of the metal layer ML. The third upper layer PDL3 may contact at least a portion of the top surface of the metal layer ML. The third upper layer PDL3 may cover at least a portion of the top surface of the metal layer ML. In a plan view, at least a portion of the third upper layer PDL3 may overlap with at least a portion of the metal layer ML. An end portion (or edge) of the third upper layer PDL3 may contact the metal layer ML.

[0168] The third upper layer PDL3 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2). The third upper layer PDL3 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the non-display area NDA. The third upper layer PDL3 may be in contact with the pixel circuit layer PCL (or the second protective layer PVL2) in the electrode deposition area S. The third upper layer PDL3 may be disposed on the bottom of the connection electrode CE2 in the electrode deposition area S. At least a portion of the third upper layer PDL3 may be in contact with at least a portion of the connection electrode CE2.

[0169] In the following, reference will be made to Figure 11 Describe the electrical connections between circuit elements. Figure 11 is a schematic block diagram illustrating an electrical connection structure of a light emitting element according to an embodiment.

[0170] Reference Figure 11 Combined with Figure 6 , the sub-pixel SPX may include a pixel circuit PXC configured to drive the light emitting element LD.

[0171] The pixel circuit PXC may include at least one circuit element. For example, the pixel circuit PXC may include a transistor and a storage capacitor. For example, the pixel circuit PXC may include a driving transistor, a switching transistor, and a storage capacitor. However, the embodiment is not necessarily limited thereto.

[0172] The pixel circuit PXC may be electrically connected to a scan line SL and a data line DL. The scan line SL may supply a scan signal to the pixel circuit PXC. In some embodiments, the scan line SL may be electrically connected to a gate electrode of a switching transistor of the pixel circuit PXC. The light-emitting element LD may be configured to emit light corresponding to a data signal provided from the data line DL.

[0173] The pixel circuit PXC may be electrically connected to a first power line PL1 and a second power line PL2. For example, the first electrode AE of the light-emitting element LD may be electrically connected to the pixel circuit PXC and the first power line PL1, and the second electrode CE of the light-emitting element LD may be electrically connected to the second power line PL2. The first power line PL1 and the second power line PL2 may be disposed on the base layer BSL.

[0174] The power of the first power line PL1 and the power of the second power line PL2 can have different potentials. For example, the power of the first power line PL1 can be high-potential pixel power supplied with power from the first voltage potential VDD, and the power of the second power line PL2 can be low-potential pixel power supplied with power from the second voltage potential VSS. The potential difference between the power of the first power line PL1 and the power of the second power line PL2 can be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0175] The first power line PL1 may be electrically connected to the pixel circuit PXC (eg, a driving transistor) and the second power line PL2 may be electrically connected to a cathode electrode (eg, a second electrode CE) of the light emitting element LD.

[0176] In some embodiments, the second power line PL2 can be electrically connected to the second electrode CE. For example, power can be applied to the second electrode CE via the second power line PL2 disposed in the non-display area NDA. In some embodiments, the second electrode CE disposed in the display area DA can be adjacent to the connection electrode CE2 disposed in the non-display area NDA. The second electrode CE disposed in the display area DA can be electrically connected to the connection electrode CE2 disposed in the non-display area NDA. The connection electrode CE2 in the non-display area DA can be electrically connected to the second conductive layer SL2 via the metal layer ML. In some embodiments, the second conductive layer SL2 described above can be adjacent to the second power line PL2. The second conductive layer SL2 can be electrically connected to the second power line PL2. Accordingly, the second power line PL2 can apply power to the connection electrode CE2 via the second conductive layer SL2.

[0177] Accordingly, the second electrode CE formed in the display area DA can be electrically connected to the second power line PL2 in the non-display area NDA. As described above, since the second electrode CE in the display area DA and the second power line PL2 are electrically connected to each other, the power provided by the second power line PL2 can be applied to the entire display area DA.

[0178] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 in a forward direction to form effective light sources, respectively. These effective light sources are aggregated to form the light emitting element LD of the sub-pixel SPX.

[0179] The light emitting element LD can emit light at a brightness corresponding to the driving current supplied by the pixel circuit PXC. The pixel circuit PXC can supply a driving current corresponding to the data signal to the light emitting element LD during each frame period. The light emitting element LD can emit light at a brightness corresponding to the current flowing through the light emitting element LD.

[0180] In the following, reference will be made to Figure 12 and Figure 13 A display system 1000 to which the display device DD can be applied is described.

[0181] Figure 12 is a schematic block diagram illustrating a display system according to an embodiment. Figure 13 It shows Figure 12 Schematic perspective view of an application example of the display system shown in .

[0182] Reference Figure 12 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0183] The processor 1100 can perform various tasks and various calculations. In an embodiment, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, and a central processing unit (CPU). The processor 1100 can be connected to other components of the display system 1000 through a bus system to control the components of the display system 1000.

[0184] exist Figure 12 , it is shown that the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and connected to the second display device 1220 through a second channel CH2.

[0185] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The display device DD described above is configured identically. The first image data IMG1 and the first control signal CTRL1 may be provided to the display device DD as input image data and a control signal, respectively. Figure 1 The display device DD shown in .

[0186] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display devices DD described are configured identically.

[0187] The display system 1000 may include a computing system for providing an image display function (such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra-mobile computer (UMPC)). In addition, the display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0188] Reference Figure 13 , Figure 12 The display system 1000 shown in FIG. 1 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0189] The head-mounted display device 2000 may include a head-mounted strap 2100 and a display device housing box 2200. The head-mounted strap 2100 may be connected to the display device housing box 2200. The head-mounted strap 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to surround the side portions of the user's head, and the vertical strap may be configured to surround the upper portion of the user's head (e.g., the user's forehead). However, embodiments are not limited thereto. For example, the head-mounted strap 2100 may be implemented in the form of a glasses frame or a helmet.

[0190] The display device receiving box 2200 can receive Figure 12 The first display device 1210 and the second display device 1220 are shown in FIG. The display device container 2200 can also accommodate Figure 12 The processor 1100 shown in FIG.

[0191] According to the embodiments described above, a display device capable of reducing the risk that an electrode (eg, a cathode electrode) will be disconnected can be provided.

[0192] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, unless otherwise specifically noted, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, as would be apparent to one of ordinary skill in the art at the time of filing this application. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, characterized in that: The display device includes: a display area and a non-display area, pixels are arranged in the display area, and the non-display area corresponds to an area separated from the display area; a pixel circuit layer, comprising a pixel circuit; A first electrode is provided on the pixel circuit layer; an insulating layer having at least a portion exposing the first electrode; a second electrode disposed in the display area; and A connecting electrode is formed integrally with the second electrode, and the connecting electrode is arranged in the non-display area, wherein: The insulating layer comprises: A first insulating layer is provided in the display area; and A second insulating layer is provided in the non-display area, and The second insulating layer contacts at least a portion of the connecting electrode.

2. The display device according to claim 1, wherein The display device further includes: A metal layer is provided in the non-display area, and the metal layer is provided on the pixel circuit layer, wherein: In a plan view, at least a portion of the second insulating layer overlaps with at least a portion of the metal layer, The second insulating layer exposes the top surface of the metal layer, An end portion of the second insulating layer is in contact with the connection electrode, and The connecting electrode contacts at least a portion of the top surface of the metal layer.

3. The display device according to claim 1, wherein The insulating layer includes a lower layer and an upper layer provided on the lower layer, At least a portion of the insulating layer extends from the display area to the non-display area, and The lower layer includes: First Lower Level; and a second lower layer disposed on the first lower layer, and The upper layer includes: First upper level; a second upper layer disposed on the first upper layer; and The third upper layer is arranged on the second upper layer.

4. The display device according to claim 1, wherein At least a portion of the second insulating layer is connected to at least a portion of the first insulating layer, so that at least a portion of the insulating layer is disposed in the display area and the non-display area.

5. The display device according to claim 1, wherein The pixel circuit layer includes: a first protective layer; and a second protective layer, disposed on the first protective layer; The second protective layer is provided at the uppermost portion of the pixel circuit layer, and At least a portion of the second insulating layer is in contact with the second protective layer.

6. The display device according to claim 2, wherein: At least a portion of the second insulating layer covers the side surface of the metal layer, and The pixel circuit layer includes: a contact hole penetrating at least a portion of the pixel circuit layer; A first conductive layer is provided in the display area; and A second conductive layer is provided in the non-display area, and The metal layer is electrically connected to the second conductive layer through the contact hole.

7. A display device, characterized in that: The display device includes: a display area and a non-display area, pixels being arranged in the display area, the non-display area corresponding to an area separated from the display area; a pixel circuit layer, comprising a pixel circuit; a first power line and a second power line electrically connected to the pixel circuit; a first electrode, disposed on the pixel circuit layer; an insulating layer having at least a portion exposing the first electrode; a second electrode disposed in the display area; and A metal layer is provided on the pixel circuit layer in the non-display area, wherein: The insulating layer comprises: A first insulating layer is provided in the display area; and A second insulating layer is provided in the non-display area. The second insulating layer contacts at least a portion of the metal layer, and The non-display area includes a contact area in which the second power line and the connection electrode are electrically connected to each other.

8. The display device according to claim 7, wherein: The display device further includes: The connecting electrode is formed integrally with the second electrode and is disposed in the non-display area, wherein: The connection electrode contacts at least a portion of the top surface of the metal layer, and The contact area includes: a first contact area, disposed at a first side of the display area; a second contact area, disposed at a second side of the display area; a third contact area disposed at a third side of the display area; and The fourth contact area is arranged at a fourth side of the display area.

9. The display device according to claim 8, wherein The metal layer has to The thickness is within the range of The contact area includes: a fifth contact region disposed between the first contact region and the second contact region; and The sixth contact region is arranged between the third contact region and the fourth contact region.

10. The display device according to claim 7, wherein: The insulating layer includes a lower layer and an upper layer provided on the lower layer, wherein the lower layer includes: First Lower Level; and a second lower layer, provided on the first lower layer, The upper layer includes: First upper level; a second upper layer disposed on the first upper layer; and A third upper layer is provided on the second upper layer, and the contact area surrounds at least a portion of the display area.

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