Pixel driving circuit and display device

Abstract

The utility model discloses a pixel driving circuit and a display device, and the pixel driving circuit comprises a driving sub-circuit which is configured to provide a driving signal for a third node under the control of signals of a first node and a second node; the first initial sub-circuit is configured to provide a signal of a first input signal end to a first node under the control of a signal of a first scanning signal end; the coupling sub-circuit is configured to couple a signal of a data signal end or a second input signal end to a third node under the control of a signal of at least one scanning signal end; the holding sub-circuit is configured to store a voltage difference of signals of the first node and the third node; and the light-emitting control sub-circuit is electrically connected with the first light-emitting signal end, the first power supply end and the second node, and is configured to provide the signal of the first power supply end to the second node under the control of the signal of the first light-emitting signal end.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a pixel driving circuit and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a pixel driving circuit and a display device.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving subcircuit, a coupling subcircuit, a holding subcircuit, a first initial subcircuit, and a light emitting control subcircuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node;

[0007] The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal and the first node respectively, and is configured to provide the signal of the first input signal terminal to the first node under the control of the signal of the first scan signal terminal;

[0008] The coupling subcircuit is electrically connected to at least one scan signal terminal, the data signal terminal, the second input signal terminal and the third node, respectively, and is configured to couple the signal of the data signal terminal or the second input signal terminal to the third node under the control of the signal of the at least one scan signal terminal;

[0009] The holding sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store a voltage difference between the signals of the first node and the third node;

[0010] The light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the first power supply terminal and the second node respectively, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signal of the first light-emitting signal terminal.

[0011] In an exemplary embodiment, the at least one scan signal terminal includes: a second scan signal terminal and a third scan signal terminal, and the coupling subcircuit includes: a second transistor, a fourth transistor, and a second capacitor;

[0012] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;

[0013] The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node;

[0014] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the third node.

[0015] In an exemplary embodiment, the at least one scan signal terminal includes: a second scan signal terminal, and the coupling subcircuit includes: a second transistor and a second capacitor;

[0016] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the data signal terminal in part of the time period and is electrically connected to the second input signal terminal in part of the time period, and the second electrode of the second transistor is electrically connected to the fourth node;

[0017] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the third node.

[0018] In an exemplary embodiment, the first initial sub-circuit includes: a first transistor, the holding sub-circuit includes: a first capacitor, and the driving sub-circuit includes: a third transistor;

[0019] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0020] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0021] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

[0022] In an exemplary embodiment, the first initial sub-circuit includes: a first transistor, the holding sub-circuit includes: a first capacitor, the driving sub-circuit includes: a third transistor, and the third transistor includes: a first control electrode and a second control electrode;

[0023] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0024] a first control electrode of the third transistor is electrically connected to the first node, a second control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node;

[0025] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

[0026] In an exemplary embodiment, the pixel driving circuit is configured to drive the light emitting device to emit light, and the light emitting control subcircuit includes: a fifth transistor;

[0027] The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0028] The light emitting device is electrically connected to the third node and the second power supply terminal respectively.

[0029] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device to emit light, the light-emitting control subcircuit is further electrically connected to the second light-emitting signal terminal, the third node, and the fifth node, and the light-emitting control subcircuit includes: a fifth transistor and a sixth transistor;

[0030] The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0031] The control electrode of the sixth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0032] The light emitting device is electrically connected to the fifth node and the second power supply terminal respectively.

[0033] In an exemplary embodiment, further comprising: a second initial subcircuit;

[0034] The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal and the third node respectively, and is configured to provide the signal of the third input signal terminal to the third node under the control of the signal of the fourth scan signal terminal.

[0035] In an exemplary embodiment, the second initial sub-circuit includes: a seventh transistor;

[0036] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node.

[0037] In an exemplary embodiment, further comprising: a second initial subcircuit;

[0038] The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal and the fifth node respectively, and is configured to provide the signal of the third input signal terminal to the fifth node under the control of the signal of the fourth scan signal terminal.

[0039] In an exemplary embodiment, the second initial sub-circuit includes: a seventh transistor;

[0040] The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0041] In an exemplary embodiment, further comprising: a third initial subcircuit;

[0042] The third initial sub-circuit is electrically connected to the fifth scan signal terminal, the fourth input signal terminal and the second node respectively, and is configured to provide the signal of the fourth input signal terminal to the second node under the control of the signal of the fifth scan signal terminal.

[0043] In an exemplary embodiment, the third initial sub-circuit includes: an eighth transistor;

[0044] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth input signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

[0045] In an exemplary embodiment, the signals received by the first input signal terminal and the first power supply terminal connected to the same pixel driving circuit are the same signal.

[0046] In an exemplary embodiment, the signals received by the first signal input terminal and the second signal input terminal connected to the same pixel driving circuit are the same signal.

[0047] In an exemplary embodiment, the second signal input terminal and the third signal input terminal connected to the same pixel driving circuit receive the same signal.

[0048] In an exemplary embodiment, the second signal input terminal and the fourth signal input terminal connected to the same pixel driving circuit receive the same signal.

[0049] In an exemplary embodiment, the signal received by the second scanning signal terminal connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal are the same signal, or the signal received by the second scanning signal terminal connected to the pixel driving circuit in the i-th row and the first scanning signal terminal of the pixel driving circuit in the i-1th row are the same signal.

[0050] In an exemplary embodiment, the fourth scanning signal terminal and the fifth scanning signal terminal connected to the same pixel driving circuit receive the same signal.

[0051] In an exemplary embodiment, the third scan signal terminal connected to the pixel driving circuit in the i-th row and the fourth scan signal terminal of the pixel driving circuit in the (i+K)-th row receive the same signal, where K is a positive integer greater than 1.

[0052] In a second aspect, the present disclosure further provides a display device comprising: the above-mentioned pixel driving circuits arranged in an array.

[0053] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0054] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0056] Figure 1 A schematic structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0057] Figure 2 is the equivalent circuit diagram of the first initial subcircuit;

[0058] Figure 3 To maintain the equivalent circuit diagram of the subcircuit;

[0059] Figure 4 is the equivalent circuit of the driving subcircuit Figure 1 ;

[0060] Figure 5 is the equivalent circuit of the driving subcircuit Figure 2 ;

[0061] Figure 6 is the equivalent circuit of the coupled subcircuit Figure 1 ;

[0062] Figure 7 is the equivalent circuit of the coupled subcircuit Figure 2 ;

[0063] Figure 8 The equivalent circuit of the light emitting control subcircuit Figure 1 ;

[0064] Figure 9 The equivalent circuit of the light emitting control subcircuit Figure 2 ;

[0065] Figure 10 A schematic structural diagram of a pixel driving circuit provided in an exemplary embodiment;

[0066] Figure 11 for Figure 10 An equivalent circuit diagram of the second initial subcircuit in ;

[0067] Figure 12 A schematic structural diagram of a pixel driving circuit provided in another exemplary embodiment;

[0068] Figure 13 for Figure 12 The equivalent circuit of the second initial subcircuit in Figure 1 ;

[0069] Figure 14 for Figure 12 The equivalent circuit of the second initial subcircuit in Figure 2 ;

[0070] Figure 15 A schematic structural diagram of a pixel driving circuit provided in yet another exemplary embodiment;

[0071] Figure 16 is the equivalent circuit diagram of the third initial subcircuit;

[0072] Figure 17 An equivalent circuit of a pixel driving circuit Figure 1 ;

[0073] Figure 18 An equivalent circuit of a pixel driving circuit Figure 2 ;

[0074] Figure 19 for Figure 18The driving timing of the pixel driving circuit provided Figure 1 ;

[0075] Figure 20 for Figure 18 The driving timing of the pixel driving circuit provided Figure 2 ;

[0076] Figure 21 An equivalent circuit of a pixel driving circuit Figure 3 ;

[0077] Figure 22 An equivalent circuit of a pixel driving circuit Figure 4 ;

[0078] Figure 23 for Figure 22 The driving timing of the pixel driving circuit provided Figure 1 ;

[0079] Figure 24 for Figure 22 The driving timing of the pixel driving circuit provided Figure 2 ;

[0080] Figure 25 for Figure 22 The driving timing of the pixel driving circuit provided Figure 3 ;

[0081] Figure 26 for Figure 22 The driving timing of the pixel driving circuit provided Figure 4 ;

[0082] Figure 27 for Figure 22 The driving timing of the pixel driving circuit provided Figure 5 ;

[0083] Figure 28 for Figure 22 The driving timing of the pixel driving circuit provided Figure 6 ;

[0084] Figure 29 for Figure 22 The driving timing of the pixel driving circuit provided Figure 7 ;

[0085] Figure 30 for Figure 22 The driving timing of the pixel driving circuit provided Figure 8 ;

[0086] Figure 31 An equivalent circuit of a pixel driving circuit Figure 5 ;

[0087] Figure 32An equivalent circuit of a pixel driving circuit Figure 6 ;

[0088] Figure 33 An equivalent circuit of a pixel driving circuit Figure 7 ;

[0089] Figure 34 for Figure 32 and Figure 33 The driving timing of the pixel driving circuit provided Figure 1 ;

[0090] Figure 35 for Figure 32 and Figure 33 The driving timing of the pixel driving circuit provided Figure 2 ;

[0091] Figure 36 An equivalent circuit of a pixel driving circuit Figure 8 ;

[0092] Figure 37 An equivalent circuit of a pixel driving circuit Figure 9 ;

[0093] Figure 38 An equivalent circuit of a pixel driving circuit Figure 10 ;

[0094] Figure 39 An equivalent circuit of a pixel driving circuit Figure 10 one;

[0095] Figure 40 An equivalent circuit of a pixel driving circuit Figure 10 two;

[0096] Figure 41 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 1 ;

[0097] Figure 42 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 2 ;

[0098] Figure 43 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 3 ;

[0099] Figure 44 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 4;

[0100] Figure 45 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 5 ;

[0101] Figure 46 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 6 ;

[0102] Figure 47 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 7 ;

[0103] Figure 48 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 8 . DETAILED DESCRIPTION

[0104] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0105] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.

[0106] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0107] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0108] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0109] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0110] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0111] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0112] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0113] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0114] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0115] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0116] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0117] A display product includes at least one sub-pixel, each of which includes a pixel driver circuit and a light-emitting device. The pixel driver circuit can drive the light-emitting device to emit light. The pixel driver circuit includes a driver transistor. The gate electrode of the driver transistor is connected to a large number of transistors, resulting in a large parasitic capacitance coupled to the gate electrode of the driver transistor. This reduces the tracking ratio of the gate and source voltages of the pixel driver circuit, causing the voltage of the drive signal maintained between the gate and source electrodes of the driver transistor to deviate, reducing the consistency of the display brightness of the display product and affecting the display quality of the display substrate.

[0118] To this end, the present disclosure provides a pixel driving circuit.

[0119] Figure 1 This is a schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present disclosure. Figure 1 As shown, the pixel driving circuit provided by the embodiment of the present disclosure may include: a driving subcircuit, a coupling subcircuit, a holding subcircuit, a first initial subcircuit and a light emitting control subcircuit.

[0120] The driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of signals of the first node N1 and the second node N2.

[0121] The first initial sub-circuit is electrically connected to the first input signal terminal IN1, the first scan signal terminal Gate1 and the first node N1, and is configured to provide the signal of the first input signal terminal IN1 to the first node N1 under the control of the signal of the first scan signal terminal Gate1.

[0122] The coupling sub-circuit is electrically connected to at least one scan signal terminal Gate, the data signal terminal Data, the second input signal terminal IN2 and the third node N3, respectively, and is configured to couple the signal of the data signal terminal Data or the second input signal terminal IN2 to the third node N3 under the control of the signal of at least one scan signal terminal Gate.

[0123] The holding sub-circuit is electrically connected to the first node N1 and the third node N3 , respectively, and is configured to store a voltage difference between the signals at the first node N1 and the third node N3 .

[0124] The light control subcircuit is electrically connected to the first light signal terminal EM1, the first power terminal VDD and the second node N2 respectively, and is configured to provide a signal from the first power terminal VDD to the second node N2 under the control of the signal from the first light signal terminal EM1.

[0125] In an exemplary embodiment, the first power supply terminal VDD may continuously provide a high-level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0126] In the present disclosure, the first initial sub-circuit connected to the first node is electrically connected only to the first input signal terminal and the first scan signal terminal, which means that the number of transistors connected to the first node is relatively small, and the setting of the coupling sub-circuit can couple the data of the data signal terminal to the third node connected to the driving sub-circuit, reducing the number of transistors directly coupled to the first node connected to the driving sub-circuit, and can achieve normal data writing and threshold compensation. Therefore, the pixel driving circuit provided in the embodiment of the present disclosure can reduce the parasitic capacitance coupled with the first node N1 while ensuring normal display, so that the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit is not easy to deviate, thereby ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0127] In an exemplary embodiment, the pixel driving circuit is configured to drive the light emitting device L to emit light.

[0128] In an exemplary embodiment, the light emitting device may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light emitting device is electrically connected to the pixel driving circuit, and the cathode of the light emitting device is electrically connected to the second power supply terminal VSS.

[0129] In an exemplary embodiment, the second power supply terminal VSS may continuously provide a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0130] In an exemplary embodiment, the light-emitting device may include a current-driven device, and a current-driven light-emitting diode may be used, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0131] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0132] Figure 2 is the equivalent circuit diagram of the first initial subcircuit. Figure 2 As shown, in an exemplary embodiment, the first initial sub-circuit includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0133] In an exemplary embodiment, the first input signal terminal IN1 may receive a first initial signal. The first transistor T1 may be referred to as a first initial transistor. The first transistor T1 writes the first initial signal into the first node N1 under the control of a signal from the first scan signal terminal Gate1.

[0134] Figure 2 Only an exemplary structure of the first initial sub-circuit is shown in FIG. 3 , and those skilled in the art will readily appreciate that the implementation of the first initial sub-circuit is not limited thereto.

[0135] Figure 3 To maintain the equivalent circuit diagram of the subcircuit. Figure 3 As shown, in an exemplary embodiment, the holding sub-circuit includes: a first capacitor C1 , wherein a first end of the first capacitor C1 is electrically connected to the first node N1 , and a second end of the first capacitor C1 is electrically connected to the third node N3 .

[0136] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal at the first node N1 and improve the reliability of the pixel driving circuit.

[0137] Figure 3 Only an exemplary structure of the holding sub-circuit is shown in FIG. 3 , and it is easily understood by those skilled in the art that the implementation of the holding sub-circuit is not limited thereto.

[0138] Figure 4 is the equivalent circuit of the driving subcircuit Figure 1 .like Figure 4 As shown, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a single-gate transistor. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0139] Figure 5 is the equivalent circuit of the driving subcircuit Figure 2 .like Figure 5As shown, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 may be a dual-gate transistor. The third transistor T3 includes a first control electrode and a second control electrode. The first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0140] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor. The connection method of the third transistor in the present disclosure may improve the output saturation characteristics of the third transistor T3.

[0141] Figure 4 and Figure 5 Two exemplary structures of the driving sub-circuit are shown in FIG. 1 . It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit is not limited thereto.

[0142] Figure 6 is the equivalent circuit of the coupled subcircuit Figure 1 .like Figure 6 As shown, in an exemplary embodiment, at least one scan signal terminal includes: a second scan signal terminal Gate2 and a third scan signal terminal Gate3, and the coupling sub-circuit may include: a second transistor T2, a fourth transistor T4, and a second capacitor C2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0143] In an exemplary embodiment, the second input signal terminal IN2 may receive the second initial signal. The second transistor T2 may be referred to as a second initial transistor. The second transistor T2 writes the second initial signal into the fourth node N4 under the control of the signal of the second scan signal terminal Gate2.

[0144] In an exemplary embodiment, the data signal terminal Data may receive a data signal. The fourth transistor T4 may be referred to as a write transistor. The fourth transistor T4 writes the data signal into the fourth node N4 under the control of the signal of the third scan signal terminal Gate3.

[0145] Figure 7 is the equivalent circuit of the coupled subcircuit Figure 2 .like Figure 7 As shown, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2. The coupling sub-circuit may include a second transistor T2 and a second capacitor C2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data during a portion of the time period and to the second input signal terminal IN2 during a portion of the time period. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0146] In an exemplary embodiment, the second input signal terminal IN2 can receive the second initial signal, and the data signal terminal Data can receive the data signal. Under the control of the signal of the second scan signal terminal Gate2, the second transistor T2 writes the data signal to the fourth node N4 in part of the time period and writes the second initial signal to the fourth node N4 in part of the time period.

[0147] Figure 6 and Figure 7 Two exemplary structures of the coupling sub-circuit are shown in FIG. 1 . It is easy for those skilled in the art to understand that the implementation of the coupling sub-circuit is not limited thereto.

[0148] In an exemplary embodiment, Figure 7 The coupling subcircuit provided is Figure 6 Compared with the coupling sub-circuit provided, the number of transistors included is smaller, which can reduce the area occupied by the pixel driving circuit and the number of connected signal lines, and can achieve a high PPI of the display device.

[0149] Figure 8 The equivalent circuit of the light emitting control subcircuit Figure 1 .like Figure 8 As shown, in an exemplary embodiment, the light emitting control subcircuit may include a fifth transistor T5. A control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0150] In an exemplary embodiment, the first power supply terminal VDD may receive a first power supply signal, and the fifth transistor T5 may be referred to as a light emitting transistor. The fifth transistor T5 writes the first power supply signal into the second node N2 under the control of a signal from the first light emitting signal terminal EM1.

[0151] like Figure 8 As shown, the light emitting device L is electrically connected to the third node N3 and the second power supply terminal VSS, respectively.

[0152] Figure 9 The equivalent circuit of the light emitting control subcircuit Figure 2 .like Figure 9 As shown, in an exemplary embodiment, the light emission control subcircuit is further electrically connected to the second light emission signal terminal EM2, the third node N3, and the fifth node N5. The light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light emission signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light emission signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0153] In an exemplary embodiment, the first power supply terminal VDD may receive a first power supply signal, and the fifth transistor T5 may be referred to as a first light-emitting transistor. Under control of a signal from the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power supply signal to the second node N2. The sixth transistor T6 may be referred to as a second light-emitting transistor. Under control of a signal from the second light-emitting signal terminal EM2, the sixth transistor T6 writes a drive signal output from the third node N3 to the fifth node N5.

[0154] like Figure 9 As shown, the light emitting device L′ is electrically connected to the fifth node N5 and the second power supply terminal VSS, respectively.

[0155] Figure 8 and Figure 9 Two exemplary structures of the light emitting control sub-circuit are shown in FIG. 1 . It is easy for those skilled in the art to understand that the implementation of the light emitting control sub-circuit is not limited thereto.

[0156] In an exemplary embodiment, Figure 9 The provided light emitting control subcircuit isolates the third node N3 from the light emitting device L, thereby preventing the parasitic capacitance of the light emitting device from affecting the signal at the third node N3.

[0157] Figure 10 FIG. 1 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment. Figure 10 As shown, in an exemplary embodiment, when the light-emitting device is electrically connected to the third node N3, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the third node N3, respectively, and is configured to provide the signal of the third input signal terminal IN3 to the third node N3 under the control of the signal of the fourth scan signal terminal Gate4.

[0158] Figure 11 for Figure 10 The equivalent circuit diagram of the second initial subcircuit in . Figure 11 As shown, the second initial sub-circuit may include a seventh transistor T7, a control electrode of which is electrically connected to the fourth scan signal terminal Gate4, a first electrode of which is electrically connected to the third input signal terminal IN3, and a second electrode of which is electrically connected to the third node N3.

[0159] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initialization signal. The seventh transistor T7 can be referred to as a third initialization transistor. Under the control of the signal of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initialization signal to the third node N3 to initialize the third node N3. Exemplarily, the seventh transistor T7 can be turned on once or multiple times during a display frame to initialize the anode of the light-emitting device or bias the third transistor T3.

[0160] Figure 12 FIG. 1 is a schematic structural diagram of a pixel driving circuit provided in another exemplary embodiment. Figure 12 As shown, in an exemplary embodiment, when the light-emitting device is electrically connected to the fifth node N5, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and one of the third node N3 and the fifth node N5, respectively, and is configured to provide the signal of the third input signal terminal IN3 to one of the third node N3 and the fifth node N5 under the control of the signal of the fourth scan signal terminal Gate4.

[0161] Figure 13 for Figure 12 The equivalent circuit of the second initial subcircuit in Figure 1 , Figure 14 for Figure 12 The equivalent circuit of the second initial subcircuit in Figure 2 .like Figure 13 and Figure 14 As shown, in an exemplary embodiment, the second initial sub-circuit includes a seventh transistor T7. A control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and a second electrode of the seventh transistor T7 is electrically connected to one of the third node N3 and the fifth node N5. Figure 13 The following description is made by taking the example that the second electrode of the seventh transistor is electrically connected to the third node N3. Figure 14 The description is made by taking the example that the second electrode of the seventh transistor is electrically connected to the fifth node N5.

[0162] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as a third initialization transistor. Under the control of the signal of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initialization signal to the third node N3 or the fifth node N5, thereby initializing the third node N3 or the fifth node N5. For example, the seventh transistor T7 can be turned on once or multiple times in a display frame, and this disclosure does not impose any limitation on this. When the second electrode of the seventh transistor T7 is electrically connected to the third node N3, turning on the seventh transistor T7 can initialize the second electrode of the third transistor T3 or bias the third transistor T3. When the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5, turning on the seventh transistor T7 can initialize the anode of the light-emitting device.

[0163] Figure 11 、 Figure 13 and Figure 14 An exemplary structure of the second initial sub-circuit is shown in FIG. , and those skilled in the art will readily appreciate that the implementation of the second initial sub-circuit is not limited thereto.

[0164] Figure 15 FIG. 1 is a structural diagram of a pixel driving circuit provided in another exemplary embodiment. Figure 15 As shown, in an exemplary embodiment, the pixel driving circuit may further include a third initial sub-circuit. The third initial sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the second node N2, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the second node N2 under the control of the signal of the fifth scan signal terminal Gate5.

[0165] Figure 16 is the equivalent circuit diagram of the third initial subcircuit. Figure 16 As shown, in an exemplary embodiment, the third initial sub-circuit includes an eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first electrode of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0166] In an exemplary embodiment, the fourth input signal terminal IN4 can receive a fourth initial signal. The eighth transistor T8 can be referred to as a fourth initial transistor. The eighth transistor T8 writes the fourth initial signal into the second node N2 under the control of the signal of the fifth scan signal terminal Gate5 to initialize or bias the second node N2.

[0167] The arrangement of the second initial sub-circuit and the third initial sub-circuit in the present disclosure can initialize the second node before the light-emitting device emits light, thereby ensuring the consistency of the light-emitting brightness in the display device.

[0168] Figure 16 An exemplary structure of the third initial sub-circuit is shown in FIG. , and those skilled in the art will readily appreciate that the implementation of the third initial sub-circuit is not limited thereto.

[0169] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the first power supply terminal VDD connected to the same pixel driving circuit may be the same signal.

[0170] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the second input signal terminal IN2 connected to the same pixel driving circuit may be the same signal.

[0171] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the third input signal terminal IN3 connected to the same pixel driving circuit may be the same signal.

[0172] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the fourth input signal terminal IN4 connected to the same pixel driving circuit may be the same signal.

[0173] In an exemplary embodiment, the voltage value of the third initial signal received by the third input signal terminal IN3 is less than the sum of the voltage value of the signal at the second power supply terminal and the voltage value between the two electrodes of the light-emitting device, so as to ensure that the light-emitting device does not emit light when the anode of the light-emitting device L is initialized.

[0174] In an exemplary embodiment, the first initial signal received by the first input signal terminal IN1 is a positive voltage signal, so as to ensure that the third transistor T3 can be normally turned on, thereby improving the reliability of the pixel driving circuit.

[0175] In an exemplary embodiment, the voltage value of the first initial signal received by the first input signal terminal IN1 may be equal to the voltage value of the second initial signal received by the second input signal terminal IN2, the voltage value of the first initial signal received by the first input signal terminal IN1 may be greater than the voltage value of the third initial signal received by the third input signal terminal IN3, and the voltage value of the third initial signal received by the third input signal terminal IN3 may be greater than the voltage value of the fourth initial signal received by the fourth input signal terminal IN4.

[0176] In an exemplary embodiment, the signal received by the second scanning signal terminal Gate2 connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal EM1 are the same signal, or the signal received by the second scanning signal terminal Gate2 connected to the pixel driving circuit in the i-th row and the first scanning signal terminal Gate1 of the pixel driving circuit in the i-1th row are the same signal.

[0177] In an exemplary embodiment, when the pixel driving circuit is electrically connected to the fourth scan signal terminal and the fifth scan signal terminal respectively, the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 connected to the same pixel driving circuit receive the same signal.

[0178] In an exemplary embodiment, the third scan signal terminal Gate3 connected to the pixel driving circuit in the i-th row and the fourth scan signal terminal Gate4 connected to the pixel driving circuit in the (i+K)-th row receive the same signal, where K is a positive integer greater than 1.

[0179] In an exemplary embodiment, the signals received by at least two signal terminals connected to the pixel driving circuit are the same signal, which can reduce the number of signal lines connected to the pixel driving circuit and achieve a high PPI of the display device.

[0180] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0181] In an exemplary embodiment, the N-type transistor may be an oxide thin film transistor. The active pattern of the oxide thin film transistor is made of an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0182] In an exemplary embodiment, any capacitor among the first capacitor C1 to the second capacitor C2 can be a capacitor device made by a process. For example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the second capacitor C2 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the second capacitor C2 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0183] Figure 17 An equivalent circuit of a pixel driving circuit Figure 1 .like Figure 17 As shown, the pixel driving circuit includes: a driving subcircuit, a holding subcircuit, a coupling subcircuit and a light-emitting control subcircuit, wherein the first initial subcircuit includes: a first transistor T1, the holding subcircuit includes: a first capacitor C1, the coupling subcircuit includes: a second transistor T2 and a second capacitor C2, the driving subcircuit includes: a third transistor T3, and the light-emitting control subcircuit includes: a fifth transistor T5. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data during a partial time period and to the second input signal terminal IN2 during a partial time period, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or A first control electrode of the third transistor T3 is electrically connected to the first node N1, a second control electrode of the third transistor T3 is electrically connected to the third node N3, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3; a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the third node N3.

[0184] In an exemplary embodiment, Figure 17 At least one of the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0185] Figure 18 An equivalent circuit of a pixel driving circuit Figure 2 .like Figure 18 As shown, the pixel driving circuit includes: a driving subcircuit, a holding subcircuit, a coupling subcircuit, a light emitting control subcircuit, and at least one of a second initial subcircuit and a third initial subcircuit. Figure 18The following description uses an example in which a pixel driving circuit includes a second initial subcircuit and a third initial subcircuit. The first initial subcircuit includes a first transistor T1, a holding subcircuit includes a first capacitor C1, a coupling subcircuit includes a second transistor T2 and a second capacitor C2, a driving subcircuit includes a third transistor T3, a light emitting control subcircuit includes a fifth transistor T5, the second initial subcircuit includes a seventh transistor T7, and the third initial subcircuit includes an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in a partial time period, and is electrically connected to the second input signal terminal IN2 in a partial time period, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the third transistor A second electrode of T3 is electrically connected to the third node N3; a control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and a second electrode of the seventh transistor T7 is electrically connected to the third node N3; a control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3; a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the third node N3.

[0186] In an exemplary embodiment, Figure 18At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0187] Figure 18 The seventh transistor T7 in the circuit initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figure 18 The working process of the first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5 is the same as that of the first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5. Figure 17 The first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5 have the same working process. Figure 18 The working process of the pixel driving circuit provided, Figure 17 The working process of the provided pixel driving circuit will not be described in detail here.

[0188] Figure 19 for Figure 18 The driving timing of the pixel driving circuit provided Figure 1 . Figure 19 Therefore Figure 18 All transistors in the example are N-type transistors. Figure 19 As shown, Figure 18 The working process of the provided pixel driving circuit may include:

[0189] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signal at the first light-emitting signal terminal EM1 is low-level. During this stage, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fifth transistor T5 is turned off.

[0190] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2, where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0191] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, and the signals at the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 are low-level signals. In this stage, the first electrode of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the seventh transistor T7 and the eighth transistor T8 are turned off.

[0192] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0193] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V dataThe fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V data -V IN1 +Vth.

[0194] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first emitting signal terminal EM1, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. During this phase, the first electrode of the second transistor T2 is electrically connected to the other of the second input signal terminal IN2 and the data signal terminal Data. The first and second transistors T1 and T2 are turned on, while the fifth, seventh, and eighth transistors T5, T7, and T8 are turned off.

[0195] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0196] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value V1 of the signal at the first node N1 is V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0197] In the fourth phase S4, the light-emitting phase, the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. During this phase, the signal written to the first electrode of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0198] The fifth transistor T5 is turned on so that the power voltage outputted from the first power terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0199] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1.

[0200] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage and the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0201] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0202] I=K*(Vgs-Vth) 2

[0203] =K*(V1-V3-Vth)2

[0204] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0205] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0206] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the second phase and the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third phase, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0207] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0208] I=K*(Vgs-Vth) 2

[0209] =K*(V1-V3-Vth) 2

[0210] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0211] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0212] Figure 20 for Figure 18 The driving timing of the pixel driving circuit provided Figure 2 . Figure 20 Therefore Figure 18 All transistors in the example are N-type transistors. Figure 20 As shown, Figure 18 The working process of the provided pixel driving circuit may include:

[0213] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1 and the fifth scanning signal terminal Gate5 are low-level signals. During this stage, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off.

[0214] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3.

[0215] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, and the signals at the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 are low-level signals. In this stage, the first electrode of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the seventh transistor T7 and the eighth transistor T8 are turned off.

[0216] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1-Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0217] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V data -V IN1 +Vth.

[0218] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first emitting signal terminal EM1, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. During this phase, the first electrode of the second transistor T2 is electrically connected to the other of the second input signal terminal IN2 and the data signal terminal Data. The first and second transistors T1 and T2 are turned on, while the fifth, seventh, and eighth transistors T5, T7, and T8 are turned off.

[0219] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2)(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0220] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value V1 of the signal at the first node N1 is V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0221] In the fourth phase S4, the bias phase, the signal at the fifth scanning signal terminal Gate5 is a high-level signal, while the signals at the first emission signal terminal EM1, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the fourth scanning signal terminal Gate4 are low-level signals. During this phase, the first electrode of the second transistor T2 is electrically connected to the other of the second input signal terminal IN2 and the data signal terminal Data. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0222] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0223] In the fifth stage S5, the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. During this stage, the signal written to the first electrode of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0224] The fifth transistor T5 is turned on so that the power voltage outputted from the first power terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0225] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1.

[0226] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage and the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0227] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0228] I=K*(Vgs-Vth) 2

[0229] =K*(V1-V3-Vth) 2

[0230] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0231] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0232] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the second phase and the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third phase, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data(C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0233] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0234] I=K*(Vgs-Vth) 2

[0235] =K*(V1-V3-Vth) 2

[0236] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0237] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0238] Figure 20 The working process of the pixel driving circuit provided is similar to Figure 19 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0239] Figure 21 An equivalent circuit of a pixel driving circuit Figure 3 .like Figure 21As shown, the pixel driving circuit includes: a first initial subcircuit, a driving subcircuit, a holding subcircuit, a coupling subcircuit, and a light-emitting control subcircuit. The first initial subcircuit includes: a first transistor T1; the holding subcircuit includes: a first capacitor C1; the coupling subcircuit includes: a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving subcircuit includes: a third transistor T3; and the light-emitting control subcircuit includes: a fifth transistor T5. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, and the control electrode of the third transistor T3 is electrically connected to the first node N1. The first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0240] In an exemplary embodiment, Figure 21 At least one of the first to fifth transistors T1 to T5 is an N-type transistor. Exemplarily, the first to fifth transistors T1 to T5 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0241] Figure 22 An equivalent circuit of a pixel driving circuit Figure 4 .like Figure 22As shown, the pixel driving circuit includes: a first initial subcircuit, a driving subcircuit, a holding subcircuit, a coupling subcircuit, a light emitting control subcircuit, and at least one of a second initial subcircuit and a third initial subcircuit. Figure 22 The following description uses an example in which a pixel driving circuit includes a second initial subcircuit and a third initial subcircuit. The first initial subcircuit includes a first transistor T1, a holding subcircuit includes a first capacitor C1, a coupling subcircuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2, a driving subcircuit includes a third transistor T3, a light-emitting control subcircuit includes a fifth transistor T5, the second initial subcircuit includes a seventh transistor T7, and the third initial subcircuit includes an eighth transistor T8. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, and the fourth transistor A first electrode of T4 is electrically connected to the data signal terminal Data, and a second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; a control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and a second electrode of the seventh transistor T7 is electrically connected to the third node N3; a control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3; a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the third node N3.

[0242] In an exemplary embodiment, Figure 22At least one of the first to fifth transistors T1 to T5, the seventh transistor T7, and the eighth transistor T8 is an N-type transistor. Exemplarily, the first to fifth transistors T1 to T5, the seventh transistor T7, and the eighth transistor T are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0243] Figure 22 The seventh transistor T7 in the circuit initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figure 22 The working process of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 is the same as that of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5. Figure 21 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 have the same working process. Figure 22 The working process of the pixel driving circuit provided, Figure 21 The working process of the provided pixel driving circuit will not be described in detail here.

[0244] Figure 23 for Figure 22 The driving timing of the pixel driving circuit provided Figure 1 . Figure 23 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 23 The following example illustrates that the signal received by the second scanning signal terminal connected to the pixel driving circuit of the i-th row and the first scanning signal terminal connected to the pixel driving circuit of the i-1th row are the same signal, and the signal received by the fifth scanning signal terminal Gate5 and the fourth scanning signal terminal Gate4 are the same signal. Figure 23 As shown, Figure 22 The working process of the provided pixel driving circuit may include:

[0245] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first light-emitting signal terminal EM1 and the third scanning signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fifth transistor T5 is turned off.

[0246] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where VIN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0247] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first emission signal terminal EM1 are high-level signals, while the signals at the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0248] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0249] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0250] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0251] In the fourth stage S4, the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0252] The fifth transistor T5 is turned on so that the power voltage outputted from the first power terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0253] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(Vdata -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0254] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0255] I=K*(Vgs-Vth) 2

[0256] =K*(V1-V3-Vth) 2

[0257] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0258] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0259] Figure 24 for Figure 22 The driving timing of the pixel driving circuit provided Figure 2 . Figure 24 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 24 The following example illustrates that the second scanning signal terminal connected to the pixel driving circuit of the i-th row and the first scanning signal terminal connected to the pixel driving circuit of the i-1-th row receive the same signal, and the time when the fifth scanning signal terminal Gate5 receives the effective level signal is later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal. Figure 24 As shown, Figure 22 The working process of the provided pixel driving circuit may include:

[0260] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1, the third scanning signal terminal Gate3, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, and the fifth transistor T5 is turned off.

[0261] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where VIN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3.

[0262] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first emission signal terminal EM1 are high-level signals, while the signals at the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0263] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0264] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0265] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0266] In the fourth phase S4, the bias phase, the signal at the fifth scanning signal terminal Gate5 is a high-level signal, and the signals at the first emission signal terminal EM1, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fourth scanning signal terminal Gate4 are low-level signals. The eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0267] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0268] In the fifth stage S5, the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0269] The fifth transistor T5 is turned on so that the power voltage outputted from the first power terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0270] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + VOLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0271] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0272] I=K*(Vgs-Vth) 2

[0273] =K*(V1-V3-Vth) 2

[0274] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0275] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0276] Figure 24 The working process of the pixel driving circuit provided is similar to Figure 23 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0277] Figure 25 for Figure 22 The driving timing of the pixel driving circuit provided Figure 3 . Figure 25 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 25 The following example illustrates that the second scanning signal terminal and the first light emitting signal terminal connected to the same pixel driving circuit receive the same signal, and the fifth scanning signal terminal Gate5 and the fourth scanning signal terminal Gate4 receive the same signal. Figure 25 As shown, Figure 22 The working process of the provided pixel driving circuit may include:

[0278] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second scanning signal terminal Gate2, and the third scanning signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0279] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0280] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first emission signal terminal EM1 are high-level signals, while the signals at the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0281] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0282] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0283] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0284] In the fourth phase S4, the light-emitting phase, the signals at the first light-emitting signal terminal EM1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0285] The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 , where V IN2 The fifth transistor T5 is turned on so that the power supply voltage output from the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0286] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0287] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0288] I=K*(Vgs-Vth) 2

[0289] =K*(V1-V3-Vth) 2

[0290] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0291] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0292] Figure 26 for Figure 22 The driving timing of the pixel driving circuit provided Figure 4 . Figure 26 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 26 The second scanning signal terminal and the first light emitting signal terminal connected to the same pixel driving circuit receive the same signal, and the time when the fifth scanning signal terminal Gate5 receives the effective level signal is later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal is used as an example for explanation. Figure 26 As shown, Figure 22 The working process of the provided pixel driving circuit may include:

[0293] In the first phase S1, the initialization phase, the signals at the first scanning signal terminal Gate1 and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0294] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0295] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first emission signal terminal EM1 are high-level signals, while the signals at the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0296] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0297] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0298] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0299] In the fourth phase S4, the bias phase, the signal at the fifth scanning signal terminal Gate5 is a high-level signal, and the signals at the first emission signal terminal EM1, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fourth scanning signal terminal Gate4 are low-level signals. The eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0300] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0301] In the fifth stage S5, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0302] The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 , where V IN2 The fifth transistor T5 is turned on so that the power supply voltage output from the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0303] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0304] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0305] I=K*(Vgs-Vth) 2

[0306] =K*(V1-V3-Vth) 2

[0307] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0308] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0309] Figure 26 The working process of the pixel driving circuit provided is similar to Figure 25Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0310] Figure 27 for Figure 22 The driving timing of the pixel driving circuit provided Figure 5 . Figure 27 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 27 The fifth scanning signal terminal Gate5 and the fourth scanning signal terminal Gate4 receive the same signal for explanation. Figure 27 As shown, Figure 22 The working process of the provided pixel driving circuit may include:

[0311] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second scanning signal terminal Gate2, and the third scanning signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0312] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0313] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, and the first emission signal terminal EM1 are high-level signals, and the signals at the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0314] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0315] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0316] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data)(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0317] In the fourth stage S4, the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0318] The fifth transistor T5 is turned on so that the power voltage outputted from the first power terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0319] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0320] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0321] I=K*(Vgs-Vth) 2

[0322] =K*(V1-V3-Vth) 2

[0323] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0324] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0325] Figure 28 for Figure 22 The driving timing of the pixel driving circuit provided Figure 6 . Figure 28 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 28 The explanation is based on the fact that the time when the fifth scanning signal terminal Gate5 receives the effective level signal is later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal. Figure 28 As shown, Figure 22 The working process of the provided pixel driving circuit may include:

[0326] In the first phase S1, the initialization phase, the signals at the first scanning signal terminal Gate1 and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0327] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3.

[0328] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, and the first emission signal terminal EM1 are high-level signals, and the signals at the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0329] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V dataThe fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0330] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0331] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0332] In the fourth phase S4, the bias phase, the signal at the fifth scanning signal terminal Gate5 is a high-level signal, and the signals at the first emission signal terminal EM1, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fourth scanning signal terminal Gate4 are low-level signals. The eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0333] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2is the voltage value of the signal at the second input signal terminal IN3.

[0334] In the fifth stage S5, the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0335] The fifth transistor T5 is turned on so that the power voltage outputted from the first power terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light emitting device L to emit light.

[0336] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0337] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0338] I=K*(Vgs-Vth) 2

[0339] =K*(V1-V3-Vth) 2

[0340] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0341] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0342] Figure 28The working process of the pixel driving circuit provided is similar to Figure 27 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0343] Figure 29 for Figure 22 The driving timing of the pixel driving circuit provided Figure 7 . Figure 29 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 29 The driving timing provided is Figure 23 Compared with the driving timing provided, the only difference is that the duration of the signal of the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 being the effective level signal is different, but the signals of the multiple signal terminals connected to the pixel driving circuit at different stages are the same. Therefore, Figure 29 The working process of the pixel driving circuit provided is similar to Figure 23 The working process of the provided pixel driving circuit is exactly the same, and will not be described in detail herein.

[0344] Figure 30 for Figure 22 The driving timing of the pixel driving circuit provided Figure 8 . Figure 30 Therefore Figure 22 All transistors in the figure are N-type transistors. Figure 30 The driving timing provided is Figure 24 Compared with the driving timing provided, the only difference is that the duration of the signal of the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 being the effective level signal is different, but the signals of the multiple signal terminals connected to the pixel driving circuit at different stages are the same. Therefore, Figure 30 The working process of the pixel driving circuit provided is similar to Figure 24 The working process of the provided pixel driving circuit is exactly the same, and will not be described in detail herein.

[0345] Figure 31 An equivalent circuit of a pixel driving circuit Figure 5 .like Figure 31As shown, the pixel driving circuit includes: a first initial subcircuit, a driving subcircuit, a holding subcircuit, a coupling subcircuit and a light-emitting control subcircuit, wherein the first initial subcircuit includes: a first transistor T1, the holding subcircuit includes: a first capacitor C1, the coupling subcircuit includes: a second transistor T2 and a second capacitor C2, the driving subcircuit includes: a third transistor T3, and the light-emitting control subcircuit includes: a fifth transistor T5 and a sixth transistor T6. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in a partial time period, and is electrically connected to the second input signal terminal IN2 in a partial time period, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0346] In an exemplary embodiment, Figure 31 At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0347] Figure 32 An equivalent circuit of a pixel driving circuit Figure 6 , Figure 33 An equivalent circuit of a pixel driving circuit Figure 7 .like Figure 32 and Figure 33 As shown, the pixel driving circuit includes: a first initial subcircuit, a driving subcircuit, a holding subcircuit, a coupling subcircuit, a light emitting control subcircuit, and at least one of a second initial subcircuit and a third initial subcircuit. Figure 32 and Figure 33The following description uses an example in which a pixel driving circuit includes a second initial subcircuit and a third initial subcircuit. The first initial subcircuit includes a first transistor T1, a holding subcircuit includes a first capacitor C1, a coupling subcircuit includes a second transistor T2 and a second capacitor C2, a driving subcircuit includes a third transistor T3, a light emitting control subcircuit includes a fifth transistor T5 and a sixth transistor T6, the second initial subcircuit includes a seventh transistor T7, and the third initial subcircuit includes an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in a partial time period, and is electrically connected to the second input signal terminal IN2 in a partial time period, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1 A first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; a control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and a second electrode of the seventh transistor T7 is electrically connected to one of the third node N3 and the fifth node N5; a control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3; a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the third node N3. Figure 32 The following description is made by taking the case where the second electrode of the seventh transistor is electrically connected to the third node as an example. Figure 33 The description is made by taking the example that the second electrode of the seventh transistor is electrically connected to the fifth node.

[0348] In an exemplary embodiment, Figure 32 and Figure 33 At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0349] Figure 32 and Figure 33 The seventh transistor T7 in the circuit initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figure 27 and Figure 28 The working process of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 is the same as that of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5 and the sixth transistor T6. Figure 26 The first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 in the embodiment have the same working process. Figure 27 and Figure 28 The working process of the pixel driving circuit provided, Figure 26 The working process of the provided pixel driving circuit will not be described in detail here.

[0350] Figure 34 for Figure 32 and Figure 33 The driving timing of the pixel driving circuit provided Figure 1 . Figure 34 Therefore Figure 32 and Figure 33 All transistors in the figure are N-type transistors. Figure 34 The following description is made by taking the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 as an example, where the signals received are the same signal. Figure 34 As shown, Figure 32 and Figure 33 The working process of the provided pixel driving circuit may include:

[0351] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 and the sixth transistor T6 are turned off.

[0352] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0353] In the second stage S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, and the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. In this stage, the first electrode of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0354] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0355] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V data -V IN1 +Vth.

[0356] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. During this phase, the first electrode of the second transistor T2 is electrically connected to the other of the second input signal terminal IN2 and the data signal terminal Data. The first and second transistors T1 and T2 are turned on, while the fifth, sixth, seventh, and eighth transistors T5, T6, T7, and T8 are turned off.

[0357] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=Vdata The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0358] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value V1 of the signal at the first node N1 is V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0359] In the fourth phase S4, the light-emitting phase, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this phase, the signal written to the first electrode of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0360] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0361] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + VOLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1.

[0362] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage and the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0363] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0364] I=K*(Vgs-Vth) 2

[0365] =K*(V1-V3-Vth) 2

[0366] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0367] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0368] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the second phase and the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third phase, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0369] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0370] I=K*(Vgs-Vth)2

[0371] =K*(V1-V3-Vth) 2

[0372] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0373] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0374] Figure 35 for Figure 32 and Figure 33 The driving timing of the pixel driving circuit provided Figure 2 . Figure 35 Therefore Figure 32 and Figure 33 All transistors in the figure are N-type transistors. Figure 35 The following is an example of the time when the fifth scanning signal terminal Gate5 receives the effective level signal later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal. Figure 35 As shown, Figure 32 and Figure 33 The working process of the provided pixel driving circuit may include:

[0375] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the fifth scanning signal terminal Gate5 are low-level signals. During this stage, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0376] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3.

[0377] In the second stage S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, and the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. In this stage, the first electrode of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0378] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0379] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = VIN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V data -V IN1 +Vth.

[0380] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. During this phase, the first electrode of the second transistor T2 is electrically connected to the other of the second input signal terminal IN2 and the data signal terminal Data. The first and second transistors T1 and T2 are turned on, while the fifth, sixth, seventh, and eighth transistors T5, T6, T7, and T8 are turned off.

[0381] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0382] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value V1 of the signal at the first node N1 is V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -Vdata )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0383] In the fourth stage, the bias stage, the signal of the fifth scanning signal terminal Gate5 is a high-level signal, the signals of the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are low-level signals, the eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0384] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0385] In the fifth stage S5, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first electrode of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0386] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0387] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1.

[0388] When the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage and the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1-Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0389] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0390] I=K*(Vgs-Vth) 2

[0391] =K*(V1-V3-Vth) 2

[0392] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0393] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0394] When the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data in the second phase and the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third phase, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0395] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0396] I=K*(Vgs-Vth) 2

[0397] =K*(V1-V3-Vth) 2

[0398] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0399] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0400] Figure 36 An equivalent circuit of a pixel driving circuit Figure 8 .like Figure 36 As shown, the pixel driving circuit includes: a first initial subcircuit, a driving subcircuit, a holding subcircuit, a coupling subcircuit, and a light-emitting control subcircuit. The first initial subcircuit includes: a first transistor T1; the holding subcircuit includes: a first capacitor C1; the coupling subcircuit includes: a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving subcircuit includes: a third transistor T3; and the light-emitting control subcircuit includes: a fifth transistor T5 and a sixth transistor T6. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The node N3 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0401] In an exemplary embodiment, Figure 36At least one of the first to sixth transistors T1 to T6 is an N-type transistor. Exemplarily, the first to sixth transistors T1 to T6 are all N-type transistors, or the first transistor T1 and the first to fourth transistors T1 to T4 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0402] Figure 37 An equivalent circuit of a pixel driving circuit Figure 9 , Figure 38 An equivalent circuit of a pixel driving circuit Figure 10 , Figure 39 An equivalent circuit of a pixel driving circuit Figure 10 one, Figure 40 An equivalent circuit of a pixel driving circuit Figure 10 2. As Figures 37 to 40 As shown, the pixel driving circuit includes: a first initial subcircuit, a driving subcircuit, a holding subcircuit, a coupling subcircuit, a light emitting control subcircuit, and at least one of a second initial subcircuit and a third initial subcircuit. Figure 37 and Figure 38 The description is made by taking the pixel driving circuit including the second initial sub-circuit as an example. Figure 39 and Figure 40The following description uses an example in which a pixel driving circuit includes a second initial subcircuit and a third initial subcircuit. The first initial subcircuit includes a first transistor T1, a holding subcircuit includes a first capacitor C1, a coupling subcircuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2, a driving subcircuit includes a third transistor T3, a light emitting control subcircuit includes a fifth transistor T5 and a sixth transistor T6, the second initial subcircuit includes a seventh transistor T7, and the third initial subcircuit includes an eighth transistor T8. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, the second electrode of the first transistor T1 is electrically connected to the first node N1, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4 The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, and the first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN 3, a second electrode of the seventh transistor T7 is electrically connected to the third node N3 or the fifth node N5; a control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3; a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the third node N3. Figure 37 and Figure 39The following description is made by taking the example that the second electrode of the seventh transistor T7 is electrically connected to the third node N3. Figure 38 and Figure 40 The description is made by taking the example that the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0403] In an exemplary embodiment, Figure 39 and Figure 40 At least one of the first to eighth transistors T1 to T8 is an N-type transistor. Exemplarily, the first to eighth transistors T1 to T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0404] Figures 37 to 40 The seventh transistor T7 in the circuit initializes the third node N3, and the eighth transistor T8 resets the second node N2. Figures 37 to 40 The working process of the first transistor T1 to the sixth transistor T6 is the same as Figure 36 The first transistor T1 to the sixth transistor T6 have the same working process. Figure 39 and Figure 37 Compared to the above, only the eighth transistor T8 is added. Figure 39 The working process of the first transistor T1 to the seventh transistor T7 is the same as Figure 37 The first transistor T1 to the seventh transistor T7 have the same working process. Figure 40 and Figure 38 Compared to the above, only the eighth transistor T8 is added. Figure 40 The working process of the first transistor T1 to the seventh transistor T7 is the same as Figure 38 The first transistor T1 to the seventh transistor T7 have the same working process.

[0405] This disclosure only provides Figure 39 and Figure 40 The working process of the pixel driving circuit provided, Figure 36 、 Figure 37 and Figure 39 The working process of the provided pixel driving circuit will not be described in detail here.

[0406] Figure 41 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 1 . Figure 41 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 41The following example illustrates that the second scanning signal terminal connected to the pixel driving circuit of the i-th row and the first scanning signal terminal connected to the pixel driving circuit of the i-1-th row receive the same signal, and the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 receive the same signal. Figure 41 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0407] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the third scanning signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fifth transistor T5 and the sixth transistor T6 are turned off.

[0408] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0409] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0410] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0411] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0412] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0413] In the fourth stage S4, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0414] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0415] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0416] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0417] I=K*(Vgs-Vth) 2

[0418] =K*(V1-V3-Vth) 2

[0419] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0420] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0421] Figure 42 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 2 . Figure 42 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 42 The following example illustrates that the second scanning signal terminal connected to the pixel driving circuit of the i-th row and the first scanning signal terminal connected to the pixel driving circuit of the i-1-th row receive the same signal, and the time when the fifth scanning signal terminal Gate5 receives the effective level signal is later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal. Figure 42 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0422] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the third scanning signal terminal Gate3, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0423] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3.

[0424] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0425] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0426] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0427] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2)(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0428] In the fourth stage, the bias stage, the signal of the fifth scan signal terminal Gate5 is a high-level signal, the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are low-level signals, the eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0429] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0430] In the fifth stage S5, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0431] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0432] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -VIN2 )(C2 / C1+C2)

[0433] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0434] I=K*(Vgs-Vth) 2

[0435] =K*(V1-V3-Vth) 2

[0436] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0437] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0438] Figure 42 The working process of the pixel driving circuit provided is similar to Figure 42 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0439] Figure 43 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 3 . Figure 43 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 43 The second scanning signal terminal and the first light emitting signal terminal connected to the same pixel driving circuit receive the same signal, and the fifth scanning signal terminal Gate5 and the fourth scanning signal terminal Gate4 receive the same signal. Figure 43 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0440] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, and the third scanning signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0441] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0442] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0443] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1-Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0444] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0445] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0446] In the fourth stage S4, the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0447] The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 , where V IN2The fifth transistor T5 and the sixth transistor T6 are turned on, so that the power supply voltage output from the first power supply terminal VDD provides a driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0448] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0449] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0450] I=K*(Vgs-Vth) 2

[0451] =K*(V1-V3-Vth) 2

[0452] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0453] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0454] Figure 44 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 4 . Figure 44 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 44The second scanning signal terminal and the first light emitting signal terminal connected to the same pixel driving circuit receive the same signal, and the time when the fifth scanning signal terminal Gate5 receives the effective level signal is later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal is used as an example for explanation. Figure 44 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0455] In the first phase S1, the initialization phase, the signals at the first scanning signal terminal Gate1 and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0456] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0457] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0458] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0459] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0460] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0461] In the fourth phase S4, the bias phase, the signal at the fifth scanning signal terminal Gate5 is a high-level signal, and the signals at the first emission signal terminal EM1, the second emission signal terminal EM2, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fourth scanning signal terminal Gate4 are low-level signals. The eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0462] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0463] In the fifth stage S5, the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0464] The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 , where V IN2 The fifth transistor T5 and the sixth transistor T6 are turned on, so that the power supply voltage output from the first power supply terminal VDD provides a driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0465] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0466] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0467] I=K*(Vgs-Vth) 2

[0468] =K*(V1-V3-Vth) 2

[0469] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0470] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0471] Figure 44 The working process of the pixel driving circuit provided is similar to Figure 43 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0472] Figure 45 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 5 . Figure 45 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 45 The fifth scanning signal terminal Gate5 and the fourth scanning signal terminal Gate4 receive the same signal for illustration. Figure 45 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0473] In the first stage S1, the initialization stage, the signals at the first scanning signal terminal Gate1, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, and the third scanning signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0474] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0475] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0476] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0477] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0478] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0479] In the fourth stage S4, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0480] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0481] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0482] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0483] I=K*(Vgs-Vth) 2

[0484] =K*(V1-V3-Vth) 2

[0485] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0486] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0487] Figure 46 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 6 . Figure 46 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 46 The explanation is based on the fact that the time when the fifth scanning signal terminal Gate5 receives the effective level signal is later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal. Figure 46 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0488] In the first phase S1, the initialization phase, the signals at the first scanning signal terminal Gate1 and the fourth scanning signal terminal Gate4 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0489] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is VIN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3.

[0490] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0491] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0492] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are high-level signals, and the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0493] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The voltage value of the signal at the fourth node N4 is V data Jump to V IN2Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V IN2 -V data )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0494] In the fourth phase S4, the bias phase, the signal at the fifth scanning signal terminal Gate5 is a high-level signal, and the signals at the first emission signal terminal EM1, the second emission signal terminal EM2, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fourth scanning signal terminal Gate4 are low-level signals. The eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0495] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0496] In the fifth stage S5, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0497] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0498] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1-Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data )(C2 / C1+C2)

[0499] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0500] I=K*(Vgs-Vth) 2

[0501] =K*(V1-V3-Vth) 2

[0502] =K*[(V data -V IN2 )(C2 / C1+C2)] 2

[0503] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0504] Figure 46 The working process of the pixel driving circuit provided is similar to Figure 45 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0505] Figure 47 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 7 . Figure 47 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 47 The description is made by taking the fifth scanning signal terminal Gate5 and the fourth scanning signal terminal Gate4 receiving the same signal as an example. Figure 47 The driving timing provided is Figure 41 Compared with the driving timing provided, the difference is that the duration of the signals of the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 being valid level signals is different, and the duration of the signal of the second scanning signal terminal Gate2 being a valid level signal is longer than the duration of the signal of the first scanning signal terminal Gate1 being a valid level signal.

[0506] like Figure 47 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0507] In the first stage S1, the initialization stage, the signals at the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light-emitting signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fourth transistor T4 and the fifth transistor T5 are turned off.

[0508] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal of the second node N2 is V2=V IN2 , where V IN2 The sixth transistor T6 is turned on, and the signal at the fifth node N5 is connected to the signal at the third node N3.

[0509] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0510] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0511] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0512] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(V data -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0513] In the fourth stage S4, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0514] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0515] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 )(C2 / C1+C2)

[0516] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0517] I=K*(Vgs-Vth) 2

[0518] =K*(V1-V3-Vth) 2

[0519] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0520] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0521] Figure 48 for Figure 39 and Figure 40 The driving timing of the pixel driving circuit provided Figure 8 . Figure 48 Therefore Figure 39 and Figure 40 All transistors in the figure are N-type transistors. Figure 48 The description is made by taking the time when the fifth scanning signal terminal Gate5 receives the effective level signal later than the time when the fourth scanning signal terminal Gate4 receives the effective level signal as an example. Figure 48 The driving timing provided is Figure 42 Compared with the driving timing provided, the difference is that the duration of the signals of the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 being valid level signals is different, and the duration of the signal of the second scanning signal terminal Gate2 being a valid level signal is longer than the duration of the signal of the first scanning signal terminal Gate1 being a valid level signal.

[0522] like Figure 48 As shown, Figure 39 and Figure 40 The working process of the provided pixel driving circuit may include:

[0523] In the first stage S1, the initialization stage, the signals at the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, while the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0524] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 , where V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The seventh transistor T7 is turned on, and the signal of the third input signal terminal IN3 is written into one of the third node N3 and the fifth node N5. The voltage value of the signal of one of the third node N3 and the fifth node N5 is V IN3 , where V IN3 is the voltage value of the signal at the third input signal terminal IN3. The sixth transistor T6 is turned on, and the signal at the fifth node N5 is connected to the signal at the third node N3.

[0525] In the second stage S2, the threshold compensation stage, the signals at the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0526] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The second transistor T2 is turned on, and the signal of the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V IN2 The fifth transistor T5 is turned on, and the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3 until the voltage value of the signal at the third node N3 reaches V3 = V IN1 -Vth, Vth is the threshold voltage of the third transistor. At this time, the voltage stored in the first capacitor C1 is Vth, and the voltage stored in the second capacitor C2 is V IN2 -V IN1 +Vth.

[0527] In the third phase S3, the data writing phase, the signals at the first scanning signal terminal Gate1 and the third scanning signal terminal Gate3 are high-level signals, and the signals at the first emitting signal terminal EM1, the second emitting signal terminal EM2, the second scanning signal terminal Gate2, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0528] The first transistor T1 is turned on, and the signal of the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1=V IN1 The fourth transistor T4 is turned on, and the signal of the data signal terminal Data is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4=V data The voltage value of the signal at the fourth node N4 is V IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also jumps, V3 = V IN1 -Vth+(Vdata -V IN2 )(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0529] In the fourth stage, the bias stage, the signal of the fifth scan signal terminal Gate5 is a high-level signal, the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are low-level signals, the eighth transistor T8 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0530] The eighth transistor T8 is turned on, and the signal of the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2=V IN2 , where V IN2 is the voltage value of the signal at the second input signal terminal IN3.

[0531] In the fifth stage S5, the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, and the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0532] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power supply voltage output by the first power supply terminal VDD provides a driving current to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, thereby driving the light emitting device L to emit light.

[0533] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED , the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1=V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED+Vth-(V data -V IN2 )(C2 / C1+C2)

[0534] At this time, the driving current I flowing through the third transistor T3 (also the driving current driving the light emitting device L) satisfies:

[0535] I=K*(Vgs-Vth) 2

[0536] =K*(V1-V3-Vth) 2

[0537] =K*[(V IN2 -V data )(C2 / C1+C2)] 2

[0538] Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0539] Figure 48 The working process of the pixel driving circuit provided is similar to Figure 47 Compared with the working process of the pixel driving circuit provided, the difference is that the bias stage of initializing the second node N2 occurs after the data writing stage and before the light emitting stage to bias the driving transistor, thereby improving the hysteresis effect of the driving transistor after long-term action.

[0540] In an exemplary embodiment, Figure 17 、 Figure 18 、 Figure 21 、 Figure 22 、 Figure 31 、 Figure 32 、 Figure 33 、 Figures 36 to 40 The control electrode (i.e., the first node) of the third transistor (driving transistor) in the provided pixel driving circuit is electrically connected only to the first transistor T1. That is, in the light-emitting stage, the capacitance value of the parasitic capacitance coupled with the control electrode of the third transistor is relatively small, so that the parasitic capacitance of the first transistor has little effect on the signal of the first node N1, and the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit is not easily deviated, thereby ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0541] In an exemplary embodiment, Figure 17 、 Figure 18 、 Figure 21 、 Figure 22 、 Figure 31 、 Figure 32 、 Figure 33 、 Figures 36 to 40The control electrode (i.e., the first node) of the third transistor (driving transistor) in the provided pixel driving circuit is electrically connected only to the first transistor T1. That is, in the light-emitting stage, the capacitance value of the parasitic capacitance coupled with the control electrode of the third transistor is relatively small, so that the parasitic capacitance of the first transistor has little effect on the signal of the first node N1, and the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit is not easily deviated, thereby ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0542] In an exemplary embodiment, all transistors in the pixel driving circuit may be N-type transistors; or some transistors may be N-type transistors and some transistors may be P-type transistors. The N-type transistor may be made of a semiconductor oxide material, and the P-type transistor may be made of a low-temperature polysilicon material. The MOB and Ion of the P-type transistor are higher than those of the N-type transistor, and can be quickly turned on and off in scenarios where light emission and anode reset are used frequently. For example, the fifth transistor T5 may be a P-type transistor, that is, the fifth transistor T5 is disconnected when the signal at the first light-emitting signal terminal EM1 is a high-level signal, and is turned on when the signal is a low-level signal. Alternatively, the fifth transistor and the sixth transistor may be P-type transistors, or the fifth transistor, the sixth transistor, and the seventh transistor may be P-type transistors, which is conducive to high-frequency refresh and can be applied to PWM dimming scenarios. Alternatively, the fourth transistor may be a P-type transistor, which can increase the data writing speed. In this case, the second scanning signal terminal Gate2 and the third scanning signal terminal Gate3 can receive the same signal.

[0543] In an exemplary embodiment, Figure 17 、 Figure 18 、 Figure 21 、 Figure 22 In the provided pixel driving circuit, before and after the signal of the fourth node N4 jumps, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3:

[0544] [V3-(V IN1 -Vth)]*(C1+C OLED )+{(V3-Vdata)-[(V IN1 -Vth)-V IN2 ]}*C2=0, where C OLED is the parasitic capacitance of the light emitting device L.

[0545] V3=[C2 / (C1+C2+C OLED )]*(V IN2 -Vdata)+V IN1 -Vth

[0546] Since the signal of the first node N1 before the light emitting stage is the signal of the first input signal terminal IN1, that is, V1=V IN1, therefore, Vgs=V1-V3=[C2 / (C1+C2+C OLED )]*(V IN2 -Vdata)+Vth

[0547] In an exemplary embodiment, Figure 31 、 Figure 32 、 Figure 33 、 Figures 36 to 40 In the provided pixel driving circuit, before and after the signal of the fourth node N4 jumps, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3:

[0548] [V3-(V IN1 -Vth)]*C1+{(V3-Vdata)-[(V IN1 -Vth)-V IN2 ]}*C2=0

[0549] V3=[C2 / (C1+C2)]*(V IN2 -Vdata)+V IN1 -Vth

[0550] Since the signal of the first node N1 before the light emitting stage is the signal of the first input signal terminal IN1, that is, V1=V IN1 , therefore, Vgs=V1-V3=[C2 / (C1+C2)]*(V IN2 -Vdata)+Vth

[0551] Regarding the drive timing described above, for the embodiment including the T7 transistor, S1-S4 can be a refresh period. At a first drive frequency, a display frame can include a refresh period. The first drive frequency can be a frequency in a high-frequency drive mode. At a second drive frequency, a display frame can include a refresh period and at least one hold period. The hold period can be defined as a self-scan period in which no data signal is written, the data signal written in the refresh period is held, and the pixel emits light. The second drive frequency can be a frequency in a low-frequency drive mode. The hold period can include a first hold period and a second hold period. During the first hold period, only the seventh transistor T7 is turned on, while all other transistors are turned off to reset the anode of the light-emitting device. That is, the signal at the fourth scan signal terminal Gate4 is an active level signal. The seventh transistor T7 can be turned on multiple times, and the number of times is unlimited. During the second hold period, the seventh transistor T7 is turned off, and the fifth and sixth transistors T5 and T6 are turned on, causing the light-emitting device L to emit light.

[0552] When the embodiment further includes an eighth transistor T8, in the first holding phase, the eighth transistor T8 may also be turned on to write the fourth initial signal to the second node N2 to bias the driving transistor; the turn-on time of the eighth transistor T8 may occur after the turn-on time of the seventh transistor T7, or may be the same as the turn-on time of the seventh transistor T7. The present disclosure does not limit this. The eighth transistor T8 may be turned on multiple times, and the number of times is not limited.

[0553] An embodiment of the present disclosure further provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit provided by any of the aforementioned embodiments. The driving method for the pixel driving circuit may include:

[0554] Step 100: The driving sub-circuit provides a driving signal to the third node under the control of the signal of the first node;

[0555] Step 200: The first initial sub-circuit provides a signal from a first input signal terminal to a first node under the control of a signal from a first scan signal terminal.

[0556] Step 300: The coupling sub-circuit couples the signal of the data signal terminal or the second input signal terminal to the third node under the control of the signal of at least one scan signal terminal;

[0557] Step 400: The maintaining sub-circuit stores the voltage difference between the signals at the first node and the third node;

[0558] Step 500: The light-emitting control subcircuit provides a signal from the first power supply terminal to the second node under the control of the signal from the first light-emitting signal terminal.

[0559] An embodiment of the present disclosure further provides a display device, comprising: any one of the aforementioned pixel driving circuits arranged in an array.

[0560] A display device may include a timing controller, a data driver, a scan driver, a light emitting driver, a plurality of scan signal terminals, a plurality of data signal lines, a plurality of light emitting signal lines, and a pixel array, wherein the timing controller is connected to the data driver, the scan driver, and the light emitting driver, respectively. The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, a first light emitting signal terminal and a second light emitting signal terminal connected to the pixel driving circuit are electrically connected to the light emitting signal lines, at least one scan signal terminal connected to the pixel driving circuit is electrically connected to the scan signal lines, and a data signal terminal connected to the pixel driving circuit is electrically connected to the data signal lines.

[0561] The data driver is connected to a plurality of data signal lines, the scan driver is connected to a plurality of scan signal lines, and the light-emitting driver is connected to a plurality of light-emitting signal lines. In an exemplary embodiment, the timing controller may provide the data driver with grayscale values and control signals that are suitable for the specifications of the data driver, provide the scan driver with clock signals, scan start signals, and the like that are suitable for the specifications of the scan driver, and provide the light-emitting driver with clock signals, emission stop signals, and the like that are suitable for the specifications of the light-emitting driver. The data driver may use the grayscale values and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, the data driver may use the clock signal to sample the grayscale values and apply data voltages corresponding to the grayscale values to the data signal lines in units of pixel rows. The scan driver may generate scan signals to be provided to the scan signal lines by receiving the clock signal, scan start signal, and the like from the timing controller. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines. For example, the scan driver may be configured as a shift register and may generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal. The light-emitting driver may generate an emission signal to be provided to a light-emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver may sequentially provide an emission signal having an off-level pulse to the light-emitting signal line. For example, the light-emitting driver may be configured as a shift register and may generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal.

[0562] A display device may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units including a first subpixel emitting a first color light, a second subpixel emitting a second color light, and a third subpixel emitting a third color light, the first subpixel, the second subpixel, and the third subpixel each including a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel, the second subpixel, and the third subpixel are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel, the second subpixel, and the third subpixel are respectively connected to the pixel driving circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel in which they are located.

[0563] In an exemplary embodiment, the first subpixel may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0564] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0565] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure. In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally, vertically, or in a square pattern, which is not limited in this disclosure.

[0566] In an exemplary embodiment, the display device may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0567] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0568] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0569] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit, characterized in that: include: a driving subcircuit, a coupling subcircuit, a holding subcircuit, a first initial subcircuit, and a light emitting control subcircuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node; The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal and the first node respectively, and is configured to provide the signal of the first input signal terminal to the first node under the control of the signal of the first scan signal terminal; The coupling subcircuit is electrically connected to at least one scan signal terminal, the data signal terminal, the second input signal terminal and the third node respectively, and is configured to couple the signal of the data signal terminal or the second input signal terminal to the third node under the control of the signal of the at least one scan signal terminal; The holding sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store a voltage difference between the signals of the first node and the third node; The light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the first power supply terminal and the second node respectively, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signal of the first light-emitting signal terminal.

2. The pixel driving circuit according to claim 1, wherein: The at least one scanning signal terminal includes: a second scanning signal terminal and a third scanning signal terminal, and the coupling sub-circuit includes: a second transistor, a fourth transistor and a second capacitor; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node; The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node; A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the third node.

3. The pixel driving circuit according to claim 1, wherein: The at least one scanning signal terminal includes: a second scanning signal terminal, and the coupling sub-circuit includes: a second transistor and a second capacitor; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the data signal terminal in part of the time period and is electrically connected to the second input signal terminal in part of the time period, and the second electrode of the second transistor is electrically connected to the fourth node; A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the third node.

4. The pixel driving circuit according to claim 1, wherein: The first initial sub-circuit includes: a first transistor, the holding sub-circuit includes: a first capacitor, and the driving sub-circuit includes: a third transistor; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

5. The pixel driving circuit according to claim 1, wherein: The first initial sub-circuit includes: a first transistor, the holding sub-circuit includes: a first capacitor, the driving sub-circuit includes: a third transistor, and the third transistor includes: a first control electrode and a second control electrode; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node; a first control electrode of the third transistor is electrically connected to the first node, a second control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

6. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit is configured to drive the light emitting device to emit light, and the light emitting control subcircuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The light emitting device is electrically connected to the third node and the second power supply terminal respectively.

7. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit is configured to drive the light emitting device to emit light, and the light emitting control subcircuit is further electrically connected to the second light emitting signal terminal, the third node and the fifth node. The light emitting control subcircuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node; The light emitting device is electrically connected to the fifth node and the second power supply terminal respectively.

8. The pixel driving circuit according to claim 6 or 7, characterized in that: Also includes: a second initial subcircuit; The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal and the third node respectively, and is configured to provide the signal of the third input signal terminal to the third node under the control of the signal of the fourth scan signal terminal.

9. The pixel driving circuit according to claim 8, wherein: The second initial sub-circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node.

10. The pixel driving circuit according to claim 7, wherein: Also includes: a second initial subcircuit; The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal and the fifth node respectively, and is configured to provide the signal of the third input signal terminal to the fifth node under the control of the signal of the fourth scan signal terminal.

11. The pixel driving circuit according to claim 10, wherein: The second initial sub-circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

12. The pixel driving circuit according to claim 1, wherein: Also includes: a third initial subcircuit; The third initial sub-circuit is electrically connected to the fifth scan signal terminal, the fourth input signal terminal and the second node respectively, and is configured to provide the signal of the fourth input signal terminal to the second node under the control of the signal of the fifth scan signal terminal.

13. The pixel driving circuit according to claim 12, wherein: The third initial sub-circuit includes: an eighth transistor; The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth input signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

14. The pixel driving circuit according to claim 1, wherein: The signals received by the first input signal terminal and the first power supply terminal connected to the same pixel driving circuit are the same signal.

15. The pixel driving circuit according to claim 1, wherein: The signals received by the first signal input terminal and the second signal input terminal connected to the same pixel driving circuit are the same signal.

16. The pixel driving circuit according to claim 8, wherein: The signals received by the second signal input terminal and the third signal input terminal connected to the same pixel driving circuit are the same signal.

17. The pixel driving circuit according to claim 12, wherein: The signals received by the second input signal terminal and the fourth input signal terminal connected to the same pixel driving circuit are the same signal.

18. The pixel driving circuit according to claim 1, wherein: The signal received by the second scanning signal terminal connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal are the same signal, or the signal received by the second scanning signal terminal connected to the pixel driving circuit in the i-th row and the first scanning signal terminal of the pixel driving circuit in the i-1th row are the same signal.

19. The pixel driving circuit according to claim 13, wherein: The fourth scanning signal terminal and the fifth scanning signal terminal connected to the same pixel driving circuit receive the same signal.

20. The pixel driving circuit according to claim 2, wherein: The pixel driving circuit is also electrically connected to the fourth scanning signal terminal. The signal received by the third scanning signal terminal connected to the pixel driving circuit in the i-th row and the fourth scanning signal terminal of the pixel driving circuit in the i+K-th row is the same signal, where K is a positive integer greater than 1.

21. A display device, characterized in that: include: The pixel driving circuit according to any one of claims 1 to 20 is arranged in an array.

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