Chip and electronic equipment

Abstract

The utility model relates to a chip and electronic equipment, and the chip comprises a substrate which comprises a first region and a second region which are located in different position regions; the plurality of signal pins are arranged in the first area; the plurality of charging pin groups are arranged in the second area in an array form; wherein each charging pin group in the plurality of charging pin groups comprises a first charging pin and a second charging pin, and the first charging pin is electrically connected with the second charging pin. According to the chip, the signal pin and the charging pin group are respectively arranged in the two different position areas of the chip substrate, so that the power supply wiring and the signal wiring are designed separately, the interference of the power supply wiring on the signal wiring is reduced, and the internal impedance of the chip is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic chips, and in particular to a chip and an electronic device. Background Art

[0002] With the rapid development of electronic products, signal transmission rates on motherboards are increasing, placing higher and higher demands on electronic product design. The quality of signal transmission directly affects the performance and stability of various motherboard functions. During chip design, as chip size decreases, the pin spacing becomes closer, which interferes with chip signal transmission. Utility Model Content

[0003] To overcome the problems existing in the related art, the present disclosure provides a chip and an electronic device.

[0004] According to a first aspect of an embodiment of the present disclosure, a chip is provided, comprising: a substrate, comprising a first area and a second area located in different position areas; a plurality of signal pins, arranged in the first area; a plurality of charging pin groups, arranged in an array form in the second area; wherein each charging pin group in the plurality of charging pin groups comprises a first charging pin and a second charging pin, and the first charging pin is electrically connected to the second charging pin.

[0005] In some embodiments, first charging pins of adjacent charging pin groups in the array are arranged adjacent to each other, or second charging pins of adjacent charging pin groups in the array are arranged adjacent to each other.

[0006] In some embodiments, the substrate includes a first side and a second side, the first side and the second side are two opposite sides of the substrate, the first region is disposed adjacent to the first side, and the second region is disposed adjacent to the second side.

[0007] In some embodiments, the first charging pin and the second charging pin in the same charging pin group are adjacently arranged.

[0008] In some embodiments, the same charging pin group includes a plurality of first charging pins and a plurality of second charging pins arranged in an array, the plurality of first charging pins are located in the same row, and the plurality of second charging pins are located in another row.

[0009] In some embodiments, the multiple signal pins include a first signal pin and a second signal pin, the usage rate of the first signal pin is higher than the usage rate of the second signal pin; the distance between the first signal pin and the nearest edge of the substrate is a first distance; the distance between the second signal pin and the nearest edge of the substrate is a second distance; the first distance is smaller than the second distance.

[0010] In some embodiments, there are multiple first signal pins, and the first signal pins are arranged along an edge of the substrate.

[0011] In some embodiments, the first signal pins include one or more of a transient limit pin ILIM, a detection pin DET, a serial clock line pin SCL, a serial data line pin SDA, an address setting pin ADDR, and a ground pin GND.

[0012] In some embodiments, the second signal pin includes an interrupt pin INT and / or a temperature detection pin TS.

[0013] In some embodiments, the multiple charging pin groups include at least one of the following charging pins: a plurality of charging port pins CHG arranged in the first row of the second area; a plurality of battery pins BAT arranged in the second row of the second area; a plurality of battery pins BAT arranged in the third row of the second area; and a plurality of charging port pins CHG arranged in the fourth row of the second area.

[0014] In some embodiments, the multiple signal pins are arranged in an array, and the multiple signal pins include at least one of the following signal pins: an instantaneous limit pin ILIM and a detection pin DET arranged in sequence in the first row of the first area; a ground pin GND and a temperature detection pin TS arranged in sequence in the second row of the first area; an address setting pin ADDR and an interrupt pin INT arranged in sequence in the third row of the first area; and a serial clock line pin SCL and a serial data line pin SDA arranged in sequence in the fourth row of the first area.

[0015] In some embodiments, the first area includes a first side, which is a side adjacent to the detection pin DET, the temperature detection pin TS, the interrupt pin INT and the serial data line pin SDA, and the multiple charging pins are arranged on the first side of the first area.

[0016] According to a second aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: a circuit board; and the chip described in any one of the first aspects, wherein the chip is arranged on the circuit board.

[0017] In some embodiments, the first charging pin of the first pin group of the chip and the first charging pin of the second pin group of the chip are electrically connected through the circuit board.

[0018] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: the present disclosure arranges the signal pins and the charging pins in two different position areas of the chip substrate respectively, and arranges the same pins of adjacent pin groups adjacent to each other, so as to facilitate the separate design of the power lines and the signal lines, thereby reducing the interference of the power lines on the signal lines and reducing the internal impedance of the chip.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0021] Figure 1 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment.

[0022] Figure 2 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment.

[0023] Figure 3 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment. DETAILED DESCRIPTION

[0024] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0025] In related technologies, the chip is provided with charging pins involved in the charging and discharging process and signal pins for transmitting the model. Since the current in the wiring related to the charging pin is large, the charging wiring will interfere with the model of the signal wiring, thereby affecting the quality and integrity of the chip signal transmission process.

[0026] In order to solve the above technical problems, according to an embodiment of the present disclosure, a chip and an electronic device are provided, wherein the chip includes: a substrate, including a first area and a second area located in different position areas; a plurality of signal pins, arranged in the first area; a plurality of charging pin groups, arranged in an array form in the second area; wherein each charging pin group in the plurality of charging pin groups includes a first charging pin and a second charging pin, and the first charging pin is electrically connected to the second charging pin.

[0027] The present disclosure arranges the signal pin and the charging pin in two different positions on the chip substrate, so as to separate the power line and the signal line, thereby reducing the interference of the power line on the signal line and lowering the internal impedance of the chip.

[0028] It is understandable that the chip involved in the present disclosure can be applicable to any terminal listed below.

[0029] It is understandable that the terminal involved in the present disclosure may also be referred to as a terminal device, user equipment (UE), mobile station (MS), mobile terminal (MT), etc., which is a device that provides voice and / or data connectivity to users. For example, the terminal can be a handheld device with wireless connection function, a vehicle-mounted device, etc. At present, some examples of terminals are: smart phones (Mobile Phones), pocket personal computers (PPCs), handheld computers, personal digital assistants (PDAs), laptops, tablet computers, wearable devices, or vehicle-mounted devices, etc. In addition, when it is a vehicle-to-everything (V2X) communication system, the terminal device can also be a vehicle-mounted device. It should be understood that the embodiments of the present disclosure do not limit the specific technology and specific device form adopted by the terminal.

[0030] Figure 1 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment. Figure 2 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment. Figure 3 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment.

[0031] In some embodiments, as Figures 1 to 3 As shown, the chip may include: a substrate 100 , a plurality of signal pins 200 and a charging pin 300 .

[0032] The substrate 100 may be the main structure of the chip. For example, the substrate 100 may be a semiconductor structure constituting the main body of the chip.

[0033] A pin can be a metal interface used by a chip to connect to other external circuits.

[0034] The substrate 100 may include a first area 111 and a second area 112 located in different position areas. Multiple signal pins 200 can be set in the first area 111, and multiple charging pins 300 can be set in the second area 112, so that the lines connected to the signal pins 200 and the lines connected to the charging pins 300 can be designed separately, and the distance between the signal lines and the charging lines can be increased to reduce the interference of the charging lines with larger current on the signal lines, thereby improving the signal transmission stability of the signal lines.

[0035] The trace may be a line that connects from a pin to other circuits.

[0036] And since the signal pin 200 is connected to other circuits such as the processor, and the charging pin 300 is connected to the power supply, that is, the extension directions of the signal line and the charging line are different, therefore, setting the signal pin 200 in the first area 111 and setting the charging pin 300 in the second area 112 can allow the signal line to be extended without passing through the second area 112, and allow the charging line to be extended without passing through the first area 111, thereby reducing the crossing between the signal line and the charging line, thereby reducing the interference of the charging line on the signal line, and simplifying the chip routing design.

[0037] Each of the plurality of charging pin groups includes a first charging pin and a second charging pin, wherein the first charging pin is electrically connected to the second charging pin, and the first charging pins of adjacent charging pin groups in the array are adjacently arranged or the second charging pins are adjacently arranged.

[0038] The charging pins 300 may be grouped into a plurality of charging pin groups. Each of the plurality of charging pin groups includes a first charging pin 301 and a second charging pin 302 . The first charging pin 301 is electrically connected to the second charging pin 302 .

[0039] Among them, the first charging pins 301 of adjacent pin groups can be arranged adjacent to each other, so as to reduce the distance between the first charging pins 301 of adjacent pin groups, and reduce the internal conduction impedance of the chip between adjacent pin groups to reduce the loss of charging current and discharging current when passing through the chip.

[0040] In other embodiments, the second charging pins 302 in adjacent pin groups can be arranged adjacent to each other, thereby reducing the spacing between the second charging pins 302 of adjacent pin groups and reducing the internal conduction impedance of the chip between adjacent pin groups to reduce the loss of charging current and discharging current when passing through the chip.

[0041] In some embodiments, as Figure 1 and Figure 2As shown, the substrate 100 may include a first side and a second side relative to each other, and the first area 111 and the second area 112 may be arranged adjacent to the first side and the second side, so that the first area 111 and the second area 112 are respectively arranged in two opposite parts of the substrate 100. By respectively arranging the first area 111 and the second area 112 in two opposite parts of the substrate 100, the spacing between the first area 111 and the second area 112 can be increased, so that the trace connected to the signal pin 200 and the trace connected to the charging pin 300 can be designed separately, and the distance between the signal trace and the charging trace is increased to reduce the interference of the charging trace with a larger current on the signal trace, thereby improving the signal transmission stability of the signal trace.

[0042] In some embodiments, as Figure 1 and Figure 2 As shown, the plurality of signal pins 200 may include a first signal pin 201 and a second signal pin 202. The distance between the first signal pin 201 and the nearest edge of the substrate 100 may be a first distance, and the distance between the second signal pin 202 and the nearest edge of the substrate 100 may be a second distance. Figure 2 As shown, the first signal pin 201 may include a ground pin GND, and the second signal pin 202 may include a temperature detection pin TS. The distance between the ground pin GND and the nearest edge of the substrate 100 is the distance to the first side of the substrate 100, and the distance between the temperature detection pin TS and the nearest edge of the substrate 100 is the distance to the first side of the substrate 100. The distance between the ground pin GND and the first side of the substrate 100 is less than the distance between the temperature detection pin TS and the first side of the substrate 100.

[0043] The minimum distance between the first signal pin 201 and the edge of the substrate 100 is smaller than the minimum distance between the second signal pin 202 and the edge, so that the first signal pin 201 is closer to the edge of the chip. The wiring connected to the first signal pin 201 does not need to pass through or bypass the second signal pin 202, which can reduce the wiring design connected to the first signal pin 201.

[0044] The first signal pin 201 may be a pin with a higher usage rate, and the second signal pin 202 may be a pin with a lower usage rate, so as to reduce the routing design of the first signal pin 201 with a higher usage rate.

[0045] The pin usage rate can be the ratio of pin usage in different product solutions of the chip. For example, in 10 product solutions, the ground pin GND is used, and the temperature detection pin TS is used in 5 of them. In this case, the ground pin GND has a higher usage rate than the temperature detection pin TS.

[0046] Exemplarily, the chip can be applied to different electronic devices, wherein a variety of electronic devices need to use the first signal pin 201 , and some electronic devices do not need to use the second signal pin 202 .

[0047] In some embodiments, as Figure 1 and Figure 2 As shown, the number of the first signal pins 201 can be multiple, and the first signal pins 201 can be set along the edge of the substrate 100, which can make it easier for the routing connected to the first signal pins 201 with a higher utilization rate to extend outside the substrate 100, and can further reduce the distance span of the routing connected to the first signal pins 201 with a higher utilization rate, reduce the design difficulty of the signal routing, and improve the utilization rate of the chip's edge portion, thereby improving the chip's substrate 100 area utilization rate, which helps to further miniaturize the chip.

[0048] Figure 3 The figure is a schematic diagram showing chip pin distribution according to an exemplary embodiment.

[0049] In some embodiments, as Figure 3 As shown, the charging pin 300 may include a plurality of pin groups, and each pin group may include a first charging pin 301 and a second charging pin 302 .

[0050] The first charging pin 301 and the second charging pin 302 can be pins for charging and discharging current to flow into or out of the chip. For example, the first charging pin 301 can be connected to an external load and an external charging port, and the second charging pin 302 can be connected to an external battery. When charging the external battery, current can flow into the chip from the first charging pin 301 and out of the chip from the second charging pin 302. When the external battery is discharging, current can flow into the chip from the second charging pin 302 and out of the chip from the first charging pin 301.

[0051] Since the current during the charging and discharging process is relatively large, a plurality of charging pins 300 may be provided to reduce the current burden of a single charging pin 300 .

[0052] For example, the first charging pin 301 may be a charging port pin CHG, and the second charging pin 302 may be a battery pin BAT.

[0053] The first charging pin 301 can be electrically connected to the second charging pin 302. For example, the chip can include multiple sets of metal-oxide semiconductor field-effect transistors connected in parallel, the first charging pin 301 can be one end of the metal-oxide semiconductor field-effect transistor, and the second charging pin 302 can be the other end of the metal-oxide semiconductor field-effect transistor, so that the first charging pin 301 and the second charging pin 302 are electrically connected.

[0054] The first charging pin 301 and the second charging pin 302 can be arranged adjacent to each other to reduce the span distance between the first charging pin 301 and the second charging pin 302, thereby reducing the internal conduction impedance of the chip between the first charging pin 301 and the second charging pin 302, so as to reduce the loss of the charging current and the discharging current when passing through the chip.

[0055] In some embodiments, as Figure 3 As shown, the same pin group includes a plurality of first charging pins and a plurality of second charging pins arranged in an array, the plurality of first charging pins are located in the same row, and the plurality of second charging pins are located in another row.

[0056] The above arrangement enables the charging pins within the pin group to form a mutually parallel array, thereby reducing the maximum spacing between the charging pins 300 of adjacent pin groups, and reducing the internal conduction impedance of the chip between adjacent pin groups, thereby reducing the loss of charging current and discharging current when passing through the chip.

[0057] In some embodiments, the first charging pins 301 of adjacent pin groups are arranged adjacent to each other, thereby reducing the spacing between the first charging pins 301 of adjacent pin groups and reducing the internal conduction impedance of the chip between adjacent pin groups to reduce the loss of charging current and discharging current passing through the chip.

[0058] In other embodiments, the second charging pins 302 of adjacent pin groups are arranged adjacent to each other, thereby reducing the spacing between the second charging pins 302 of adjacent pin groups and reducing the internal conduction impedance of the chip between adjacent pin groups, thereby reducing the loss of charging current and discharging current when passing through the chip.

[0059] In some embodiments, as Figure 3 As shown, the charging pins 300 may include a first pin group 310 and a second pin group 320. The substrate 100 may include a third side 101 and a fourth side 102, wherein the third side 101 and the fourth side 102 may be two different sides of the substrate 100.

[0060] The first charging pin 301 of the first pin group 310 may be disposed close to the third side 101 of the substrate 100 , and the first charging pin 301 of the second pin group 320 may be disposed close to the fourth side 102 of the substrate 100 .

[0061] The second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 can be positioned between the first charging pin 301 of the first pin group 310 and the first charging pin 301 of the second pin group 320. Furthermore, the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 can be positioned adjacent to each other to reduce the distance between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320. This facilitates wiring within the chip, electrically connecting the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320, and placing the first pin group 310 and the second pin group 320 in parallel.

[0062] By reducing the distance between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320, the line length between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 can be reduced, thereby reducing the internal conduction impedance of the chip between the first charging pin 301 and the second charging pin 302, thereby reducing the loss of the charging current and the discharging current when passing through the chip.

[0063] In some embodiments, the third side 101 and the fourth side 102 are opposite sides of the substrate 100. By placing the first charging pin 301 of the first pin group 310 closer to the third side 101 of the substrate 100, the first charging pin 301 of the second pin group 320 can be placed on the fourth side 102 of the substrate 100. This increases the spacing between the first charging pin 301 of the first pin group 310 and the first charging pin 301 of the second pin group 320, leaving available area for the centralized placement of the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the first pin group 310. This further shortens the spacing between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the first pin group 310, improves chip edge area utilization, and facilitates chip miniaturization.

[0064] In other embodiments, the second charging pin 302 of the first pin group 310 may be disposed near the third side 101 of the substrate 100, and the second charging pin 302 of the second pin group 320 may be disposed near the fourth side 102 of the substrate 100. The second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 may be disposed between the first charging pin 301 of the first pin group 310 and the first charging pin 301 of the second pin group 320.

[0065] Furthermore, the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 can be arranged adjacent to each other to reduce the distance between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320, so as to facilitate setting a circuit inside the chip, so that the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 are electrically connected, and the first pin group 310 and the second pin group 320 are in parallel.

[0066] By reducing the distance between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320, the line length between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the second pin group 320 can be reduced, thereby reducing the internal conduction impedance of the chip between the first charging pin 301 and the second charging pin 302, thereby reducing the loss of the charging current and the discharging current when passing through the chip.

[0067] In some embodiments, as Figure 1-Figure 3 As shown, the first charging pins 301 and the second charging pins 302 are distributed in a rectangular array.

[0068] The above arrangement can also make the array of multiple second charging pins 302 of the first pin group 310 and the array of multiple second charging pins 302 of the first pin group 310 parallel to each other, thereby reducing the maximum spacing between the second charging pins 302 of the first pin group 310 and the second charging pins 302 of the second pin group 320, and reducing the maximum internal on-resistance of the chip between the first charging pin 301 and the second charging pin 302, so as to reduce the maximum loss of charging current and discharging current when passing through the chip.

[0069] In some embodiments, as Figure 2 and Figure 3 As shown, the first signal pins 201 may include one or more of a transient limit pin ILIM, a detection pin DET, a serial clock line pin SCL, a serial data line pin SDA, an address setting pin ADDR, and a ground pin GND.

[0070] The instantaneous limit pin ILIM can be used as a current or power limiting protection mechanism to protect the device from damage. The detection pin DET can be used to determine if the battery is in the battery compartment. If the battery is not in the battery compartment, the charging circuit is prevented from charging. If the battery is in the battery compartment, the detection pin DET can be grounded to enable normal charging operation.

[0071] The serial clock line pin SCL and the serial data line pin SDA are used to realize serial communication between the chip and external devices.

[0072] The address setting pin ADDR can be connected to different resistors to make the chip present different address characteristics, so that the system of the electronic device can identify different chip addresses.

[0073] The ground pin GND can provide an analog signal ground for the chip.

[0074] By arranging the above-mentioned type of pins near the edge of the substrate 100 , the routing design of the above-mentioned pins can be made easier, thereby reducing the routing design cost of the chip in different application scenarios.

[0075] In some embodiments, as Figure 2 and Figure 3 As shown, the second signal pin 202 may include an interrupt pin INT and / or a temperature detection pin TS.

[0076] The temperature detection pin TS can be used to implement the battery temperature protection function.

[0077] The interrupt pin INT can be used by the chip to send an interrupt signal to the outside of the system to notify the occurrence of specific events including fault time.

[0078] By arranging the pins with low usage rates at locations away from the edge of the substrate 100 , the routing design near the first signal pins 201 of the substrate 100 can be made easier, thereby reducing the routing design cost of the chip in different application scenarios.

[0079] In some embodiments, as Figure 2 and Figure 3 As shown, multiple charging pins 300 are arranged in an array, and the charging pins 300 can be distributed in four rows within the second area 112. The first row of the second area 112 can be provided with multiple charging port pins CHG; the second row of the second area 112 can be provided with multiple battery pins BAT; the third row of the second area 112 can be provided with multiple battery pins BAT; and the fourth row of the second area 112 can be provided with multiple charging port pins CHG.

[0080] The first row of charging port pins CHG are arranged close to the third side 101, and the fourth row of charging port pins CHG are arranged close to the fourth side 102. The second row of battery pins BAT and the third row of battery pins BAT can be arranged adjacent to each other.

[0081] For example, the first row and the fourth row may each be provided with three charging port pins CHG, and the second row and the third row may each be provided with three battery pins BAT.

[0082] In some embodiments, as Figure 2 and Figure 3As shown, a plurality of signal pins 200 are arranged in an array, and the signal pins 200 can be distributed in four rows within the first area 111. The first row of the first area 111 is sequentially provided with an instantaneous limit pin ILIM and a detection pin DET, the second row of the first area 111 is sequentially provided with a ground pin GND and a temperature detection pin TS, the third row of the first area 111 is sequentially provided with an address setting pin ADDR and an interrupt pin INT, and the fourth row of the first area 111 is sequentially provided with a serial clock line pin SCL and a serial data line pin SDA.

[0083] In some embodiments, as Figure 2 and Figure 3 As shown, the first region 111 includes a first side, which may be adjacent to the detection pin DET, the temperature detection pin TS, the interrupt pin INT, and the serial data line pin SDA. The plurality of charging pins 300 may be disposed on the first side of the first region 111. The first region 111 may also include a second side, which may be adjacent to the transient limit pin ILIM, the ground pin GND, the address setting pin ADDR, and the serial clock line pin SCL. The first edge of the substrate may be located on the second side of the first region 111.

[0084] Based on the same concept, an embodiment of the present disclosure further provides an electronic device.

[0085] The electronic device may include a laptop computer, desktop computer, mobile phone, digital broadcast terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, translation machine, and wearable device such as a watch or bracelet, and may be any electronic device with a chip. In the following description, a mobile phone is used as an example, but the present disclosure is not limited to this.

[0086] In some embodiments, an electronic device includes: a circuit board and a chip, wherein the chip can be disposed on the circuit board. The chip can be a power management chip that can be used to manage the charging and discharging process of the electronic device.

[0087] In some embodiments, the first charging pin 301 of the chip's first pin group 310 and the first charging pin 301 of the chip's second pin group 320 are electrically connected via a circuit board. This configuration allows the first charging pin 301 of the first pin group 310 and the first charging pin 301 of the second pin group 320 to be electrically connected while maintaining a relatively large spacing. This leaves available space for the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the first pin group 310 to be centrally located, further shortening the spacing between the second charging pin 302 of the first pin group 310 and the second charging pin 302 of the first pin group 310. This also improves the utilization of the chip's edge area, facilitating chip miniaturization.

[0088] The embodiment of the present disclosure may include a first area 111 and a second area 112 located in different position areas through the substrate 100. Multiple signal pins 200 can be set in the first area 111, and multiple charging pins 300 can be set in the second area 112, so that the lines connected to the signal pins 200 and the lines connected to the charging pins 300 can be designed separately, and the distance between the signal lines and the charging lines can be increased to reduce the interference of the charging lines with larger current on the signal lines, thereby improving the signal transmission stability of the signal lines.

[0089] And since the signal pin 200 is connected to other circuits such as the processor, and the charging pin 300 is connected to the power supply, that is, the extension directions of the signal line and the charging line are different, therefore, setting the signal pin 200 in the first area 111 and setting the charging pin 300 in the second area 112 can allow the signal line to be extended without passing through the second area 112, and allow the charging line to be extended without passing through the first area 111, thereby reducing the crossing between the signal line and the charging line, thereby reducing the interference of the charging line on the signal line, and simplifying the chip routing design.

[0090] It is understood that in this disclosure, "plurality" refers to two or more than two, and other quantifiers are similar. "And / or" describes the association relationship of related objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship. The singular forms "a", "the" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0091] It is further understood that the terms "second," "second," and the like are used to describe various information, but such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another and do not indicate a particular order or level of importance. In fact, expressions such as "second," "secondary," and the like are fully interchangeable. For example, without departing from the scope of this disclosure, the second information may also be referred to as the second information, and similarly, the second information may also be referred to as the second information.

[0092] It can be further understood that the terms "center", "longitudinal", "lateral", "front", "back", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this embodiment and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation.

[0093] It is further understood that, unless otherwise specified, “connection” includes a direct connection where there are no other components between the two elements, and also includes an indirect connection where there are other elements between the two elements.

[0094] It is further understood that although operations are described in a particular order in the drawings in the embodiments of the present disclosure, this should not be construed as requiring that the operations be performed in the particular order shown or in a serial order, or that all of the operations shown be performed to obtain the desired results. In certain circumstances, multitasking and parallel processing may be advantageous.

[0095] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0096] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the scope of the appended claims.

Claims

1. A chip, characterized in that: The chip includes: The substrate includes a first region and a second region located in different position areas; a plurality of signal pins, arranged in the first area; a plurality of charging pin groups arranged in an array in the second area; Each of the plurality of charging pin groups includes a first charging pin and a second charging pin, and the first charging pin is electrically connected to the second charging pin.

2. The chip according to claim 1, characterized in that The first charging pins of adjacent charging pin groups in the array are arranged adjacent to each other, or The second charging pins of adjacent charging pin groups in the array are arranged adjacent to each other.

3. The chip according to claim 1, characterized in that The substrate includes a first side and a second side, wherein the first side and the second side are two opposite sides of the substrate, the first region is disposed adjacent to the first side, and the second region is disposed adjacent to the second side.

4. The chip according to claim 1, characterized in that The first charging pin and the second charging pin in the same charging pin group are arranged adjacent to each other.

5. The chip according to claim 1, characterized in that The same charging pin group includes a plurality of first charging pins and a plurality of second charging pins arranged in an array, wherein the plurality of first charging pins are located in the same row, and the plurality of second charging pins are located in another row.

6. The chip according to claim 1, characterized in that The plurality of signal pins include a first signal pin and a second signal pin, wherein a usage rate of the first signal pin is higher than a usage rate of the second signal pin; The distance between the first signal pin and the nearest edge of the substrate is a first distance; The distance between the second signal pin and the nearest edge of the substrate is a second distance; The first distance is smaller than the second distance.

7. The chip according to claim 6, characterized in that There are a plurality of first signal pins, and the first signal pins are arranged along the edge of the substrate.

8. The chip according to claim 6, characterized in that The first signal pins include one or more of an instantaneous limit pin ILIM, a detection pin DET, a serial clock line pin SCL, a serial data line pin SDA, an address setting pin ADDR and a ground pin GND.

9. The chip according to claim 6, characterized in that The second signal pin includes an interrupt pin INT and / or a temperature detection pin TS.

10. The chip according to claim 9, characterized in that The plurality of charging pin groups include at least one of the following charging pins: a plurality of charging port pins CHG arranged in a first row of the second area; a plurality of battery pins BAT arranged in a second row in the second area; a plurality of battery pins BAT arranged in a third row in the second area; A plurality of charging port pins CHG are disposed in a fourth row of the second area.

11. The chip according to claim 10, characterized in that The plurality of signal pins are arranged in an array, and the plurality of signal pins include at least one of the following signal pins: An instantaneous limit pin ILIM and a detection pin DET are sequentially arranged in the first row of the first area; A ground pin GND and a temperature detection pin TS are sequentially arranged in the second row of the first area; An address setting pin ADDR and an interrupt pin INT are sequentially arranged in the third row of the first area; The fourth row of the first area is provided with serial clock line pins SCL and serial data line pins SDA in sequence.

12. The chip according to claim 11, characterized in that The first area includes a first side, which is a side adjacent to the detection pin DET, the temperature detection pin TS, the interrupt pin INT, and the serial data line pin SDA. The multiple charging pins are arranged on the first side of the first area.

13. An electronic device, characterized in that: include: circuit boards; The chip according to any one of claims 1 to 12, wherein the chip is arranged on the circuit board.

14. The electronic device according to claim 13, wherein: The first charging pin of the first pin group of the chip and the first charging pin of the second pin group of the chip are electrically connected through the circuit board.

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