Micro-display chip based on multi-layer stacking

Abstract

The utility model relates to a micro-display chip based on multilayer stacking, which comprises a driving wafer, a first pixel layer and a second pixel layer, and an anode contact is arranged on the driving wafer; the first pixel layer is stacked on the driving wafer in the Z direction, an anode connecting piece and auxiliary pixels are arranged in the first pixel layer, and the anode connecting piece penetrates through one auxiliary pixel and then is electrically connected with the corresponding anode contact; the second pixel layer is stacked on the first pixel layer in the Z direction, sub-pixels corresponding to the anode connecting pieces are arranged in the second pixel layer, and the sub-pixels in the second pixel layer are electrically connected with the corresponding anode connecting pieces in the first pixel layer. The manufacturing method is simpler, the operation is convenient, and the manufacturing period of the display chip is effectively shortened.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a micro display chip based on multi-layer stacking. Background Art

[0002] In the field of LED display, micro-display technology has been widely developed in recent years, especially Micro-LED display technology, which has the advantages of high efficiency, low power consumption, high integration and high stability, and is considered to be one of the most promising next-generation new display and light-emitting devices. Micro-LED display technology has now been widely used in near-eye display terminal products, including virtual reality (VR), augmented reality (AR), mixed reality (MR), etc. The display area of the existing micro-display chip is usually arranged with a plurality of pixel units arranged in an array. In order to further reduce the horizontal size of the micro-display chip and increase the pixel density, the prior art can set the chip into a vertically stacked multi-layer structure, and each layer is provided with a light-emitting pixel unit. In this multi-layer structure, Figure 1 As shown, the upper pixel unit needs to be connected to the anode of the driver wafer 10 through the anode connector 306 of the lower layer. In order to configure the above-mentioned anode connector 306, the layer where the anode connector is located generally needs to be specially prepared to reserve a separate space for placing the anode connector while avoiding the pixel unit. This preparation method is relatively cumbersome and cannot utilize the original single-layer pixel structure for superposition, which increases the preparation cycle of the display chip and cannot meet production needs. Utility Model Content

[0003] Therefore, the technical problem to be solved by the present invention is to overcome the defects of the prior art in that the preparation of the multi-layer structure display chip is complicated and the preparation cycle is long.

[0004] In order to solve the above technical problems, the present invention provides a micro display chip based on multi-layer stacking, comprising:

[0005] a driving wafer, wherein an anode contact is provided on the driving wafer;

[0006] a first pixel layer, the first pixel layer being stacked on the driving wafer along the Z direction, the first pixel layer being provided with an anode connector and auxiliary pixels, the anode connector passing through one of the auxiliary pixels and being electrically connected to a corresponding anode contact;

[0007] A second pixel layer is stacked on the first pixel layer along the Z direction, sub-pixels corresponding to the anode connector are provided in the second pixel layer, and the sub-pixels in the second pixel layer are electrically connected to the corresponding anode connector in the first pixel layer.

[0008] In one embodiment of the present invention, an anode hole is provided on the auxiliary pixel through which the anode connector passes, the anode hole is filled with the anode connector, and the anode hole has an inclination angle of 90° to 120° relative to the top surface of the driving wafer.

[0009] In one embodiment of the present invention, each of the sub-pixels and auxiliary pixels includes a pixel body, and each of the pixel bodies is provided with a bonding metal part on the side close to the driving wafer, and the bonding metal part of the sub-pixel in the second pixel layer is electrically connected to the corresponding anode connector in the first pixel layer.

[0010] In one embodiment of the present invention, a cathode contact is also provided on the driving wafer, the first pixel layer and the second pixel layer both include an insulating body, the pixel bodies in the first pixel layer and the second pixel layer are both located inside the insulating body, the outside of each pixel body is covered with an insulating passivation layer, the bonding metal part is located inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outside of the insulating passivation layer of the sub-pixel is covered with a common cathode layer, the pixel body of the sub-pixel is electrically connected to the common cathode layer through the opening, and the common cathode layer is used to be electrically connected to the cathode contact.

[0011] In one embodiment of the present invention, the pixel bodies include a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence along the Z direction, the bonding metal part is provided on the side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer of the sub-pixel is electrically connected to the common cathode layer through the opening.

[0012] In one embodiment of the present invention, a cathode connector is further provided in the first pixel layer, and the cathode connector passes through another auxiliary pixel and is electrically connected to the cathode contact. The common cathode layer in the second pixel layer is electrically connected to the cathode connector.

[0013] In one embodiment of the present invention, the pixel body is trapezoidal or cylindrical.

[0014] In one embodiment of the present invention, sub-pixels are also provided in the first pixel layer.

[0015] In one embodiment of the present invention, the light emitting colors of the sub-pixels in the first pixel layer and the second pixel layer are different.

[0016] In one embodiment of the present invention, a color conversion element is further provided in the second pixel layer, and an excitation pixel is provided in the first pixel layer. Each color conversion element corresponds to an excitation pixel one by one, and the color conversion element is located on the light output path of the corresponding excitation pixel.

[0017] In one embodiment of the present invention, the light emitting color of the sub-pixels in the second pixel layer is different from the light emitting color of the color conversion element.

[0018] In one embodiment of the present invention, filling holes are provided in the second pixel layer, and each of the filling holes is filled with the color conversion element.

[0019] In one embodiment of the present invention, an insulating layer is formed on the inner wall of the filling hole, and the insulating layer is a metal reflective layer or a light absorbing layer.

[0020] In one embodiment of the present invention, the thickness of the insulating layer is 50 nm to 2 um.

[0021] The above technical solution of the utility model has the following advantages compared with the prior art:

[0022] The multi-layer stacked micro display chip of the present invention is easier to prepare, has a simpler preparation method, is more convenient to operate, and effectively shortens the preparation period of the display chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0024] Figure 1 It is a schematic diagram of the structure of a display chip in the prior art;

[0025] Figure 2 It is a comparative diagram of trapezoidal pixels and hemispherical pixels;

[0026] Figure 3 This is a schematic diagram of the internal structure of a multi-layer stacked micro display chip of the present invention;

[0027] Figure 4 yes Figure 3 A partial enlarged view of point G in the middle;

[0028] Figure 5 This is a partial preparation flow chart of the chip of the present invention;

[0029] Figure 6 yes Figure 3 Flow chart for the preparation of the structure shown;

[0030] Figure 7 This is a schematic diagram of the internal structure of the second multi-layer stacked micro display chip of the present invention;

[0031] Figure 8 This is a schematic diagram of the internal structure of the third multi-layer stacked micro display chip of the present invention;

[0032] Description of the accompanying drawings:

[0033] 10. Driver wafer; 101. Anode contact; 102. Cathode contact;

[0034] 20, sub-pixel; 201, pixel body; 2011, P-type ohmic contact layer; 2012, P-type semiconductor layer; 2013, active layer; 2014, N-type semiconductor layer; 2015, N-type ohmic contact layer;

[0035] 30, first pixel layer; 301, insulating body; 302, bonding layer; 3021, bonding metal member; 303, insulating passivation layer; 3031, opening; 304, common cathode layer; 3041, auxiliary hole; 305, anode hole; 306, anode connector; 307, cathode hole; 308, cathode connector;

[0036] 40, second pixel layer; 401, filling hole; 402, isolation layer;

[0037] 50. Auxiliary pixels;

[0038] 60. Excite pixel;

[0039] 70. Color transfer parts;

[0040] 80. Compound semiconductor; 801. Substrate;

[0041] 90. Lens. DETAILED DESCRIPTION

[0042] The present invention is further described below with reference to the accompanying drawings and specific embodiments to enable those skilled in the art to better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention. It is apparent that the embodiments described are only some of the embodiments of the present disclosure, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present disclosure, its application, or use.

[0043] In the description of the present invention, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0044] The following will be combined Figure 2-Figure 8 , the structure of this embodiment is further described.

[0045] It should be noted that, for the convenience of description, the micro display chip in the present invention has mutually perpendicular Z and X directions, wherein the Z direction is generally the direction away from the driver wafer. In the present invention, "up" and "down" are relative in the Z direction, and similarly, "top", "bottom" or "high" and "low" are also relative in the Z direction.

[0046] Example 1

[0047] See Figure 3-Figure 7 This embodiment discloses a multi-layer stacked microdisplay chip, including a driver wafer 10, a first pixel layer 30, and a second pixel layer 40. The driver wafer 10 has a driver circuit inside for controlling the emission of sub-pixels 20 in the pixel layer. The driver wafer 10 can be a CMOS driver wafer.

[0048] The driver wafer 10 is provided with an anode contact 101;

[0049] The first pixel layer 30 is stacked on the driving wafer 10 along the Z direction. The first pixel layer 30 is provided with an anode connector 306 and an auxiliary pixel 50. The anode connector 306 passes through an auxiliary pixel 50 and is electrically connected to the corresponding anode contact 101.

[0050] The second pixel layer 40 is stacked on the first pixel layer 30 along the Z direction, and sub-pixels 20 corresponding to the anode connector 306 are provided in the second pixel layer 40. The sub-pixels 20 in the second pixel layer 40 are electrically connected to the corresponding anode connector 306 in the first pixel layer 30, that is, the sub-pixels 20 in the second pixel layer 40 are electrically connected to the anode contact 101 of the driving wafer 10 through the corresponding anode connector 306 in the lower layer.

[0051] The auxiliary pixel 50 in the above structure can be an original pixel in the first pixel layer 30, and the pixel can be directly used as an auxiliary pixel 50. When in use, it is only necessary to make the anode connector 306 in the first pixel layer 30 pass through an auxiliary pixel 50 and then electrically connect it to the corresponding anode contact 101 on the driving wafer 10. This method can avoid re-preparing the first pixel layer 30, and can directly use the original single-layer monochrome pixel product, that is, the second layer and above pixel layers can be directly superimposed on the original single-layer product for use. The preparation method is faster, which can reduce the cost of special and separate preparation of the first pixel layer 30, and the operation is simpler and more convenient, shortening the preparation cycle of the display chip.

[0052] It should be noted that after the auxiliary pixel 50 is penetrated by the anode connector 306 , the auxiliary pixel 50 cannot emit light normally and is only used as a connector.

[0053] In some embodiments, the top end length (X direction) of the anode hole 305 is greater than the bottom end length.

[0054] In some embodiments, an anode hole 305 is provided on the auxiliary pixel 50 through which the anode connector 306 passes. The anode hole 305 is filled with an anode metal material to form the anode connector 306 . The anode hole 305 has an inclination angle φ of 90° to 120° relative to the top surface of the driver wafer 10 .

[0055] Furthermore, the anode hole 305 may be trapezoidal or Y-shaped.

[0056] In one embodiment, the length of the top of the anode connector 306 in the X direction is greater than the length of the bottom, that is, it presents a structure that is wide at the top and narrow at the bottom. When the bottom length is the same, this shape of structure can obtain a thicker anode connector 306 compared to the structure that is narrow at the top and wide at the bottom, thereby enhancing the anode electrical transmission capacity.

[0057] In some embodiments, each sub-pixel 20 and auxiliary pixel 50 includes a pixel body 201, and a bonding metal part 3021 is provided on the side of each pixel body 201 close to the driving wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the second pixel layer 40 is electrically connected to the corresponding anode connector 306 in the first pixel layer 30, that is, the bonding metal part 3021 of the sub-pixel 20 in the second pixel layer 40 is electrically connected to the anode contact 101 of the driving wafer 10 through the anode connector 306.

[0058] It can be understood that if the first pixel layer 30 is the bottom pixel layer and sub-pixels 20 are also provided in the first pixel layer 30, the bonding metal part 3021 of the sub-pixel 20 can be directly electrically connected to the anode contact 101 of the driving wafer 10 through its bonding metal part 3021.

[0059] In some embodiments, a cathode contact 102 is further provided on the driver wafer 10. The first pixel layer 30 and the second pixel layer 40 both include an insulating body 301. The pixel bodies 201 in the first pixel layer 30 and the second pixel layer 40 are both located inside the insulating body 301. The exterior of each pixel body 201 is covered with an insulating passivation layer 303. A bonding metal part 3021 is located inside the insulating passivation layer 303. The upper portion of the insulating passivation layer 303 has an opening 3031.

[0060] In each sub-pixel 20, the outside of the insulating passivation layer 303 of the pixel body 201 of the sub-pixel 20 is covered with a common cathode layer 304, and the pixel body 201 of the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to be electrically connected to the cathode contact 102 to achieve cathode connection between the sub-pixel 20 and the driving wafer 10.

[0061] It can be understood that in the auxiliary pixel 50, the outside of the insulating passivation layer 303 of the pixel body 201 of the auxiliary pixel 50 may not be covered with the common cathode layer 304 or the common cathode layer 304 may be removed to avoid short circuit between the common cathode layer 304 and the anode connector 306 in the auxiliary pixel 50. The anode connector 306 in the auxiliary pixel 50 can pass through the opening 3031 of the insulating passivation layer 303 and penetrate the auxiliary pixel.

[0062] In addition, if the exterior of the insulating passivation layer 303 of the auxiliary pixel 50 still covers the common cathode layer 304, an auxiliary hole 3041 for the anode connector 306 to pass through can be provided in the common cathode layer 304. In this case, the anode connector 306 needs to sequentially pass through the auxiliary hole 3041 of the common cathode layer 304 of the auxiliary pixel and the opening 3031 of the insulating passivation layer 303, then penetrate the pixel body 201 and be electrically connected to the anode contact 101 of the driver wafer 10. To prevent the anode connector 306 from contacting the common cathode layer 304 outside the auxiliary pixel 50, an auxiliary hole 3041 is provided in the common cathode layer 304 outside the pixel body of the auxiliary pixel 50 for the anode connector 306 to pass through. Figure 6 As shown in stage d, the length L4 of the auxiliary hole 3041 in the X direction is greater than the length L5 of the opening 3031 of the insulating passivation layer 303 at the top of the auxiliary pixel 50 .

[0063] Among them, Figure 4As shown, the pixel body 201 includes a P-type semiconductor layer 2012, an active layer 2013 and an N-type semiconductor layer 2014 arranged in sequence along the Z direction, the active layer 2013 is used to emit light, and a bonding metal part 3021 is provided on the side of the P-type semiconductor layer 2012 close to the driving wafer 10. The N-type semiconductor layer of the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031 of the insulating passivation layer, and the common cathode layer 304 is used to be electrically connected to the cathode contact 102. The P-type semiconductor layer of the sub-pixel 20 is used to be electrically connected to the anode contact 101 through the bonding metal part 3021.

[0064] The bonding metal parts 3021 may correspond to the anode contacts 101 one by one, or multiple anode contacts 101 may correspond to one bonding metal part 3021 .

[0065] In some embodiments, the pixel body 201 includes a P-type ohmic contact layer 2011 , a P-type semiconductor layer 2012 , an active layer 2013 , and an N-type semiconductor layer 2014 sequentially arranged along the Z direction;

[0066] The active layer 2013 is used to emit light. A bonding metal member 3021 is provided on the side of the P-type semiconductor layer 2012 near the driver wafer 10. A P-type ohmic contact layer 2011 is provided between the P-type semiconductor layer 2012 and the bonding metal member 3021 to achieve better ohmic contact between the P-type semiconductor layer 2012 and the bonding metal member 3021. This ultimately allows the P-type semiconductor layer 2012 of the sub-pixel 20 to be electrically connected to the corresponding anode contact 101 through the bonding metal member 3021, thereby achieving anode connection. The N-type semiconductor layer of the sub-pixel 20 is exposed at the aforementioned opening 3031, and the exposed portion is electrically connected to the common cathode layer 304. The common cathode layer 304 is used to connect to the cathode contact 102 of the driver wafer 10 to achieve cathode connection. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 2014 and the P-type semiconductor layer 2012 in the pixel body 201 to prevent short circuits.

[0067] In some embodiments, the thickness of the P-type ohmic contact layer 2011 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe, AnZn, etc.

[0068] In some embodiments, the thickness of the insulating passivation layer 303 is 30 nm to 500 nm to better ensure insulation and passivation capabilities.

[0069] In some embodiments, the thickness of the common cathode layer 304 is 50nm to 500nm, so as to maximize its transmittance while ensuring the current expansion capability. The thicker the common cathode layer 304, the better the current expansion, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current expansion capability.

[0070] In some embodiments, a cathode connector 308 is further provided in the first pixel layer 30 . The cathode connector 308 passes through another auxiliary pixel 50 and is electrically connected to the cathode contact 102 . The common cathode layer 304 in the second pixel layer 40 is electrically connected to the cathode connector 308 .

[0071] A cathode hole 307 may be provided on the auxiliary pixel 50 where a cathode connector 308 is required, and a cathode metal material may be filled in the cathode hole 307 to form the cathode connector 308 . The structure of the cathode connector 308 is the same as that of the anode connector 306 and will not be described in detail here.

[0072] For example, Figure 3 As shown, two auxiliary pixels 50 and three sub-pixels 20 are arranged in the first pixel layer 30, wherein one auxiliary pixel 50 is provided with an anode connection 306, and another auxiliary pixel 50 is provided with a cathode connection 308, and the second pixel layer 40 is provided with one sub-pixel 20; Figure 7 As shown, four auxiliary pixels 50 and one sub-pixel 20 are arranged in the first pixel layer 30 , wherein three auxiliary pixels 50 are provided with anode connectors 306 , and another auxiliary pixel 50 is provided with cathode connectors 308 . The second pixel layer 40 is provided with three sub-pixels 20 .

[0073] In some embodiments, pixel body 201 has a trapezoidal or cylindrical shape.

[0074] like Figure 3 As shown, the pixel body 201 is trapezoidal or cylindrical. Compared with the pixels with hemispherical or semi-ellipsoidal structures, the trapezoidal or cylindrical pixels can effectively increase the pixel luminous area, thereby increasing the luminous intensity. The pixel generally has an active layer 2013 to emit light. Figure 2 It can be seen that, given the same pixel base dimensions, the active layer area (the entire shaded area) of the trapezoidal pixel is larger than the active layer area of the hemispherical pixel (the shaded area within the hemisphere), effectively increasing the luminous intensity. Similarly, cylindrical pixels can also increase the area of the active layer 2013 compared to hemispherical pixels, effectively increasing luminous intensity.

[0075] In some embodiments, as Figure 6As shown in stage d, the height D of the pixel body 201 in the Z direction is 0.3um~5um; preferably, D is 0.3um~1.5um; wherein the height of the pixel body 201 is the distance between its P-type semiconductor layer 2012 and the N-type semiconductor layer 2014 (including the thickness of the P-type semiconductor layer 2012 and the N-type semiconductor layer 2014 themselves).

[0076] Furthermore, the sidewall of the pixel body 201 has an inclination angle θ relative to the driver wafer 10 of 45° to 135°. It can be understood that the sidewall of the pixel body 201 here refers to the wall between the top and bottom surfaces of the pixel body 201.

[0077] The above-mentioned tilt angle can reduce total reflection and is more conducive to light extraction. Exceeding this range will reduce the light extraction efficiency. In addition, due to limited horizontal space, a certain amount of space needs to be reserved for subsequent processes. If the tilt angle is too small, the bottom surface of the pixel occupies too much horizontal space, which will increase the difficulty of pixel spacing arrangement.

[0078] Preferably, the inclination angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0079] Furthermore, sub-pixels 20 are also provided in the first pixel layer 30 .

[0080] In one embodiment, the light emitting colors of the sub-pixels 20 in the first pixel layer 30 and the second pixel layer 40 may be the same, so as to achieve a multi-layer monochrome setting.

[0081] In another embodiment, the light emitting colors of the sub-pixels 20 in the first pixel layer 30 and the second pixel layer 40 are different to achieve a multi-layer multi-color setting, for example, Figure 3 As shown, the light emitting color of the sub-pixel 20 in the first pixel layer 30 is red, and the number of sub-pixels 20 is 3; the light emitting color of the sub-pixel 20 in the second pixel layer 40 is green, and the number of sub-pixels 20 is 1; or, as shown in FIG. Figure 7 As shown, the light emitting color of the sub-pixel 20 in the first pixel layer 30 is green, and the number of sub-pixels arranged is 1. The light emitting color of the sub-pixel 20 in the second pixel layer 40 is red, and the number of sub-pixels arranged is 3. In actual working conditions, the specific pixel layer where the sub-pixels of different colors are located and the number of sub-pixels arranged can be selected as needed and are not limited here.

[0082] On the basis of the above two pixel layers, other pixel layers may be further stacked to form an arrangement of three or more layers.

[0083] Furthermore, the projections of all sub-pixels 20 on the driver wafer 10 do not overlap, so as to minimize the optical crosstalk between the sub-pixels 20 or the color variation caused by photoexcitation, thereby more accurately controlling the light combining effect.

[0084] In some embodiments, a lens 90 may be further connected to the upper portion of the second pixel layer 40, with multiple sub-pixels 20 corresponding to one lens 90, or a lens 90 and a sub-pixel 20 corresponding one to one. This approach can better collimate the outgoing light of each sub-pixel 20 and further reduce light interference.

[0085] This embodiment also discloses a method for preparing a multi-layer stacked microdisplay chip, comprising:

[0086] Step M1: preparing a driver wafer 10 and setting an anode contact 101 on the driver wafer 10;

[0087] Step M2: The first pixel layer 30 and the second pixel layer 40 are stacked in sequence along the Z direction on the driving wafer 10, so that the first pixel layer 30 is provided with an anode connector 306 and an auxiliary pixel 50, and the anode connector 306 passes through an auxiliary pixel 50 and is electrically connected to the corresponding anode contact 101, and the second pixel layer 40 is provided with a sub-pixel 20 corresponding to the anode connector 306, and the sub-pixel 20 in the second pixel layer 40 is electrically connected to the corresponding anode connector 306 in the first pixel layer 30.

[0088] In some embodiments, when preparing the first pixel layer 30, an anode hole 305 needs to be set on the auxiliary pixel 50 through which the anode connector 306 passes, and an anode metal material is filled in the anode hole 305 to form the anode connector 306. The inclination angle φ of the anode hole 305 relative to the top surface of the driving wafer 10 is 90° to 120°.

[0089] In one embodiment, Figure 6 As shown in stage f, after step M2, a dielectric layer is further deposited on the upper portion of the second pixel layer 40, and the dielectric layer is patterned and etched to form a lens 90, so that a plurality of sub-pixels 20 correspond to one lens 90, or each sub-pixel 20 corresponds to one lens 90 individually, so as to better collimate the outgoing light of each sub-pixel 20 and further reduce light interference.

[0090] In some embodiments, step M2 comprises:

[0091] Step M21: bonding a compound semiconductor 80 to the driver wafer 10; for example, the compound semiconductor 80 may be bonded to the driver wafer 10 via the bonding layer 302;

[0092] like Figure 5As shown, the compound semiconductor 80 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, an N-type semiconductor layer 2014, and a substrate 801, which are sequentially arranged in a direction away from the driver wafer 10. After the compound semiconductor 80 is bonded to the driver wafer 10, the substrate 801 needs to be removed to expose the N-type semiconductor layer 2014. After removing the substrate 801, as shown in FIG. Figure 5 As shown in stage c, an N-type ohmic contact layer 2015 may be further provided on the N-type semiconductor layer 2014;

[0093] Furthermore, the thickness of the N-type ohmic contact layer 2015 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or a metal alloy film such as gold germanium alloy (AuGe), gold nickel alloy (AuNi), etc.

[0094] Preferably, the thickness of the N-type ohmic contact layer 2015 is 10 nm to 100 nm, so as to ensure ohmic contact while also having a high transmittance, thereby reducing light loss.

[0095] Step M22: Patterning and etching the compound semiconductor 80 to obtain at least one group of pixels, wherein the group of pixels includes auxiliary pixels 50, each auxiliary pixel 50 including a pixel body 201, each pixel body 201 corresponding to a bonding metal member 3021; wherein the bonding metal member 3021 can be obtained by etching the bonding layer 302;

[0096] Step M23: depositing an insulating passivation layer 303 outside the pixel body 201 of the auxiliary pixel 50 and providing an opening 3031 on the upper portion of the insulating passivation layer 303;

[0097] Step M24: providing a through anode hole 305 on the auxiliary pixel 50 where the anode connector 306 is to be arranged. The anode hole 305 passes through the opening 3031. The anode hole 305 is filled with an anode metal material to form the anode connector 306. The anode connector 306 passes through the auxiliary pixel 50 and is electrically connected to the corresponding anode contact 101.

[0098] Step M25: Fill the insulating body 301 so that the pixel bodies 201 are all located inside the insulating body 301, thereby obtaining the following: Figure 6 The first pixel layer 30 shown in stage d;

[0099] Step M26: Bond another compound semiconductor 80 on top of the first pixel layer 30, and pattern-etch the compound semiconductor 80 to obtain a sub-pixel 20. The sub-pixel 20 also includes a pixel body 201. The pixel body 201 of this layer is electrically connected to the corresponding anode connector 306 via a bonding metal part 3021. Then, an insulating passivation layer 303 is deposited outside the pixel body 201. An opening 3031 is provided in the upper portion of the insulating passivation layer 303 to expose the N-type semiconductor layer 2014 or the N-type ohmic contact layer 2015 of the pixel body 201. A common cathode layer 304 is deposited outside the insulating passivation layer 303, so that the pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect to the cathode contact 102. That is, the N-type semiconductor layer 2014 of the pixel body 201 is electrically connected to the cathode contact 102 via the common cathode layer 304, thereby achieving cathode connection.

[0100] The insulating body 301 is filled outside the common cathode layer 304 so that the pixel bodies 201 of this layer are all located inside the insulating body 301, thereby obtaining the following: Figure 6 The second pixel layer 40 is shown in stage e.

[0101] Furthermore, when preparing the first pixel layer 30, the compound semiconductor 80 is patterned and etched to obtain at least one group of pixels. In addition to the auxiliary pixel 50, the group of pixels also has a sub-pixel 20. The outside of the pixel body 201 of the sub-pixel 20 is sequentially provided with an insulating passivation layer 303 and a common cathode layer 304. The N-type semiconductor layer 2014 of the pixel body 201 of the sub-pixel 20 is electrically connected to the cathode contact 102 through the common cathode layer 304.

[0102] It is understandable that if the light emission colors of the sub-pixels 20 in the two pixel layers are different, then the materials of the compound semiconductors 80 used in the preparation of the two pixel layers are also different, so that the light emission colors of the compound semiconductors used are different.

[0103] For example, the P-type semiconductor layer 2012 and the N-type semiconductor layer 2014 in the compound semiconductor 80 can both be made of materials such as gallium nitride (GaN), the substrate 801 can be made of materials such as gallium nitride (GaN), silicon (Si) or sapphire (Sapphire), and the active layer 2013 can be made of materials such as indium gallium nitride (InGaN).

[0104] In one embodiment, the insulating passivation layer 303 may be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0105] In one embodiment, the insulating body 301 may be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbon nitride (SiCN), phosphate glass (PSG), and borophosphosilicate glass (BPSG).

[0106] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0107] In one embodiment, the anode connector 306 may be made of one or more of aluminum, copper, and tungsten.

[0108] Furthermore, the material of the cathode connector 308 can be the same as that of the anode connector 306 , that is, a conductive material.

[0109] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, Cu, or a stacked structure of Ni, Au, Cu, etc. and Sn, or a bonding stack of Au, In, Ge, or Au and Si.

[0110] Furthermore, the bonding metal part 3021 may adopt the following structure: Cr2nm / Pt50nm / Ti10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, wherein Cr is an adhesion layer and Pt / Ti / Pt is a barrier layer.

[0111] Example 2

[0112] See Figure 8 The main difference between this embodiment and the first embodiment is that a color conversion element 70 is further provided in the second pixel layer 40, and excitation pixels 60 are provided in the first pixel layer 30. Each color conversion element 70 corresponds to an excitation pixel 60 one by one, and the color conversion element 70 is located on the light output path of the corresponding excitation pixel 60, so that the light emitted by the excitation pixel 60 is directed to the color conversion element 70, thereby stimulating the color conversion element 70 to emit light of a specific color.

[0113] The sub-pixels 20 are all electrically connected to the driving wafer 10, which has a driving circuit to control the sub-pixels 20 to emit light. It can be understood that the excitation pixels 60 are also electrically connected to the driving wafer 10 to control the excitation pixels 60 to emit light.

[0114] Among them, the structure of the excitation pixel 60 is the same as that of the sub-pixel 20. The excitation pixel 60 also includes a pixel body 201. Each pixel body 201 is provided with a bonding metal part 3021 on the side close to the driving wafer 10. The bonding metal part 3021 of the excitation pixel 60 is electrically connected to the anode contact 101 of the driving wafer 10; the outside of each pixel body 201 is covered with an insulating passivation layer 303, and the bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031, and the outside of the insulating passivation layer 303 is covered with a common cathode layer 304. The pixel body 201 of the excitation pixel 60 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to be electrically connected to the cathode contact 102 to realize the cathode connection between the excitation pixel 60 and the driving wafer 10.

[0115] In some embodiments, the light emitting color of the sub-pixel 20 in the second pixel layer 40 is different from the light emitting color of the color conversion element 70 .

[0116] In some embodiments, the light emitted by the sub-pixel 20 in the second pixel layer 40 is green, and the color of the light ultimately emitted by the color conversion element 70 after being excited by the excitation pixel 60 is red; the light emitted by the excitation pixel 60 is also blue.

[0117] It should be noted that the wavelength of the light emitting from the exciting pixel 60 needs to be shorter than the wavelength of red light, so that the shorter wavelength light can be used to excite the color conversion element 70 to convert the color and emit red light. The red light color conversion element is made of quantum dot material or red phosphor material.

[0118] Furthermore, a sub-pixel 20 is also provided in the first pixel layer 30 . The light output color of the sub-pixel 20 is blue and is directly emitted through the second pixel layer 40 .

[0119] Furthermore, the light emitting color of all pixels in the first pixel layer 30 can be made blue, for ease of preparation. It is only necessary to use some pixels in the layer only as excitation pixels 60, some pixels as sub-pixels 20, and the remaining part as auxiliary pixels 50. No other sub-pixels 20 are set on the light emitting path above the sub-pixels 20 in the first pixel layer 30, so that blue light can be emitted through the second pixel layer 40. Then the light finally emitted through the second pixel layer 40 has three different colors of light, namely blue light emitted by the blue sub-pixel 20, green light emitted by the green sub-pixel 20 and red light emitted by the color conversion element 70, thereby realizing a three-color configuration.

[0120] Similarly, a two-color configuration can also be achieved, which will not be described here.

[0121] In some embodiments, the red light color converter can use quantum dot materials, such as indium phosphide (InP); it can also use phosphor materials, such as fluoride system phosphor - KSF red phosphor (K2SiF6:Mn4+), or nitride Eu2+ doped CaAlSiN3 based red phosphor, etc.

[0122] In some embodiments, filling holes 401 are provided in the second pixel layer 40 , and each filling hole 401 is filled with a color conversion material to form a color conversion member 70 .

[0123] The color conversion element 70 may be made of quantum dot material or phosphor material.

[0124] Furthermore, the filling hole 401 is opened in the insulating body 301 of the second pixel layer 40 .

[0125] In some embodiments, the length Ls of the filling hole 401 along the X direction is not less than the maximum length of the excitation pixel 60 in the X direction, and the X direction is perpendicular to the Z direction. This method can provide a good light channel for the excitation pixel 60 below and reduce the occurrence of optical crosstalk, thereby ensuring the greatest possible color conversion effect.

[0126] Furthermore, the inner wall of the filling hole 401 is tilted relative to the driver wafer 10 , and the tilt angle C is 60° to 90°, so as to facilitate etching while ensuring the filling effect.

[0127] In some embodiments, an isolation layer 402 is formed on the inner wall of the filling hole 401 ; the isolation layer 402 is used to shield light interference from pixels below the non-filled space, so that the color conversion element 70 inside the filling hole 401 can have a better color conversion effect.

[0128] The isolation layer 402 is a metal reflective layer or a light absorbing layer.

[0129] The material of the metal reflective layer can be one or more of metals Al, Ti, Pt, Au, Cr and Ni, so as to shield light interference through metal reflection; the material of the light-absorbing layer can be carbon film, black glue, polysilicon and other light-absorbing materials, so as to shield light interference through light absorption.

[0130] Furthermore, the thickness of the insulating layer 402 is 50 nm to 2 um. If the thickness is too thin, leakage is likely to occur, while if the thickness is too thick, the cost will increase.

[0131] Specifically, the thickness required for light interference shielding can be achieved according to different materials, such as Al ≥ 50nm, black glue ≥ 1um.

[0132] In some embodiments, a lens 90 is further connected to the upper portion of the second pixel layer 40, and multiple sub-pixels 20 correspond to one lens 90, or the lens 90 and the sub-pixel 20 correspond one to one. This approach can better collimate the output light of each sub-pixel 20 and further reduce light interference.

[0133] In some embodiments, each color conversion element 70 also corresponds to a lens 90 , or multiple color conversion elements 70 correspond to one lens 90 .

[0134] The method for preparing the micro display chip in this embodiment is substantially the same as that in the first embodiment, except that the color conversion element 70 and the excitation pixel 60 need to be prepared, which will not be described in detail here.

[0135] The micro-display chips of the above-mentioned embodiments can directly use the original pixels in the first pixel layer as auxiliary pixels. This method can avoid the need to re-prepare the first pixel layer and can directly use the original single-layer pixel products. The preparation method is faster and can reduce the cost of specially preparing the first pixel layer. The operation is simpler and more convenient, and the preparation cycle of the display chip is shortened.

[0136] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the scope of protection of this application and will not be described in detail here.

[0137] It should be noted that the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A micro-display chip based on multi-layer stacking, characterized in that: include, a driving wafer, wherein an anode contact is provided on the driving wafer; a first pixel layer, the first pixel layer being stacked on the driving wafer along the Z direction, the first pixel layer being provided with an anode connector and auxiliary pixels, the anode connector passing through one of the auxiliary pixels and being electrically connected to a corresponding anode contact; A second pixel layer is stacked on the first pixel layer along the Z direction, sub-pixels corresponding to the anode connector are provided in the second pixel layer, and the sub-pixels in the second pixel layer are electrically connected to the corresponding anode connector in the first pixel layer.

2. The multi-layer stacked microdisplay chip according to claim 1, characterized in that: An anode hole is provided on the auxiliary pixel through which the anode connector passes. The anode hole is filled with the anode connector. The anode hole has an inclination angle of 90° to 120° relative to the top surface of the driving wafer.

3. The multi-layer stacked microdisplay chip according to claim 1, wherein: Each of the sub-pixels and auxiliary pixels includes a pixel body, and a bonding metal part is provided on the side of each pixel body close to the driving wafer. The bonding metal part of the sub-pixel in the second pixel layer is electrically connected to the corresponding anode connector in the first pixel layer.

4. The multi-layer stacked microdisplay chip according to claim 3, wherein: A cathode contact is also provided on the driving wafer, and the first pixel layer and the second pixel layer both include an insulating body. The pixel bodies in the first pixel layer and the second pixel layer are both located inside the insulating body, and the outside of each pixel body is covered with an insulating passivation layer. The bonding metal part is located inside the insulating passivation layer, and the upper part of the insulating passivation layer has an opening. The outside of the insulating passivation layer of the sub-pixel is covered with a common cathode layer, and the pixel body of the sub-pixel is electrically connected to the common cathode layer through the opening, and the common cathode layer is used to be electrically connected to the cathode contact.

5. The multi-layer stacked micro-display chip according to claim 4, characterized in that: The pixel bodies all include a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence along the Z direction. The bonding metal part is provided on the side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer of the sub-pixel is electrically connected to the common cathode layer through the opening.

6. The multi-layer stacked microdisplay chip according to claim 4, characterized in that: A cathode connector is further provided in the first pixel layer. The cathode connector passes through another auxiliary pixel and is electrically connected to the cathode contact. The common cathode layer in the second pixel layer is electrically connected to the cathode connector.

7. The multi-layer stacked micro-display chip according to claim 3, characterized in that: The pixel body is in a trapezoidal or cylindrical shape.

8. The multi-layer stacked microdisplay chip according to claim 1, wherein: Sub-pixels are also provided in the first pixel layer.

9. The multi-layer stacked micro-display chip according to claim 8, characterized in that: The light emitting colors of the sub-pixels in the first pixel layer and the second pixel layer are different.

10. The multi-layer stacked microdisplay chip according to claim 1, characterized in that: The second pixel layer is further provided with a color conversion element, the first pixel layer is provided with excitation pixels, each color conversion element corresponds to an excitation pixel one by one, and the color conversion element is located on the light output path of the corresponding excitation pixel.

11. The multi-layer stacked microdisplay chip according to claim 10, characterized in that: The light-emitting color of the sub-pixels in the second pixel layer is different from the light-emitting color of the color conversion element.

12. The multi-layer stacked micro-display chip according to claim 10, characterized in that: Filling holes are provided in the second pixel layer, and each of the filling holes is filled with the color conversion element.

13. The multi-layer stacked micro-display chip according to claim 12, characterized in that: An insulating layer is formed on the inner wall of the filling hole, and the insulating layer is a metal reflective layer or a light absorbing layer.

14. The multi-layer stacked micro-display chip according to claim 13, characterized in that: The thickness of the insulating layer is 50nm-2um.

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