Chip testing device, chip testing system and transceiver testing system
By designing test devices compatible with multiple types of chips, including test boards, expansion boards and power supply interfaces, the problem of high testing costs in the existing technology is solved, and lower cost and more efficient chip testing is achieved.
Patent Information
- Application Number
- CN202421933450.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-08-09
AI Technical Summary
The existing chip test device has a single function, resulting in high testing costs.
It provides a chip testing device, including a test board, an expansion board and a variety of voltage power supply interfaces, supports the connection and power supply of multiple types of chips, is compatible with a variety of communication protocols, and can be tested in high and low temperature boxes.
It reduces the comprehensive testing cost of multiple types of chips and improves the versatility and efficiency of testing.
Smart Images
Figure CN223229700U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of chip testing technology, and specifically relates to a chip testing device, a chip testing system, and a testing system dedicated to a transceiver. Background Art
[0002] Automatic Test Equipment (ATE) plays a vital role in the semiconductor industry. It is used to test the functional integrity of integrated circuits (ICs) and ensure the functional integrity and production quality of ICs.
[0003] Before fully testing a chip, design companies typically perform basic functional verification—simple verification of the chip's internal programs—to improve the pass rate of subsequent tests. However, current chip testing equipment has limited functionality, resulting in high testing costs. Therefore, there is an urgent need for a chip testing device with more comprehensive functionality and lower testing costs. Utility Model Content
[0004] In response to the problems existing in the above-mentioned prior art, a chip testing device, a chip testing system and a testing system dedicated to transceivers are proposed. By using this chip testing device, chip testing system and a testing system dedicated to transceivers, the comprehensive testing cost of various types of chips can be reduced.
[0005] This application provides the following solutions.
[0006] In a first aspect, the present application provides a chip testing device, comprising: a test board, an expansion board connected to the test board, and a power supply interface of multiple voltages;
[0007] The expansion board is used to connect different types of chips to be tested;
[0008] A test platform is built on the test board, which is compatible with multiple communications;
[0009] The power supply interface with multiple voltages is used to power different types of chips under test.
[0010] In some possible embodiments, the test panel is placed in a high and low temperature box.
[0011] In some possible embodiments, the chip testing device further includes: a status indicator, the status indicator being communicatively connected to the testing board;
[0012] The status indicator is used to indicate the communication status between the test board and the chip to be tested.
[0013] In some possible embodiments, the test board is provided with an analog-to-digital converter port, and the analog-to-digital converter port is used to output voltage and current data of the chip to be tested.
[0014] In some possible embodiments, the chip testing device further includes a display screen;
[0015] The analog-to-digital converter port of the test board is connected to a display screen, which is used to display the voltage and current data of the chip under test.
[0016] In some possible embodiments, the chip to be tested is placed in a high and low temperature box;
[0017] The number of chips to be tested that can be connected to the device simultaneously is determined by the volume of the high and low temperature chamber.
[0018] In some possible embodiments, the test board is a microcontroller unit MCU;
[0019] The expansion board is configured as: a test unit or a test function module DUT connected to the microcontroller unit MCU.
[0020] In some possible embodiments, the test platform is compatible with serial peripheral interface communication SPI and inter-integrated circuit communication IIC.
[0021] In a second aspect, the present application provides a chip testing system, including the above-mentioned chip testing device.
[0022] In a third aspect, the present application provides a test system dedicated to a transceiver, including the above-mentioned chip testing device.
[0023] The chip testing device provided in the embodiment of the present application can connect the test board to various types of chips to be tested through various types of expansion boards connected to the test board. A test platform is built on the test board, which is compatible with various types of communications. The chip testing device is also provided with various types of power supply interfaces, which can power various types of chips to be tested. In this way, the chip testing device provided in the embodiment of the present application can be compatible with the testing of various types of chips, which can reduce the comprehensive testing cost of various types of chips.
[0024] Other advantages of the present application will be explained in more detail with reference to the following description and accompanying drawings.
[0025] It should be understood that the above description is only an overview of the technical solution of this application, so that the technical means of this application can be more clearly understood and implemented in accordance with the contents of the description. In order to make the above and other purposes, features and advantages of this application more obvious and easy to understand, the following examples are used to illustrate the specific implementation methods of this application. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The advantages and benefits described herein, as well as other advantages and benefits, will be apparent to those skilled in the art upon reading the detailed description of the exemplary embodiments below. The accompanying drawings are provided for illustration purposes only and are not to be considered limiting of the present application. The same reference numerals are used throughout the accompanying drawings to denote the same components. In the accompanying drawings:
[0027] Figure 1 A schematic diagram of a chip testing device provided in an embodiment of the present application;
[0028] Figure 1a A schematic diagram of a chip testing device for a broadband transceiver provided in an embodiment of the present application;
[0029] Figure 1b A schematic diagram of a chip testing device for a narrowband transceiver provided in an embodiment of the present application;
[0030] Figure 2 A schematic diagram of a chip testing device provided in an embodiment of the present application;
[0031] Figure 3 A schematic diagram of a test board in a chip testing device provided in an embodiment of the present application;
[0032] Figure 4 A schematic diagram of an expansion board in a chip testing device provided in an embodiment of the present application.
[0033] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION
[0034] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although the accompanying drawings illustrate exemplary embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.
[0035] In the description of the embodiments of the present application, it should be understood that terms such as "including" or "having" are intended to indicate the presence of disclosed features, numbers, steps, behaviors, components, parts, or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, numbers, steps, behaviors, components, parts, or combinations thereof. The terms "first", "second", etc. are used only for the convenience of description to distinguish between the same or similar technical features, and cannot be understood as indicating or implying the relative importance or quantity of these technical features. Thus, the features defined by "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the term "plurality" means two or more than two.
[0036] Unless otherwise specified, " / " means or. For example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. For convenience of description, spatial relationship terms such as "under," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.
[0037] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0038] See also Figure 1 , which is a schematic diagram of a chip testing device provided in an embodiment of the present application.
[0039] like Figure 1 As shown, the chip testing device provided in the embodiment of the present application includes: a test board 100, an expansion board 200 connected to the test board, and a power supply interface 300 of multiple voltages;
[0040] The expansion board 200 is used to connect different types of chips to be tested;
[0041] A test platform is built on the test board 100, and the test platform is compatible with multiple communications;
[0042] The multi-voltage power supply interface 300 is used to supply power to different types of chips under test.
[0043] The chip to be tested in the embodiment of the present application may be a chip in a transceiver, such as Figure 1aAs shown, the chip testing device provided in the embodiment of the present application can be connected to a broadband transceiver to test the broadband transceiver or one or more chips integrated in the broadband transceiver. Figure 1b As shown, the chip testing device provided in the embodiment of the present application can be connected to a narrowband transceiver to test one or more chips in the narrowband transceiver or integrated in the narrowband transceiver.
[0044] It should be noted that, in the embodiment of the present application, the test board 100 is a microcontroller unit MCU; the expansion board 200 is configured as: a test unit or a test function module (Device Under Test, DUT) connected to the microcontroller unit MCU, which can be referred to as a "mother-daughter board" structure in the embodiment of the present application. The power supply interface 300 of multiple voltages in the embodiment of the present application can include an adjustable power supply interface that provides 3.3V and 5V voltages, which can meet the power supply requirements of a variety of products. In actual correspondence, the power supply interface 300 in the embodiment of the present application can also provide other voltages, and the embodiment of the present application is not limited here. The test platform in the embodiment of the present application can be compatible with multiple communications, such as serial peripheral interface communication (Serial Peripheral Interface, SPI) and inter-integrated circuit communication (Inter-Integrated Circuit, IIC). In actual applications, the test platform in the present application can also be built using C language, which can simplify the program of the test platform to a certain extent, and C language is easy to operate and modify, has strong readability, and is convenient for modifying and updating the test platform.
[0045] Therefore, it can be seen that the chip testing device provided in the embodiment of the present application can connect the test board to various types of chips to be tested through various types of expansion boards connected to the test board, eliminating the need to switch dedicated test boards for different types of chips to be tested. When the chip to be tested is updated due to product development or other reasons, the present application does not need to redesign the test board, and only needs to update the expansion board to make the chip testing device in the present application compatible with the new chip to be tested.
[0046] Furthermore, the test board in the embodiment of the present application is equipped with a test platform that is compatible with various types of communications. The chip testing device is also provided with various types of power supply interfaces that can power various types of chips to be tested. Thus, the chip testing device provided in the embodiment of the present application is compatible with testing various types of chips, thereby reducing the comprehensive testing costs of various types of chips.
[0047] As a possible implementation method, the test board provided in the embodiment of the present application can be arranged in a high and low temperature box. The chip to be tested in the embodiment of the present application can also be arranged in a high and low temperature box. In this way, the chip testing device provided by the present application does not need to build an additional heat flow hood platform, and the high and low temperature box can ensure that the ambient temperature of the chip to be tested is fixed, which is convenient for high and low temperature experiments on the chip to be tested. In actual applications, the number of chips to be tested that can be connected simultaneously to the chip testing device provided by the present application can be determined by the volume of the high and low temperature box. When the volume of the high and low temperature box is large, more chips to be tested can be accommodated in the high and low temperature box, so the chip testing device is connected to more chips to be tested at the same time, and multiple chips to be tested can be tested at the same time.
[0048] like Figure 2 As shown, in an embodiment of the present application, the chip testing device may further include a status indicator 400. The status indicator 400 is communicatively connected to the test board. The status indicator 400 is used to indicate the communication status between the test board and the chip to be tested. As an example, the status indicator in the present application may be an LED indicator light. When the communication between the test board and the chip to be tested is normal, the LED light is green. When the communication between the test board and the chip to be tested is abnormal, the LED light is red. When the chip to be tested can be read back normally, the LED light is blue.
[0049] As a possible implementation, the test board 100 in the embodiment of the present application can be provided with an analog-to-digital converter (ADC) port 101, which is used to output the voltage and current data of the chip under test. The present application utilizes the ADC port to collect the voltage and current data of the chip in real time, so that during the experiment, it is possible to observe whether the voltage and current data of the chip are offset, which facilitates the technician to adjust the test program in real time.
[0050] As a possible implementation, Figure 2 As shown, the chip testing device in the embodiment of the present application may further include a display screen 500. The analog-to-digital converter port of the test board is connected to the display screen 500, which is used to display the voltage, current and temperature data of the chip under test, so that technicians can adjust the test program in real time.
[0051] As an example, the specific circuit diagram of the test board in the chip testing device in the embodiment of the present application can be as follows: Figure 3 As shown, the specific circuit diagram of the expansion board can be as follows Figure 4As shown. In summary, the chip testing device provided in the embodiment of the present application can connect the test board to various types of chips to be tested through various types of expansion boards connected to the test board, without the need to test special test boards for different types of chips to be tested. A test platform is built on the test board in the embodiment of the present application, and the platform is compatible with various types of communications. The chip testing device is also provided with various types of power supply interfaces, which can supply power to various types of chips to be tested. In this way, the chip testing device provided in the embodiment of the present application can be compatible with the testing of various types of chips, and can reduce the comprehensive testing cost of various types of chips.
[0052] Based on the chip testing device provided in the above embodiment, the present application may also provide a chip testing system. The chip testing system may include the chip testing device in the above embodiment. It should be noted that the chip testing system in the embodiment of the present application includes the various components of the embodiment of the chip testing device described above and achieves the same effects and functions, which will not be repeated here.
[0053] Based on the chip testing device provided in the above embodiment, the present application can also provide a test system dedicated to a transceiver. The test system dedicated to a transceiver in the present application can include the chip testing device in the above embodiment, and is specifically used to test various chips in the transceiver. It should be noted that the test system dedicated to a transceiver in the embodiment of the present application includes various components of the aforementioned chip testing device embodiment and achieves the same effects and functions, and will not be repeated here.
[0054] Although illustrative embodiments of the present application have been illustrated and described in detail in the drawings and foregoing description, they should be considered illustrative and not restrictive, and it should be understood that only certain exemplary embodiments have been shown and described and that all changes and modifications that come within the spirit of the claimed invention are intended to be protected. It should be understood that although words such as preferred, preferred, preferred, or more preferred are used in the above description to indicate that the features so described may be more desirable, they may not be required and implementations without these features are contemplated within the scope of the present invention, which scope is defined by the appended claims. When reading the claims, when words such as "a," "an," "at least one," or "at least one portion" are used, it is not intended to limit the claim to only one item unless specifically stated to the contrary in the claim. When the language "at least a portion" and / or "a portion" is used, the item may include a portion and / or the entire item unless specifically stated to the contrary.
[0055] Although the spirit and principles of the present application have been described above with reference to several specific embodiments, it should be understood that the present application is not limited to the specific embodiments disclosed, and the division into various aspects does not mean that the features of these aspects cannot be combined. The present application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims
1. A chip testing device, characterized in that: include: A test board, an expansion board connected to the test board, and power supply interfaces of various voltages; The expansion board is used to connect different types of chips to be tested; A test platform is built on the test board, and the test platform is compatible with multiple communications; The power supply interfaces with multiple voltages are used to supply power to different types of chips to be tested.
2. The device according to claim 1, characterized in that The test plate is arranged in a high and low temperature box.
3. The device according to claim 1, characterized in that The device further includes: a status indicator, the status indicator being communicatively connected to the test board; The status indicator is used to indicate the communication status between the test board and the chip to be tested.
4. The device according to claim 1, characterized in that The test board is provided with an analog-to-digital converter port, and the analog-to-digital converter port is used to output voltage and current data of the chip to be tested.
5. The device according to claim 4, characterized in that The device also includes a display screen; The analog-to-digital converter port of the test board is connected to the display screen, and the display screen is used to display the voltage and current data of the chip to be tested.
6. The device according to claim 1, characterized in that The chip to be tested is placed in a high and low temperature box; The number of chips to be tested that are simultaneously connected to the device is determined by the volume of the high and low temperature chamber.
7. The device according to claim 1, characterized in that The test board is a microcontroller unit MCU; The expansion board is configured as a test unit or a test function module DUT connected to the microcontroller unit MCU.
8. The device according to claim 1, characterized in that The test platform is compatible with serial peripheral interface communication SPI and inter-integrated circuit communication IIC.
9. A chip testing system, characterized in that: The chip testing system includes the chip testing device according to any one of claims 1-8.
10. A transceiver testing system, characterized in that: It is specially used for transceiver testing, and the testing system includes the chip testing device according to any one of claims 1-8.