Packaging structure and chip

Abstract

The utility model discloses a packaging structure and a chip, the packaging structure comprises a substrate, the substrate comprises a first surface and a second surface which are oppositely arranged, and a through hole is formed in the substrate; the welding pad is located on the second surface of the substrate and covers the through hole; the first insulating layer covers the first surface of the substrate, the side wall of the through hole and the surface of the welding pad; the second insulating layer covers the first insulating layer above part of the side wall of the through hole; the third insulating layer covers the first insulating layer above part of the side wall of the through hole, and the third insulating layer and the second insulating layer are arranged at an interval; and the metal layer covers the second insulating layer and the third insulating layer and is in contact with the welding pad. According to the utility model, the second insulating layer and the third insulating layer are arranged on the first insulating layer above the side wall of the through hole at intervals, so that the stress effect of the whole-section insulating dielectric layer on the contact position of the metal layer and the welding pad is reduced, the first insulating layer at the stress concentration position is effectively protected, and the reliability of the packaging structure is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor packaging, and in particular relates to a packaging structure and a chip. Background Art

[0002] As the integration of CMOS products continues to increase, the single-layer insulation layer packaging process is gradually unable to meet the needs of the products. The use of a double-insulation layer packaging process, coating a photoresist layer on the first insulation layer as the second insulation layer can alleviate the stress concentration in the first insulation layer and achieve a better packaging effect.

[0003] The packaging structures in the existing technology include a full-hole photoresist layer glue type structure and a half-hole photoresist layer glue type structure. The full-hole photoresist layer glue type packaging structure exerts a large stress pull on the bottom of the TSV hole, which can easily cause the metal layer at the bottom of the hole to be delaminated from the welding pad, affecting the conduction of the circuit; the half-hole photoresist layer glue type packaging structure has a thin insulating layer at the bottom of the hole and is prone to stress concentration at the corner position, which can easily cause damage to the insulating layer at the corner, resulting in conduction between the metal layer and the substrate, forming a short circuit.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a packaging structure and a chip. Utility Model Content

[0005] The purpose of the utility model is to provide a packaging structure and a chip.

[0006] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0007] A packaging structure, comprising:

[0008] a substrate, the substrate comprising a first surface and a second surface opposite to each other, wherein a through hole is formed in the substrate and passes through the first surface and the second surface;

[0009] a soldering pad, located on the second surface of the substrate and covering the through hole;

[0010] a first insulating layer covering all or part of the first surface of the substrate, the sidewalls of the through hole, and part of the surface of the pad;

[0011] a second insulating layer covering the first insulating layer above a portion of the sidewall of the through hole and extending above the first insulating layer above the first surface of the substrate;

[0012] a third insulating layer covering the first insulating layer above a portion of the sidewall of the through hole and extending to the first insulating layer above the pad, wherein the third insulating layer and the second insulating layer are spaced apart from each other and disposed above the first insulating layer above the sidewall of the through hole;

[0013] A metal layer covers all or part of the second insulating layer and all or part of the third insulating layer, the metal layer contacts the first insulating layer at a position between the second insulating layer and the third insulating layer, and the metal layer contacts the solder pad under the through hole.

[0014] In one embodiment, the through hole includes a first side wall and a second side wall connected to each other, the first side wall is arranged adjacent to the first surface of the substrate, the second side wall is arranged adjacent to the second surface of the substrate, and the angle between the first side wall and the first surface of the substrate is greater than the angle between the second side wall and the second surface of the substrate.

[0015] In one embodiment, the first side wall is connected to the first surface, and the second side wall is connected to the second surface.

[0016] In one embodiment, the gap between the second insulating layer and the third insulating layer is located above the second sidewall and adjacent to the connection between the first sidewall and the second sidewall; or,

[0017] Located above the first side wall and adjacent to the junction of the first side wall and the second side wall; or,

[0018] The first side wall and the second side wall are located beside the connection.

[0019] In one embodiment, the thickness of the second insulating layer first increases and then decreases downward along the first sidewall, and the thickness of the third insulating layer gradually increases downward along the second sidewall.

[0020] In one embodiment, the first insulating layer is an inorganic thin film layer or an organic polymer layer.

[0021] In one embodiment, the second insulating layer and the third insulating layer are photosensitive layers.

[0022] In one embodiment, the thickness of the first insulating layer of the substrate at the gap is less than or equal to the thickness of the first insulating layer above the gap or below the gap.

[0023] Another embodiment of the present invention provides the following technical solutions:

[0024] A chip comprises the above-mentioned packaging structure.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The utility model arranges a second insulating layer and a third insulating layer on the first insulating layer above the side wall of the through hole, thereby reducing the stress of the entire insulating medium layer on the contact position between the metal layer and the welding pad, and at the same time can effectively protect the first insulating layer at the position where stress concentration is prone to occur, thereby improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a schematic diagram of the packaging structure in Comparative Example 1 of the present invention;

[0029] Figure 2 This is a schematic diagram of the packaging structure in Comparative Example 2 of the present invention;

[0030] Figure 3 This is a schematic diagram of the packaging structure in Example 1 of the present utility model;

[0031] Figures 4a to 4f This is a process flow chart of the packaging method in Example 1 of the present utility model.

[0032] Description of main reference numerals:

[0033] 10 - substrate, 10a - first surface, 10b - second surface, 20 - pad, 30 - through hole, 30a - first sidewall, 30b - second sidewall, 401 - first insulating layer, 402 - second insulating layer, 403 - third insulating layer, 50 - metal layer. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the following will be combined with the drawings of the embodiments of the present invention to clearly and completely describe the technical solutions of the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] The utility model discloses a packaging structure, comprising:

[0036] A substrate comprising a first surface and a second surface opposite to each other, wherein a through hole is formed in the substrate and passes through the first surface and the second surface;

[0037] a solder pad located on the second surface of the substrate and covering the through hole;

[0038] a first insulating layer covering all or part of the first surface of the substrate, the sidewalls of the through hole, and part of the surface of the pad;

[0039] a second insulating layer covering the first insulating layer above a portion of the sidewall of the through hole and extending above the first insulating layer above the first surface of the substrate;

[0040] a third insulating layer covering the first insulating layer above a portion of the sidewall of the through hole and extending to the first insulating layer above the pad, the third insulating layer and the second insulating layer being spaced apart from each other on the first insulating layer above the sidewall of the through hole;

[0041] The metal layer covers all or part of the second insulating layer and all or part of the third insulating layer. The metal layer contacts the first insulating layer between the second insulating layer and the third insulating layer, and contacts the solder pad under the through hole.

[0042] The utility model also discloses a chip, comprising the above packaging structure.

[0043] Comparative Example 1:

[0044] Ginseng Figure 1 As shown, the packaging structure in this comparative example includes:

[0045] A substrate 10, comprising a first surface 10a and a second surface 10b opposite to each other, wherein a through hole 30 is formed in the substrate 10 and passes through the first surface 10a and the second surface 10b;

[0046] The solder pad 20 is located on the second surface 10 b of the substrate 10 and covers the through hole 30 ;

[0047] A first insulating layer 401 covers all or part of the first surface 10 a of the substrate 10 , the sidewalls of the through hole 30 , and part of the surface of the pad 20 ;

[0048] A second insulating layer 402 covering the first insulating layer 401 above the sidewall of the through hole 30 and extending to the first insulating layer 401 above the first surface 10 a of the substrate 10 ;

[0049] The metal layer 50 covers the second insulating layer 402 and contacts the bonding pad 20 below the through hole 30 .

[0050] The packaging structure in this comparative example is a packaging structure in the prior art in which the through hole 30 is completely covered with the second insulating layer 402. The second insulating layer 402 extends downward along the sidewall of the through hole 30 ( Figure 1The direction indicated by the arrow in the middle (indicated by the direction indicated by the arrow in the middle) first increases, then decreases, and then increases again. The second insulating layer 402 is continuously provided on the first insulating layer 301 on the sidewall. The metal layer 50 covers the second insulating layer 402 and contacts the bonding pad 20. In this package structure, due to the contraction and expansion of the material, the metal layer 50 and the bonding pad 20 in the through hole 30 are subjected to significant stress. In particular, stress concentration occurs at the contact point between the metal layer 50 and the bonding pad 20, causing delamination between the metal layer 50 and the bonding pad 20, which may cause a short circuit during chip use.

[0051] Comparative Example 2:

[0052] Ginseng Figure 2 As shown, the packaging structure in this comparative example includes:

[0053] A substrate 10, comprising a first surface 10a and a second surface 10b opposite to each other, wherein a through hole 30 is formed in the substrate 10 and passes through the first surface 10a and the second surface 10b;

[0054] The pad 20 is located on the second surface 10 b of the substrate 10 and covers the through hole 30 ;

[0055] A first insulating layer 401 covers all or part of the first surface 10 a of the substrate 10 , the sidewalls of the through hole 30 , and part of the surface of the pad 20 ;

[0056] A second insulating layer 402 covering the first insulating layer 401 above a portion of the sidewall of the through hole 30 and extending to the first insulating layer 401 above the first surface 10 a of the substrate 10 ;

[0057] The metal layer 50 covers the second insulating layer 402 , and the metal layer 50 contacts the first insulating layer 401 not covered by the second insulating layer 402 . The metal layer 50 contacts the pad 20 below the through hole.

[0058] The package structure in this comparative example is a conventional package structure in which a second insulating layer 402 covers half of the through-hole 30. The second insulating layer 402 only covers the first insulating layer 401 on a portion of the sidewalls and extends to the first insulating layer 401 above the first surface of the substrate 10. The sidewalls of the lower half of the through-hole 30 are covered only with the first insulating layer 401 for protection. The first insulating layer 401 in this package structure is a silicon oxide layer produced by chemical vapor deposition. The thickness of the silicon oxide layer covering the sidewalls of the through-hole 30 gradually decreases with the depth of the through-hole 30. When the through-hole 30 is deep, the silicon oxide layer at the corner where the sidewall of the through-hole 30 connects to the pad 20 is too thin, resulting in a decrease in the insulating capability of the insulating layer. Furthermore, due to stress concentration at the corner, the silicon oxide layer at the corner is prone to cracking, causing the metal layer 50 to connect to the substrate 10 and causing a chip short circuit.

[0059] Example 1:

[0060] Ginseng Figure 3 As shown, the packaging structure in this embodiment includes:

[0061] A substrate 10, comprising a first surface 10a and a second surface 10b opposite to each other, wherein a through hole 30 is formed in the substrate 10 and passes through the first surface 10a and the second surface 10b;

[0062] The pad 20 is located on the second surface 10 b of the substrate 10 and covers the through hole 30 ;

[0063] A first insulating layer 401 covers all or part of the first surface 10 a of the substrate 10 , the sidewalls of the through hole 30 , and part of the surface of the pad 20 ;

[0064] A second insulating layer 402 covering the first insulating layer 401 above a portion of the sidewall of the through hole 30 and extending to the first insulating layer 401 above the first surface 10 a of the substrate 10 ;

[0065] A third insulating layer 403 covers the first insulating layer 401 above a portion of the sidewall of the through hole 30 and extends to the first insulating layer 401 above the pad 20. The third insulating layer 403 and the second insulating layer 402 are spaced apart from each other on the first insulating layer 401 above the sidewall of the through hole 30.

[0066] The metal layer 50 covers all or part of the second insulating layer 402 and all or part of the third insulating layer 403. The metal layer 50 contacts the first insulating layer 301 between the second insulating layer 402 and the third insulating layer 403, and the metal layer 50 contacts the solder pad 20 under the through hole.

[0067] The substrate 10 in this embodiment is a silicon substrate, and a through hole 30 penetrating the first surface 10 a and the second surface 10 b is formed in the silicon substrate by TSV technology.

[0068] Furthermore, the through hole 30 includes a first side wall 30a and a second side wall 30b connected to each other, the first side wall 30a is arranged adjacent to the first surface 10a of the substrate 10, and the second side wall 30b is arranged adjacent to the second surface 10b of the substrate 10, and the angle between the first side wall 30a and the first surface 10a of the substrate 10 is greater than the angle between the second side wall 30b and the second surface 10b of the substrate 10.

[0069] Furthermore, the first side wall 30a is connected to the first surface 10a, and the second side wall 30b is connected to the second surface 10b.

[0070] The pad 20 is located on the second surface 10 b of the substrate 10 and covers the through hole 30 .

[0071] For example, a wafer can be used as the substrate 10, on which a plurality of chips arranged in an array are formed. A plurality of bonding pads 20 are distributed on the second surface of the wafer, and the bonding pads 20 serve as input and output terminals for electrically connecting the chips to the outside world.

[0072] In this embodiment, the first insulating layer 401 is an inorganic thin film layer or an organic polymer layer. Preferably, the first insulating layer 401 is a silicon oxide layer.

[0073] Furthermore, the thickness of the first insulating layer 401 at the gap is less than or equal to the thickness of the first insulating layer 401 below the gap.

[0074] In this embodiment, the second insulating layer 402 and the third insulating layer 403 are photosensitive layers. Preferably, the second insulating layer 402 and the third insulating layer 403 are photoresist layers.

[0075] Furthermore, the gap between the second insulating layer 402 and the third insulating layer 403 is located above the second side wall 30 b and adjacent to the connection between the first side wall 30 a and the second side wall 30 b ; or,

[0076] Located above the first side wall 30a and adjacent to the junction of the first side wall 30a and the second side wall 30b; or,

[0077] Above the portion of the first side wall 30a and the second side wall 30b located beside the connection.

[0078] Preferably, the gap is located above the second side wall 30b and adjacent to the connection between the first side wall 30a and the second side wall 30b.

[0079] Furthermore, the thickness of the second insulating layer 402 decreases along the first side wall 30a downwards ( Figure 3 The thickness of the third insulating layer 403 increases first and then decreases along the second side wall 30b downward ( Figure 3 The direction indicated by the arrow in A2 gradually increases.

[0080] The packaging method in this embodiment includes:

[0081] Ginseng Figure 4a As shown, a substrate 10 is provided, which includes a first surface 10a and a second surface 10b arranged opposite to each other. A through hole 30 is formed in the substrate 10 and passes through the first surface 10a and the second surface 10b. A pad 20 covering the through hole 30 is provided on the second surface 10b of the substrate 10.

[0082] Illustratively, a partial area of the substrate 10 is etched sequentially through a first etching process and a second etching process, wherein the ratio of the lateral etching rate to the vertical etching rate in the first etching process is greater than the ratio of the lateral etching rate to the vertical etching rate in the second etching process.

[0083] Illustratively, a photoresist layer is spin-coated on the first surface 10a of the substrate 10, and a patterned photoresist layer is formed on the first surface 10a by a photolithography process. The substrate 10 is first etched by a first etching process using the photoresist layer as a mask to form a first sidewall 30a connected to the first surface 10a of the substrate 10. Then, the etching process is adjusted to reduce the ratio of the lateral etching rate to the vertical etching rate to increase the steepness of the etching process. The substrate 10 is etched by a second etching process using the photoresist layer as a mask to form a second sidewall 30b connected to the second surface 10b of the substrate 10. After the etching is completed, the angle between the first sidewall 30a of the through hole 30 and the first surface 10a of the substrate 10 is greater than the angle between the second sidewall 30b and the second surface 10b of the substrate 10.

[0084] Ginseng Figure 4b As shown, a first insulating layer 401 is formed on all or part of the first surface 10 a of the substrate 10 and the sidewalls and bottom wall of the through hole 30 .

[0085] Illustratively, the first insulating layer 401 in this embodiment is a silicon oxide layer, which is formed on all or part of the first surface 10 a of the substrate 10 and the sidewalls and bottom wall of the through hole 30 by a chemical vapor deposition process.

[0086] An insulating dielectric layer is formed on the first insulating layer 401 .

[0087] The insulating dielectric layer in this embodiment is a photosensitive layer.

[0088] Specifically, refer to Figure 4c As shown, a photosensitive layer is prepared on the surface of the first insulating layer 401 by a coating process, and the thickness of the photosensitive layer coated on the first insulating layer 401 on the side wall of the through hole 30 first increases, then decreases, and then increases again downward along the side wall of the through hole 30.

[0089] Specifically, the photosensitive layer in this embodiment is a photoresist layer. The photoresist layer can serve as a mask layer when etching the first insulating layer 401 , and can also serve as an insulating layer to play a role of isolation and protection.

[0090] In this embodiment, a through hole 30 having a connected first side wall 30a and a second side wall 30b is formed by a two-step etching process. The angle between the first side wall 30a and the first surface 10a of the substrate 10 is greater than the angle between the second side wall 30b and the second surface 10b of the substrate 10. The through hole 30 is Y-shaped, so that the coated photoresist layer can be unevenly distributed on the first insulating layer 401 on the side wall of the through hole 30. In this embodiment, the thinnest position of the insulating layer is located above the second side wall 30b and adjacent to the connection between the first side wall 30a and the second side wall 30b.

[0091] Ginseng Figure 4d As shown, the insulating dielectric layer on a portion of the surface of the bonding pad 20 at the bottom of the through hole 30 is removed.

[0092] Specifically, the insulating dielectric layer in this embodiment is a photoresist layer, which is directly exposed and developed to form a patterned photoresist layer, exposing the first insulating layer 401 to be etched.

[0093] Ginseng Figure 4e As shown, the first insulating layer 401 on the surface of the pad 20 at the bottom of the through hole 30 is etched, and the insulating dielectric layer is thinned to form a second insulating layer 402 and a third insulating layer 403 spaced apart from each other on the first insulating layer 401 above the sidewall of the through hole 30 .

[0094] Specifically, the first insulating layer 401 is etched through an etching process to open the welding pad 20 so as to prepare a metal layer 50 in contact with the welding pad 20. At the same time, the etching process will also etch the photoresist layer on the first insulating layer 401 to thin the photoresist layer. After the etching is completed, the side walls and bottom walls of the through hole are oxygen cleaned. The oxygen plasma can react with the photoresist layer to further thin the photoresist layer, and the oxygen cleaning process can remove organic pollutants remaining on the welding pad 20 during the etching process.

[0095] In the actual etching process, it is impossible to accurately control the time it takes to etch the first insulating layer 401 on the pad 20 clean. Therefore, in order to ensure good contact between the subsequent metal layer and the pad, appropriate over-etching will be performed to ensure that the first insulating layer 401 on the pad 20 is etched clean.

[0096] It should be understood that since it is impossible to accurately control the etching amount of the photoresist layer during the etching and oxygen cleaning processes, and the photoresist layer is unevenly distributed on the first insulating layer on the side wall of the through hole 30, the photoresist layer will be gradually etched during the etching and oxygen cleaning processes. In this process, part of the first insulating layer 401 on the side wall of the through hole 30 will inevitably be etched to a certain extent. However, as long as the first insulating layer 401 is not etched through to the side wall of the through hole 30, it will not affect the packaging structure in this embodiment.

[0097] Ginseng Figure 4fAs shown, a metal layer 50 is formed on all or part of the first surface 10 a of the substrate 10 and the sidewalls and bottom wall of the through hole 30 .

[0098] Specifically, the metal layer 50 covers all or part of the second insulating layer 402 and all or part of the third insulating layer 403 , contacts the first insulating layer 401 between the second insulating layer 402 and the third insulating layer 403 , and contacts the pad 20 under the through hole 30 .

[0099] The chip in this embodiment includes the above-mentioned packaging structure or is packaged by the above-mentioned packaging method.

[0100] The chip also includes other arbitrary structures for realizing special functions, which will not be described in detail here.

[0101] It can be seen from the above scheme that the utility model has the following beneficial effects:

[0102] The utility model arranges a second insulating layer and a third insulating layer on the first insulating layer above the side wall of the through hole, thereby reducing the stress of the entire insulating medium layer on the contact position between the metal layer and the welding pad, and at the same time can effectively protect the first insulating layer at the position where stress concentration is prone to occur, thereby improving the reliability of the packaging structure.

[0103] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed within the present invention. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0104] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: a substrate, the substrate comprising a first surface and a second surface opposite to each other, wherein a through hole is formed in the substrate and passes through the first surface and the second surface; a soldering pad, located on the second surface of the substrate and covering the through hole; a first insulating layer covering all or part of the first surface of the substrate, the sidewalls of the through hole, and part of the surface of the pad; a second insulating layer covering the first insulating layer above a portion of the sidewall of the through hole and extending above the first insulating layer above the first surface of the substrate; a third insulating layer covering the first insulating layer above a portion of the sidewall of the through hole and extending to the first insulating layer above the pad, wherein the third insulating layer and the second insulating layer are spaced apart from each other and disposed above the first insulating layer above the sidewall of the through hole; A metal layer covers all or part of the second insulating layer and all or part of the third insulating layer, the metal layer contacts the first insulating layer at a position between the second insulating layer and the third insulating layer, and the metal layer contacts the solder pad under the through hole.

2. The packaging structure according to claim 1, wherein: The through hole includes a first side wall and a second side wall connected to each other, the first side wall is arranged adjacent to the first surface of the substrate, the second side wall is arranged adjacent to the second surface of the substrate, and the angle between the first side wall and the first surface of the substrate is greater than the angle between the second side wall and the second surface of the substrate.

3. The packaging structure according to claim 2, wherein: The first side wall is connected to the first surface, and the second side wall is connected to the second surface.

4. The packaging structure according to claim 2, wherein: The gap between the second insulating layer and the third insulating layer is located above the second side wall and adjacent to the connection between the first side wall and the second side wall; or, Located above the first side wall and adjacent to the junction of the first side wall and the second side wall; or, The first side wall and the second side wall are located beside the connection.

5. The packaging structure according to claim 2, wherein: The thickness of the second insulating layer first increases and then decreases downward along the first side wall, and the thickness of the third insulating layer gradually increases downward along the second side wall.

6. The packaging structure according to claim 1, wherein: The first insulating layer is an inorganic thin film layer or an organic polymer layer.

7. The packaging structure according to claim 1, wherein: The second insulating layer and the third insulating layer are photosensitive layers.

8. The packaging structure according to claim 1, wherein: The thickness of the first insulating layer at the interval is less than or equal to the thickness of the first insulating layer above the interval or below the interval.

9. A chip, characterized in that: The chip includes the package structure according to any one of claims 1 to 8.

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