Pixel and display device

Abstract

The utility model discloses a pixel and a display device. The pixel includes: a capacitor connected between a first power supply voltage line and a first node; a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node; a second transistor including a gate electrode receiving a scan signal, a first terminal connected to a data line, and a second terminal connected to a second node; a third transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to an initialization voltage line, and a second terminal connected to the first node; and a light emitting element including an anode connected to the third node and a cathode connected to a line conveying a second power supply voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, and more particularly, to a pixel and a display device including the pixel. Background Art

[0002] Due to process variations, degradation, etc., the driving transistors of the pixels of a display device (such as an organic light emitting diode (OLED) display device) may have different threshold voltages. Due to this change in threshold voltage, the pixels of the display device may not emit light with consistent brightness. In order to prevent or reduce brightness inconsistency, a pixel for performing a compensation operation to compensate for the threshold voltage of the driving transistor has been developed. For example, in order to perform a compensation operation in a diode connection method, the pixel can be connected to the driving transistor in a diode manner, and the data voltage can be transmitted to the gate node of the driving transistor through the driving transistor connected in a diode manner. Therefore, in the pixel, the data voltage in which the threshold voltage of the driving transistor is compensated can be applied to the gate node.

[0003] In a pixel performing a compensation operation in a diode connection method, before a data voltage is applied to the gate node, the gate node may be initialized to an initialization voltage lower than the data voltage. The pixel may receive an initialization signal to provide the initialization voltage to the gate node. Utility Model Content

[0004] Some embodiments provide a pixel that performs compensation operations without using an initialization signal.

[0005] Some embodiments provide a display device that performs a compensation operation without using an initialization signal.

[0006] According to an embodiment, a pixel includes: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to a data line, and a second terminal connected to the second node; a third transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; and a light-emitting element including an anode connected to the third node and a cathode connected to a line transmitting a second power supply voltage.

[0007] In an embodiment, the fourth transistor may be turned on in response to a reference voltage transmitted to the second node through the data line and the second transistor.

[0008] In an embodiment, the initialization voltage may be higher than the reference voltage.

[0009] In an embodiment, the fourth transistor may be turned off in response to a data voltage transmitted to the second node through the data line and the second transistor.

[0010] In an embodiment, the initialization voltage may be lower than the data voltage.

[0011] In an embodiment, the pixel may further include: a fifth transistor connected between a line transmitting the first power supply voltage and the second node, wherein the fifth transistor can receive an emission signal; and a sixth transistor connected between the third node and the anode of the light-emitting element, wherein the sixth transistor can receive an emission signal.

[0012] In an embodiment, the fifth transistor may include a gate receiving an emission signal, a first terminal connected to a line transmitting a first power supply voltage, and a second terminal connected to a second node, and the sixth transistor may include a gate receiving an emission signal, a first terminal connected to a third node, and a second terminal connected to an anode of the light emitting element.

[0013] In an embodiment, the first to sixth transistors may be P-type metal oxide semiconductor (PMOS) transistors.

[0014] In an embodiment, a frame period for a pixel may include an initialization period for initializing the first node and the third node, a data writing and compensation period for supplying a data voltage through a data line, and an emission period for emitting light from a light emitting element.

[0015] In an embodiment, during the initialization period, the scan signal may have a first level, the emission signal may have a second level, the reference voltage may be provided through the data line, the second transistor may transmit the reference voltage of the data line to the second node in response to the scan signal having the first level, the fourth transistor may transmit the initialization voltage to the first node in response to the reference voltage of the second node, the third transistor may transmit the initialization voltage of the first node to the third node in response to the scan signal having the first level, and the first node and the third node may be initialized based on the initialization voltage.

[0016] In an embodiment, in a data write and compensation period, the scan signal may have a first level, the emission signal may have a second level, the data voltage may be provided through the data line, the second transistor may transmit the data voltage of the data line to the second node in response to the scan signal having the first level, the third transistor may be diode-connected to the first transistor in response to the scan signal having the first level, and a voltage obtained by subtracting the threshold voltage of the first transistor from the data voltage may be applied to the first node through the first transistor connected in a diode manner.

[0017] In an embodiment, in an emission period, the scan signal may have a second level, the emission signal may have a first level, the fifth transistor and the sixth transistor may be turned on in response to the emission signal having the first level, the first transistor may generate a driving current based on the voltage of the first node, and the light-emitting element may emit light based on the driving current.

[0018] In an embodiment, the pixel may further include a seventh transistor configured to transmit an anode initialization voltage to the anode of the light emitting element in response to the scan signal.

[0019] In an embodiment, the seventh transistor may include a gate receiving a scan signal, a first terminal connected to a line transmitting an anode initialization voltage, and a second terminal connected to an anode of the light emitting element.

[0020] In an embodiment, the anode initialization voltage may be substantially the same as the initialization voltage.

[0021] In an embodiment, the anode initialization voltage may be different from the initialization voltage.

[0022] According to an embodiment, a pixel includes: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node; a second transistor including a gate receiving a scan signal, a first terminal connected to a data line, and a second terminal connected to the second node; a third transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving an emission signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving an emission signal, a first terminal connected to the third node, and a second terminal; and a light-emitting element including an anode connected to the second terminal of the sixth transistor and a cathode connected to the line transmitting the second power supply voltage.

[0023] In an embodiment, the pixel may further include a seventh transistor including a gate receiving a scan signal, a first terminal connected to a line transmitting an anode initialization voltage, and a second terminal connected to an anode of the light emitting element.

[0024] According to an embodiment, a display device includes: a display panel including a plurality of pixels; a data driver connected to each of the plurality of pixels via a data line; and a scan driver providing a scan signal to each of the plurality of pixels. Each of the plurality of pixels includes: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; and a light-emitting element including an anode connected to the third node and a cathode connected to a line transmitting a second power supply voltage.

[0025] In an embodiment, when a scan signal is applied and a reference voltage is supplied to the data line, the fourth transistor may be turned on in response to the reference voltage transmitted to the second node through the data line and the second transistor. When a scan signal is applied and a data voltage is supplied to the data line, the fourth transistor may be turned off in response to the data voltage transmitted to the second node through the data line and the second transistor.

[0026] As described above, in the pixel according to the embodiment, the gate of the fourth transistor can be connected to the second node. In such an embodiment, the fourth transistor can be turned on in response to the reference voltage applied to the second node through the data line and the second transistor, and can be turned off in response to the data voltage applied to the second node through the data line and the second transistor. Therefore, the pixel according to the embodiment can be implemented without using a separate signal (e.g., an initialization signal) for turning on or off the fourth transistor, and the number of signal lines of the display device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a circuit diagram showing a pixel according to an embodiment.

[0029] Figure 2 is a signal timing diagram illustrating an example of the operation of a pixel according to the embodiment.

[0030] Figure 3 is a circuit diagram illustrating the operation of a pixel in an initialization period.

[0031] Figure 4is a circuit diagram illustrating the operation of a pixel in a data writing and compensation period.

[0032] Figure 5 is a circuit diagram illustrating the operation of a pixel during an emission period.

[0033] Figure 6 is a circuit diagram showing a pixel according to an embodiment.

[0034] Figure 7 is a block diagram illustrating a display device according to an embodiment.

[0035] Figure 8 is a signal timing chart showing an example of the operation of the display device according to the embodiment.

[0036] Figure 9 is a block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0037] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0038] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements can be present between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0039] It will be understood that although the terms "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the spirit and scope of the present disclosure, the "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second element, component, region, layer, or section.

[0040] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be restrictive. Unless the context clearly states otherwise, as used herein, "one", "one (kind / person)", "described (should)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, in the claims, the reference to "one (kind / person)" element followed by the reference to "described (should)" element includes one element and multiple elements. For example, unless the context clearly states otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related enumerated items. It will also be understood that the terms “comprises and / or comprising” or “includes and / or including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or combinations thereof.

[0041] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device is turned over in one drawing, the element described as being on the "lower" side of the other elements will subsequently be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawing, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one drawing, the element described as being "below" or "below" the other elements will subsequently be oriented to be "above" the other elements. Therefore, the terms "below..." or "below..." can cover both "upper" and "lower" orientations.

[0042] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0044] Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the present disclosure.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a circuit diagram showing a pixel according to an embodiment.

[0047] Reference Figure 1 According to an embodiment, the pixel 100 may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a light emitting element EL. In some embodiments, the pixel 100 may further include additional transistors, for example, a fifth transistor T5 and a sixth transistor T6.

[0048] In an embodiment, the capacitor CST may be connected between a line transmitting a first power supply voltage ELVDD (e.g., a high power supply voltage) and a first node N1. The first node N1 may be a gate node connected to a gate (e.g., a gate terminal) of the first transistor T1. In some embodiments, the capacitor CST may also be referred to as a storage capacitor for storing a data voltage. In an embodiment, the capacitor CST may include a first electrode connected to a line transmitting the first power supply voltage ELVDD and a second electrode connected to the first node N1.

[0049] The first transistor T1 may generate a driving current based on the voltage of the first node N1. In an embodiment, the first transistor T1 may be referred to as a driving transistor for driving the light emitting element EL. In an embodiment, the first transistor T1 may include a gate connected to the first node N1, a first terminal (e.g., a source) connected to the second node N2, and a second terminal (e.g., a drain) connected to the third node N3.

[0050] The second transistor T2 may connect the data line DL to the second node N2 in response to the scan signal GW. The second node N2 may be a source node connected to the source of the first transistor T1. In an embodiment, the second transistor T2 may be referred to as a scan transistor or a switching transistor that transmits the voltage of the data line DL to the second node N2. In an embodiment, the second transistor T2 may include a gate that receives the scan signal GW, a first terminal connected to the data line DL, and a second terminal connected to the second node N2.

[0051] The third transistor T3 may connect the first node N1 and the third node N3 to each other in response to the scan signal GW. The third node N3 may be a drain node connected to the drain of the first transistor T1. In an embodiment, the gate node and the drain node are connected to each other via the third transistor T3, and therefore the first transistor T1 may be diode-connected or diode-connected. In an embodiment, the third transistor T3 may be referred to as a compensation transistor for connecting the first transistor T1 in a diode manner (i.e., connecting the first transistor T1 in a diode form). In an embodiment, the third transistor T3 may include a gate receiving the scan signal GW, a first terminal connected to the third node N3, and a second terminal connected to the first node N1.

[0052] The fourth transistor T4 may transmit the initialization voltage VINT to the first node N1 in response to the voltage of the second node N2. In an embodiment, the fourth transistor T4 may be referred to as an initialization transistor for providing the initialization voltage VINT to the first node N1 (or gate node). In an embodiment, the fourth transistor T4 may include a gate connected to the second node N2, a first terminal connected to a line transmitting the initialization voltage VINT, and a second terminal connected to the first node N1.

[0053] The fifth transistor T5 may be connected between a line transmitting the first power supply voltage ELVDD and the second node N2, and the sixth transistor T6 may be connected between the third node N3 and the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 may receive the same emission signal EM. In response to the emission signal EM, the fifth transistor T5 may connect the line transmitting the first power supply voltage ELVDD and the second node N2, and the sixth transistor T6 may connect the third node N3 and the anode of the light-emitting element EL. In an embodiment, the fifth transistor T5 and the sixth transistor T6 may be referred to as emission transistors, and are used to form a path for a driving current from the line transmitting the first power supply voltage ELVDD to the line transmitting the second power supply voltage ELVSS (e.g., a low power supply voltage). In an embodiment, the fifth transistor T5 may include a gate for receiving the emission signal EM, a first terminal connected to the line transmitting the first power supply voltage ELVDD, and a second terminal connected to the second node N2. The sixth transistor T6 may include a gate for receiving the emission signal EM, a first terminal connected to the third node N3, and a second terminal connected to the anode of the light-emitting element EL.

[0054] The light emitting element EL may emit light in response to the driving current generated by the first transistor T1. In an embodiment, the light emitting element EL may be an organic light emitting diode (OLED), but is not limited thereto. In another embodiment, for example, the light emitting element EL may be a nano-light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element. In an embodiment, the light emitting element EL may include an anode connected to the third node N3 through the sixth transistor T6 and a cathode connected to a line transmitting the second power supply voltage ELVSS.

[0055] In some embodiments, as Figure 1 As shown in FIG, the first to sixth transistors T1 to T6 of the pixel 100 may be implemented as P-type metal oxide semiconductor (PMOS) transistors, but are not limited thereto. In other embodiments, at least a portion of the first to sixth transistors T1 to T6 may be implemented as N-type metal oxide semiconductor (NMOS) transistors.

[0056] As described above, in the pixel 100 of the display device according to the embodiment, the gate of the fourth transistor T4 can be connected to the second node N2. Therefore, the fourth transistor T4 may not receive a separate signal (e.g., an initialization signal) and may be turned on or off in response to the voltage of the second node N2. In some embodiments, the fourth transistor T4 may be turned on in response to a reference voltage applied to the second node N2 through the data line DL and the second transistor T2, and may be turned off in response to a data voltage applied to the second node N2 through the data line DL and the second transistor T2. Therefore, the pixel 100 according to the embodiment can be implemented without using a separate signal (e.g., an initialization signal) for turning on or off the fourth transistor T4, and the number of signal lines of the display device including the pixel 100 can be reduced.

[0057] In the following, reference will be made to Figures 1 to 5 The operation of the pixel 100 according to the embodiment is described.

[0058] Figure 2 is a signal timing diagram showing an example of the operation of a pixel according to an embodiment; Figure 3 is a circuit diagram showing the operation of a pixel in an initialization period; Figure 4 is a circuit diagram illustrating the operation of a pixel in a data writing and compensation period; and Figure 5 is a circuit diagram illustrating the operation of a pixel during an emission period.

[0059] Reference Figure 1 and Figure 2 , the frame period FP for the pixel 100 may include an initialization period INIP in which the first node N1 and the third node N3 are initialized, a data writing and compensation period DWCP in which the data voltage VDAT is supplied through the data line DL, and an emission period EMP in which the light emitting element EL emits light.

[0060] In the initialization period INIP, the scan signal GW may have a first level, the emission signal EM may have a second level, and the reference voltage VREF may be provided through the data line DL. In some embodiments, the first level may be an active level for turning on each transistor, and the second level may be an inactive level for turning off each transistor. In an embodiment, for example, Figure 2 As shown in , the first level may be a low level, and the second level may be a high level. Figure 3As shown in FIG, in the initialization period INIP, the fifth transistor T5 and the sixth transistor T6 may be turned off in response to the emission signal EM having a second level. The second transistor T2 may be turned on in response to the scan signal GW having a first level and may transmit the reference voltage VREF of the data line DL to the second node N2. The fourth transistor T4 may be turned on in response to the reference voltage VREF transmitted to the second node N2 through the data line DL and the second transistor T2. In some embodiments, in order to turn on the fourth transistor T4, the reference voltage VREF applied to the gate of the fourth transistor T4 may be lower than the initialization voltage VINT applied to one terminal (e.g., source) of the fourth transistor T4. That is, the initialization voltage VINT and the reference voltage VREF may be set in a manner such that the initialization voltage VINT is higher than the reference voltage VREF. In an embodiment, for example, the initialization voltage VINT may be approximately 3 volts (V) and the reference voltage VREF may be approximately 0V. However, the initialization voltage VINT and the reference voltage VREF are not limited thereto.

[0061] Reference Figure 2 and Figure 3 In the initialization period INIP, the fourth transistor T4 turned on in response to the reference voltage VREF at the second node N2 can transmit the initialization voltage VINT to the first node N1. Since the initialization voltage VINT applied to the first node N1 is higher than the reference voltage VREF applied to the second node N2, the first transistor T1 can be turned off. In addition, the third transistor T3 can be turned on in response to the scan signal GW having a first level and can transmit the initialization voltage VINT at the first node N1 to the third node N3. Therefore, the first node N1 and the third node N3 can be initialized based on the initialization voltage VINT. Since the first node N1 (e.g., the gate node) is initialized to the initialization voltage VINT, the compensation operation in the diode connection method can be performed normally in the data write and compensation period DWCP. In addition, since the third node N3 (e.g., the drain node) is initialized to the initialization voltage VINT, the residual charge remaining at the drain node can be discharged or removed.

[0062] Reference Figure 2 and Figure 4 In the data writing and compensation period DWCP, the scan signal GW may have a first level, the emission signal EM may have a second level, and the data voltage VDAT may be provided through the data line DL. Figure 4As shown in FIG, during the data writing and compensation period DWCP, the fifth transistor T5 and the sixth transistor T6 can be turned off in response to the emission signal EM having a second level. The second transistor T2 can be turned on in response to the scan signal GW having a first level and can transmit the data voltage VDAT of the data line DL to the second node N2. The fourth transistor T4 can be turned off in response to the data voltage VDAT transmitted to the second node N2 through the data line DL and the second transistor T2. In some embodiments, in order to turn off the fourth transistor T4, the data voltage VDAT applied to the gate of the fourth transistor T4 can be higher than the initialization voltage VINT applied to one terminal (e.g., the source) of the fourth transistor T4. That is, the range of the initialization voltage VINT and the data voltage VDAT can be set in such a way that the initialization voltage VINT is lower than the range of the data voltage VDAT, or the initialization voltage VINT is lower than the minimum data voltage (e.g., the data voltage VDAT corresponding to the highest grayscale). In an embodiment, for example, the initialization voltage VINT can be approximately 3V, and the data voltage VDAT can be in the range from approximately 5V to approximately 7V. However, the initialization voltage VINT and the data voltage VDAT are not limited thereto.

[0063] During the data write and compensation period DWCP, the third transistor T3 may be turned on in response to the scan signal GW having a first level and may be diode-connected to the first transistor T1. Since the data voltage VDAT of the second node N2 is applied to the first node N1 via the diode-connected first transistor T1, a voltage (VDAT-VTH) obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the data voltage VDAT may be applied to the first node N1. This operation may be referred to as a compensation operation in a diode connection method. In addition, the storage capacitor CST may store the voltage (VDAT-VTH) at the first node N1.

[0064] Reference Figure 1 、 Figure 2 and Figure 5 , in the emission period EMP, the scan signal GW may have the second level, and the emission signal EM may have the first level. In an embodiment, as Figure 5As shown in FIG, during the emission period EMP, the second transistor T2 and the third transistor T3 may be turned off in response to the scan signal GW having a second level. Furthermore, the fourth transistor T4 may be kept in an off state based on the first power supply voltage ELVDD transmitted to the second node N2 via the fifth transistor T5. The first transistor T1 may generate a drive current IDR based on the voltage of the first node N1 or a voltage (VDAT-VTH) obtained by subtracting a threshold voltage (VTH) from the data voltage VDAT. The fifth transistor T5 may be turned on in response to the emission signal EM having a first level and may connect a line transmitting the first power supply voltage ELVDD to the second node N2. The sixth transistor T6 may be turned on in response to the emission signal EM having a first level and may connect the third node N3 to the anode of the light-emitting element EL. Thus, the fifth transistor T5 and the sixth transistor T6 may form a path for the drive current IDR from the line transmitting the first power supply voltage ELVDD to the line transmitting the second power supply voltage ELVSS. The light-emitting element EL may emit light based on the drive current IDR generated by the first transistor T1.

[0065] As described above, in the pixel 100 of the display device according to the embodiment, since the fourth transistor T4 is turned on and off based on the reference voltage VREF and the data voltage VDAT provided through the data line DL, the display device including the pixel 100 can be implemented without using a separate signal (for example, an initialization signal). That is, the pixel 100 can be driven using only the two signals GW and EM, and the number of signal lines of the display device including the pixel 100 can be reduced.

[0066] Figure 6 is a circuit diagram showing a pixel according to an embodiment.

[0067] Reference Figure 6 According to the embodiment, the pixel 200 may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a light emitting element EL. In addition to the seventh transistor T7, the pixel 200 may also include Figure 6 The pixel 200 may have Figure 1 The pixel 100 has substantially the same configuration and operates substantially the same.

[0068] The seventh transistor T7 can transmit the anode initialization voltage AVINT to the anode of the light emitting element EL in response to the scan signal GW. Figure 2In the initialization period INIP and the data writing and compensation period DWCP shown in FIG, the seventh transistor T7 can provide the anode initialization voltage AVINT to the anode of the light emitting element EL, and can initialize the anode of the light emitting element EL based on the anode initialization voltage AVINT. In some embodiments, the seventh transistor T7 may include a gate receiving the scan signal GW, a first terminal connected to a line transmitting the anode initialization voltage AVINT, and a second terminal connected to the anode of the light emitting element EL.

[0069] In some embodiments, the anode initialization voltage AVINT may be substantially the same as the initialization voltage VINT, and the line transmitting the anode initialization voltage AVINT and the line transmitting the initialization voltage VINT may be the same line. In other embodiments, the anode initialization voltage AVINT may be different from the initialization voltage VINT, and the line transmitting the anode initialization voltage AVINT may be different from the line transmitting the initialization voltage VINT.

[0070] Figure 7 is a block diagram showing a display device according to an embodiment, and Figure 8 is a signal timing chart showing an example of the operation of the display device according to the embodiment.

[0071] Reference Figure 7 According to an embodiment, a display device 600 may include: a display panel 610 including a plurality of pixels PX; a data driver 620 connected to each of the plurality of pixels PX through a data line; a scan driver 630 providing scan signals GW1, GW2, GW3, ... to the plurality of pixels PX; an emission driver 640 providing emission signals EM1, EM2, EM3, ... to the plurality of pixels PX; and a controller 650 controlling the data driver 620, the scan driver 630, and the emission driver 640.

[0072] The display panel 610 may include a plurality of pixels PX. According to an embodiment, each pixel PX of the display panel 610 may be Figure 1 100 pixels or Figure 6 200 of the pixel 200, etc. In each pixel PX, the fourth transistor can be turned on based on the reference voltage VREF provided from the data driver 620 through the data line, and can be turned off based on the data voltage VDAT provided from the data driver 620 through the data line. Therefore, the display device 600 can be implemented without using a separate signal (for example, an initialization signal) for turning on or off the fourth transistor, and the number of signal lines of the display device 600 can be reduced.

[0073] The data driver 620 can generate a reference voltage VREF and a data voltage VDAT based on the output image data ODAT and the data control signal DCTRL received from the controller 650, and can provide the reference voltage VREF and the data voltage VDAT to a plurality of pixels PX. In some embodiments, the data control signal DCTRL may include but is not limited to an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 620 can alternately provide the reference voltage VREF and the data voltage VDAT to each data line. In addition, in each horizontal time, the data driver 620 can sequentially output the reference voltage VREF and the data voltage VDAT to each data line. In an embodiment, for example, Figure 8 As shown in FIG, in a first horizontal time 1H allocated to a first pixel row, the data driver 620 may first output a reference voltage VREF to each data line, and then may output a data voltage VDAT for each pixel PX in the first pixel row to the data line. In such an embodiment, in a second horizontal time allocated to a second pixel row, the data driver 620 may sequentially output the reference voltage VREF and the data voltage VDAT for each pixel PX in the second pixel row to each data line. In such an embodiment, in a third horizontal time allocated to a third pixel row, the data driver 620 may sequentially output the reference voltage VREF and the data voltage VDAT for each pixel PX in the third pixel row to each data line. In some embodiments, the data driver 620 and the controller 650 may be implemented as a single integrated circuit, and this single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 620 and the controller 650 may be implemented as separate integrated circuits.

[0074] The scan driver 630 may provide scan signals GW1, GW2, GW3, ... to the plurality of pixels PX based on the scan control signal SCTRL received from the controller 650. The scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. Figure 8As shown in , the scan driver 630 may sequentially provide scan signals GW1, GW2, GW3, ... to a plurality of pixels PX on a row-by-row basis. In an embodiment, for example, the scan driver 630 may provide a first scan signal GW1 having a first level (e.g., a low level) to a first pixel row, and may then provide a second scan signal GW2 having a first level to a second pixel row. Thereafter, the scan driver 630 may provide a third scan signal GW3 having a first level to a third pixel row. In some embodiments, the scan driver 630 may be integrated or formed in a peripheral area of the display panel 610. In other embodiments, the scan driver 630 may be integrated or formed in a display area of the display panel 610. In other embodiments, the scan driver 630 may be implemented as one or more integrated circuits.

[0075] The emission driver 640 may provide emission signals EM1, EM2, EM3, ... to the plurality of pixels PX based on the emission control signal SCTRL received from the controller 650. The emission control signal EMCTRL may include, but is not limited to, an emission start signal and an emission clock signal. Figure 8 As shown in FIG, the emission driver 640 may sequentially provide emission signals EM1, EM2, EM3, ... to the plurality of pixels PX on a row-by-row basis. In some embodiments, the emission driver 640 may be integrated or formed in a peripheral area of the display panel 610. In other embodiments, the emission driver 640 may be integrated or formed in a display area of the display panel 610. In other embodiments, the emission driver 640 may be implemented as one or more integrated circuits.

[0076] The controller 650 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a master clock signal. The controller 650 may generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and an emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 650 may control the data driver 620 by providing the output image data ODAT and the data control signal DCTRL, control the scan driver 630 by providing the scan control signal SCTRL, and control the emission driver 640 by providing the emission control signal EMCTRL.

[0077] Figure 9is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0078] Reference Figure 9 , an embodiment of the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electrical devices, and the like.

[0079] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 1110 can be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0080] The memory device 1120 may store data used for the operation of the electronic device 1100. In embodiments, for example, the memory device 1120 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile dynamic random access memory (mobile DRAM) device).

[0081] The storage device 1130 may be a solid-state drive (SSD), a hard disk drive (HDD), or a compact disc read-only memory (CD-ROM). The I / O device 1140 may be an input device (such as a keyboard, a keypad, a mouse, a touch screen, etc.) and an output device (such as a printer, a speaker, etc.). The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link.

[0082] In the display device 1160, the gate of the fourth transistor of each pixel can be connected to the second node. In addition, the fourth transistor can be turned on in response to a reference voltage applied to the second node via the data line and the second transistor, and can be turned off in response to a data voltage applied to the second node via the data line and the second transistor. Therefore, the display device 1160 can be implemented without using a separate signal (e.g., an initialization signal) for turning on or off the fourth transistor, and the number of signal lines of the display device 1160 can be reduced.

[0083] Embodiments of the present invention can be applied to any display device 1160 and any electronic device 1100 including the display device 1160, such as smart phones, wearable electronic devices, mobile phones, televisions (TVs) (e.g., digital TVs, three-dimensional (3D) TVs, etc.), personal computers (PCs) (e.g., tablet computers, laptop computers), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, and navigation devices.

[0084] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0085] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A pixel, characterized in that: The pixels include: a capacitor connected between a line transmitting a first power supply voltage and the first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; and The light emitting element includes an anode connected to the third node and a cathode connected to a line transmitting a second power supply voltage.

2. The pixel according to claim 1, wherein A reference voltage lower than the initialization voltage is transmitted to the second node through the data line and the second transistor to turn on the fourth transistor.

3. The pixel according to claim 1, wherein A data voltage higher than the initialization voltage is transmitted to the second node through the data line and the second transistor to turn off the fourth transistor.

4. The pixel according to claim 1, wherein The pixel further comprises: a fifth transistor connected between the line transmitting the first power supply voltage and the second node, wherein the fifth transistor receives a transmission signal; and A sixth transistor is connected between the third node and the anode of the light emitting element, wherein the sixth transistor receives the emission signal.

5. The pixel according to claim 4, wherein: The fifth transistor includes a gate receiving the transmission signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node, and The sixth transistor includes a gate for receiving the emission signal, a first terminal connected to the third node, and a second terminal connected to the anode of the light emitting element.

6. The pixel according to claim 4, wherein: The first to sixth transistors are P-type metal oxide semiconductor transistors.

7. A pixel, characterized in that: The pixels include: a capacitor connected between a line transmitting a first power supply voltage and the first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving a transmission signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving the transmit signal, a first terminal connected to the third node, and a second terminal; and The light emitting element includes an anode connected to the second terminal of the sixth transistor and a cathode connected to a line transmitting a second power supply voltage.

8. A display device, characterized in that: The display device includes: a display panel comprising a plurality of pixels; a data driver connected to each of the plurality of pixels through a data line; and a scan driver configured to provide a scan signal to each of the plurality of pixels, wherein each of the plurality of pixels comprises: a capacitor connected between a line transmitting a first power supply voltage and the first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving the scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; and The light emitting element includes an anode connected to the third node and a cathode connected to a line transmitting a second power supply voltage.

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