Pixel and display device provided with same

Abstract

The utility model relates to a pixel and a display device with the same. The pixel includes: a first transistor having a first electrode turned on to a first node, a second electrode turned on to a second node, and a gate electrode turned on to a third node; a second transistor turned on between the data line and the third node, the gate electrode being electrically connected to the first scan line; a third transistor turned on between a first power supply line supplying a voltage of the first driving power supply and the first node, a gate electrode being electrically connected to the light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; and a light emitting element connected between the second node and the second power supply line.

Description

Technical Field

[0001] The utility model relates to a pixel and a display device equipped with the pixel. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. As a result, the use of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs) has increased.

[0003] Head-mounted display devices (HMDs) are currently under development. These devices enable virtual reality (VR) or augmented reality (AR) experiences, which are displayed by users wearing glasses or helmets and focusing on a view close to their eyes. High-resolution panels are suitable for HMDs, and therefore require pixels that can accommodate these high-resolution panels. Utility Model Content

[0004] An object of the present invention is to provide a pixel applicable to a high-resolution panel and a display device having the same.

[0005] According to an embodiment of the present invention, a pixel includes: a first transistor, a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a data line and the third node, and a gate electrode electrically connected to a first scan line; a third transistor connected between a first power line supplying a voltage of a first driving power supply and the first node, and a gate electrode electrically connected to a light-emitting control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; and a light-emitting element connected between the second node and a second power line supplying a second driving power supply.

[0006] The pixel further includes a fourth transistor, a first electrode of which is connected to the second node, a second electrode of which is electrically connected to a third power line for supplying initialization power, and a gate electrode of which is electrically connected to the second scan line.

[0007] When the voltage of the initialization power source is supplied to the second node, the light emitting element is turned off.

[0008] Each of the first to fourth transistors is a MOSFET including a body electrode.

[0009] Each of the first to fourth transistors is an N-type transistor.

[0010] A ground voltage is supplied to a body electrode of each of the first to fourth transistors.

[0011] A horizontal period includes a first period and a second period. During the first period, the fourth transistor is set to the on state, and the second transistor and the third transistor are set to the off state. During the second period after the first period, the second transistor is set to the on state, and the third transistor and the fourth transistor are set to the off state.

[0012] During the first period and the second period, a voltage of a data signal is supplied to the data line.

[0013] The horizontal period further includes a third period, during which the second transistor and the third transistor are set to an on state, and the fourth transistor is set to an off state.

[0014] According to an embodiment of the present invention, a display device includes: pixels connected to a write scan line, an initialization scan line, a data line, and a light-emitting control line, and the pixels located in the i-th (i is a positive number greater than 0) pixel row and the j-th (j is a positive number greater than 0) pixel column include: a first transistor, a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the j-th data line and the third node in the data lines, and turned on when a first scan signal is supplied to the first scan line in the write scan lines; a third transistor connected between a first power line supplying a voltage of a first driving power source and the first node, and turned on when a light-emitting control signal is supplied to a k-th (k is a positive number greater than 0) light-emitting control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; and a light-emitting element connected between the second node and the second power line supplying a second driving power source.

[0015] The pixel located in the i-th pixel row and the j-th pixel column also includes: a fourth transistor, a first electrode of which is connected to the second node, a second electrode of which is electrically connected to a third power line that supplies initialization power, and is turned on when a second scan signal is supplied to the second scan line.

[0016] Each of the first to fourth transistors is a MOSFET including a body electrode to which a ground voltage is supplied.

[0017] Each of the first to fourth transistors is an N-type transistor.

[0018] According to the pixel and the display device including the same according to the embodiment of the present invention, the pixel can be implemented using a transistor (eg, MOSFET) suitable for high resolution.

[0019] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the concept and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 1 is a diagram illustrating a transistor according to an embodiment of the present invention.

[0021] Figure 2 is a block diagram showing a display device according to an embodiment of the present invention.

[0022] Figure 3 It shows Figure 2 FIG. 1 is a block diagram of an embodiment of a scan driving unit, a data driving unit, and a power supply unit.

[0023] Figure 4 It shows Figure 2 A circuit diagram of an embodiment of a pixel is shown.

[0024] Figure 5 It shows Figure 4 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0025] Figures 6 to 8 It shows that according to Figure 5 Circuit diagram of the pixel working process of the signal.

[0026] Figure 9 It shows Figure 4 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG. DETAILED DESCRIPTION

[0027] Hereinafter, with reference to the accompanying drawings, a plurality of embodiments of the present invention will be described in detail so that a person having ordinary knowledge in the technical field to which the present invention belongs can easily implement the present invention. The present invention can be implemented in various forms and is not limited to the embodiments described below.

[0028] In order to clearly illustrate the present invention, parts that are not related to the description in the drawings are omitted, and similar parts are marked with the same drawing numerals throughout the entire specification.

[0029] Throughout the specification, when any part is "connected" to other parts, it includes not only the case of "direct connection", but also the case of "indirect connection" across other parts. The terms used herein are used to illustrate specific embodiments and are not used to limit the present invention. Throughout the specification, when any part "includes" any constituent element, this means that unless there is a special record to the contrary, other constituent elements may also be included, rather than excluding other constituent elements. "At least any one of X, Y and Z" and "at least any one selected from the group consisting of X, Y and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y and Z (for example, XYZ, XYY, YZ and ZZ). Here, "and / or" includes all combinations of one or more of the corresponding structures.

[0030] Although terms such as "first" and "second" are used herein to describe various components, these components are not limited by these terms. These terms are used solely to distinguish one component from the others. Therefore, the first component mentioned below may also be the second component within the technical concept of the present invention.

[0031] Figure 1 FIG. 1 is a diagram illustrating a transistor according to an embodiment of the present invention.

[0032] Reference Figure 1 According to one embodiment of the present invention, a transistor 1 may include a first electrode 2, a second electrode 4, a gate electrode 6, and a body electrode 8. For example, the transistor 1 may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The transistor 1 (e.g., a MOSFET) including the body electrode 8 has a small assembly area and is suitable for implementing high-resolution pixels.

[0033] Transistor 1 can be formed on a silicon wafer. For example, a transistor layer, a light-emitting layer, and a cover layer can be stacked on the silicon wafer to form a panel. However, this is illustrative only, and transistor 1 can be formed on various currently known substrates (e.g., a glass substrate).

[0034] The first electrode 2 of the transistor 1 may be configured as a drain electrode (or a source electrode), and the second electrode 4 may be configured as a source electrode (or a drain electrode). When the transistor 1 includes a body electrode 8, the threshold voltage of the transistor 1 may be changed due to a body effect. The body effect refers to a change in the threshold voltage of the transistor 1 due to a voltage difference between the body electrode 8 and the source electrode (or the second electrode 4) of the transistor.

[0035] For example, the threshold voltage may be increased if the voltage level of the source electrode 4 is higher than the voltage level of the body electrode 8. If the threshold voltage of the transistor 1 changes, the magnitude of the current flowing from the drain electrode 2 to the source electrode 4 of the transistor 1 may change.

[0036] In order to maintain a constant current flowing from drain electrode 2 to source electrode 4 of transistor 1, the threshold voltage of transistor 1 needs to be compensated. In an embodiment of the present invention, a pixel is proposed that uses transistor 1 including body electrode 8 for driving the transistor while compensating the threshold voltage.

[0037] In more detail, even if the voltage changes of the drain electrode 2 and the source electrode 4 are reflected in the gate electrode 6 and the threshold voltage changes, the pixel according to the embodiment of the present invention can keep the magnitude of the current flowing from the drain electrode 2 to the source electrode 4 constant.

[0038] Figure 2 is a block diagram showing a display device according to an embodiment of the present invention. Figure 3 It shows Figure 2 FIG. 1 is a block diagram of an embodiment of a scan driving unit, a data driving unit, and a power supply unit.

[0039] Reference Figure 2 According to one embodiment of the present invention, a display device 100 may include a pixel unit 110 (or panel), a timing control unit 120, a scan driver unit 130, a data driver unit 140, a power supply unit 150, and a light driver unit 160. The above structures may be implemented as separate integrated circuits, or two or more of the above structures may be integrated into a single integrated circuit. Furthermore, the scan driver unit 130 and / or the light driver unit 160 may be formed in the pixel unit 110.

[0040] The pixel portion 110 may include pixels PX (where n, m, and o are positive numbers greater than 0) connected to write scan lines SL11 to SL1n, initialization scan lines SL21 to SL2n, data lines DL1 to DLm, light emitting control lines EL1 to ELo, and power lines PL1, PL2, and PL3.

[0041] For example, the pixel PXij (refer to Figure 4) can be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th light-emitting control line ELk, and the j-th data line DLj (here, i is a positive number less than n, j is a positive number less than m, and k is a positive number less than o). Here, k can be the same as i or a number less than i. For example, when each of the light-emitting control lines EL1 to ELo is connected to the pixels PX located on one horizontal line, k can be the same number as i. For example, when each of the light-emitting control lines EL1 to ELo is connected to the pixels PX located on two or more horizontal lines, k can be a number less than i.

[0042] When the first scan signal is supplied to each of the write scan lines SL11 to SL1n, pixels PX are selected as horizontal line units (for example, pixels PX connected to the same scan line can be classified into one horizontal line (or pixel row)). The pixels PX selected by the first scan signal can receive data signals from the data lines connected to them (any one of DL1 to DLm). Pixels PX receiving data signals can generate light of a predetermined brightness in response to the voltage of the data signals.

[0043] The timing control unit 120 may receive input data Din and a control signal CS from the host system via an interface. For example, the timing control unit 120 may receive input data Din and the control signal CS from at least one of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and an AP (Application Processor) included in the host system. The control signal CS may include various signals including a clock signal.

[0044] Based on the control signal CS, the timing control unit 120 generates a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS, which are supplied to the scan driving unit 130, the data driving unit 140, and the emission driving unit 160, respectively.

[0045] The timing control unit 120 may realign the input data Din to correspond to the specifications of the display device 100. In addition, the timing control unit 120 may correct the input data Din to generate output data Dout and supply the output data Dout to the data driving unit 140. In an embodiment, the timing control unit 120 may correct the input data Din according to an optical measurement result measured during a process.

[0046] The scan driver 130 may receive a scan drive signal SCS from the timing control unit 120. The scan drive signal SCS may include at least one scan start signal and a clock signal required for driving the scan driver 130. The scan driver 130 may generate a first scan signal and a second scan signal while shifting the scan start signal in response to the clock signal.

[0047] To this end, the scanning driving unit 130 may be as follows Figure 3 As shown in FIG. 1 , a first scanning driving unit 132 and a second scanning driving unit 134 are provided.

[0048] The first scan driver 132 receives the first scan start signal FLM1 and shifts the first scan start signal FLM1 in response to a clock signal to generate a first scan signal. The first scan driver 132 sequentially supplies the first scan signal to the write scan lines SL11 ˜SL1 n.

[0049] The second scan driver 134 receives the second scan start signal FLM2 and shifts the second scan start signal FLM2 in response to the clock signal, thereby generating a second scan signal. The second scan driver 134 sequentially supplies the second scan signal to the initialization scan lines SL21 to SL2n. The first and second scan signals are set to gate-on voltages to turn on the transistors in the pixels PX.

[0050] For example, a low-level first scan signal and a high-level second scan signal may be supplied to a P-type transistor, and a high-level first scan signal and a high-level second scan signal may be supplied to an N-type transistor. The transistor receiving the first scan signal or the second scan signal may be turned on in response to the first scan signal or the second scan signal. Subsequently, supplying the first scan signal and the second scan signal may mean that a gate-on voltage is supplied to the write scan line SL1 and the initialization scan line SL2. Subsequently, not supplying the first scan signal and the second scan signal may mean that a gate-off voltage is supplied to the write scan line SL1 and the initialization scan line SL2.

[0051] exist Figure 3 , the first scan driver 132 and the second scan driver 134 are shown to connect to each of the write scan line SL1 and the initialization scan line SL2, but the present invention is not limited thereto. For example, the write scan line SL1 and the initialization scan line SL2 may also be driven by one scan driver.

[0052] The data driving unit 140 may receive the output data Dout and the data driving signal DCS from the timing control unit 120. The data driving signal DCS may include a sampling signal and / or a timing signal required for driving the data driving unit 140.

[0053] The data driving part 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driving part 140 may generate an analog data signal based on the grayscale of the output data Dout.

[0054] The data driving unit 140 may apply a certain voltage to the data lines DL1 to DLm based on the generated analog data signal. Figure 5 , the data driving unit 140 can be used in one horizontal period 1H (refer to Figure 5 ) period, the voltage Vdata (reference Figure 5 ).

[0055] The power supply unit 150 may generate various power sources required for driving the display device 100. For example, the power supply unit 150 may generate a first driving power source VDD, a second driving power source VSS, and an initialization power source Vint.

[0056] The first driving power supply VDD may be a power supply that supplies a driving current to the pixel PX. The second driving power supply VSS may be a power supply that receives a driving current from the pixel PX. During a period in which the pixel PX is set to a light-emitting state, the first driving power supply VDD may be set to a voltage greater than the second driving power supply VSS.

[0057] The initialization power source Vint may be a power source for initializing the light emitting element LD included in each of the pixels PX (refer to Figure 4 ) is a voltage of the first electrode (or anode electrode). When the initialization power source Vint is supplied to the first electrode of the light emitting element LD, the voltage may have a voltage value at which the light emitting element LD is turned off.

[0058] The first driving power VDD generated by the power supply unit 150 may be supplied to the first power line PL1, the second driving power VSS may be supplied to the second power line PL2, and the initialization power Vint may be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be connected to the pixels PX in common, but the present invention is not limited thereto.

[0059] In an embodiment, the first power line PL1 may be composed of multiple power lines, each of which is connected to different pixels PX. In an embodiment, the second power line PL2 may be composed of multiple power lines, each of which is connected to different pixels PX. In an embodiment, the third power line PL3 may be composed of multiple power lines, each of which is connected to different pixels PX. In an embodiment of the present invention, a pixel PX can be connected to any one of the first power line PL1, any one of the second power line PL2, and any one of the third power line PL3.

[0060] The light-emitting driver 160 may receive a light-emitting drive signal ECS from the timing control unit 120. The light-emitting drive signal ECS may include a light-emitting start signal and a clock signal required for driving the light-emitting driver 160. The light-emitting driver 160 may generate a light-emitting control signal while shifting the light-emitting start signal EFLM in response to the clock signal. The light-emitting driver 160 may sequentially supply the light-emitting control signal to the light-emitting control lines EL1 to ELo. The light-emitting control signal may be set to a gate-on voltage to turn on the transistor included in the pixel PX.

[0061] For example, a low-level light emission control signal may be supplied to a P-type transistor, and a high-level light emission control signal may be supplied to an N-type transistor. The transistor receiving the light emission control signal may be turned on in response to the light emission control signal. Subsequently, supplying the light emission control signal may mean supplying a gate-on voltage to the light emission control line EL. Subsequently, not supplying the light emission control signal may mean supplying a gate-off voltage to the light emission control line EL.

[0062] Figure 4 It shows Figure 2 A circuit diagram of an embodiment of a pixel is shown. Figure 4 Pixels located on the i-th horizontal line and the j-th vertical line are shown in FIG.

[0063] Reference Figure 4 According to an embodiment of the present invention, a pixel PXij can be connected to corresponding signal lines SL1i, SL2i, ELk, and DLj. For example, a pixel PXij can be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk, and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0064] A pixel PXij according to an embodiment of the present invention may include a light emitting element LD and a pixel circuit PC for controlling the amount of current supplied to the light emitting element LD.

[0065] The light-emitting element LD may be connected between a first power line PL1 and a second power line PL2. For example, a first electrode (or anode electrode) of the light-emitting element LD may be electrically connected to the first power line PL1 via the second node N2, the first transistor M1, the first node N1, and the third transistor M3, and a second electrode (or cathode electrode) of the light-emitting element LD may be electrically connected to the second power line PL2. The light-emitting element LD may generate light of a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit PC.

[0066] The light emitting element LD can be an organic light emitting diode. In addition, the light emitting element LD can be an inorganic light emitting diode such as a micro LED or a quantum dot light emitting diode. In addition, the light emitting element LD can also be an element composed of a combination of organic and inorganic substances. Figure 4 In the figure, the pixel PXij is shown to include a single light emitting element LD. However, in other embodiments, the pixel PXij includes a plurality of light emitting elements LD. The plurality of light emitting elements LD may be connected in series, in parallel, or directly in series with each other.

[0067] The pixel circuit PC may include a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a first capacitor C1 , and a second capacitor C2 .

[0068] The first to fourth transistors M1 to M4 may be transistors including body electrodes. For example, each of the first to fourth transistors M1 to M4 may be a MOSFET (metal oxide semiconductor field effect transistor). In this case, the first to fourth transistors M1 to M4 can be assembled in a narrow area, thereby making the pixel PXij suitable for a high-resolution panel. The body electrodes of the first to fourth transistors M1 to M4 may receive a ground voltage GND. The ground voltage GND may have a level higher than the voltage level of the second driving power supply VSS.

[0069] In an embodiment, the second driving power source VSS may be provided as a ground voltage GND. For example, body electrodes of the first to fourth transistors M1 to M4 may be electrically connected to the second power line PL2.

[0070] In an embodiment, each of the first to fourth transistors M1 to M4 may be formed as an N-type transistor.

[0071] The first electrode of the first transistor M1 may be connected to the first node N1, and the second electrode may be connected to the second node N2. Here, "connected" means electrically connected. The gate electrode of the first transistor M1 may be connected to the third node N3. The first node N1 may be a node connected to the second electrode of the third transistor M3, and the second node N2 may be a node connected to the first electrode of the light-emitting element LD. The first transistor M1 may control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in response to the voltage of the third node N3.

[0072] The second transistor M2 may be connected between the data line DLj and the third node N3. The gate electrode of the second transistor M2 may be electrically connected to the i-th write scan line SL1i. When the first scan signal GW is supplied to the i-th write scan line SL1i, the second transistor M2 is turned on to electrically connect the data line DLj and the third node N3.

[0073] Alternatively, a first electrode of the third transistor M3 may be electrically connected to the first power line PL1, and a second electrode thereof may be electrically connected to the first node N1. The gate electrode of the third transistor M3 may be electrically connected to the light emission control line ELk. The third transistor M3 is turned on when a light emission control signal is supplied to the light emission control line ELk, and is turned off when the light emission control signal is not supplied. When the third transistor M3 is turned off, the first power line PL1 and the first node N1 may be electrically shielded.

[0074] The first electrode of the fourth transistor M4 may be connected to the second node N2, and the second electrode may be electrically connected to the third power line PL3. The gate electrode of the fourth transistor M4 may be electrically connected to the i-th initialization scan line SL2i. When the second scan signal EB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 is turned on, thereby electrically connecting the second node N2 and the third power line PL3.

[0075] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may transfer a voltage change amount of the first node N1 to the third node N3.

[0076] The second capacitor C2 may be connected between the second node N2 and the third node N3. The second capacitor C2 may transfer a voltage change amount of the second node N2 to the third node N3.

[0077] Figure 5 It shows Figure 4 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0078] Reference Figure 2 、 Figure 4 as well as Figure 5 The horizontal period 1H (or a specific horizontal period) for supplying data signals to pixels PXij located on the i-th horizontal line and the j-th vertical line can be divided into a first period T1 and a second period T2. The start time point of the second period T2 can be after the end time point of the first period T1.

[0079] The data driving part 140 may supply a voltage Vdata of a data signal to the data line DLj during the first period T1 and the second period T2 .

[0080] The scan driving part 130 (or the first scan driving part 132 ) may supply the first scan signal GW to the i-th write scan line SL1 i during the second period T2 .

[0081] The scan driving part 130 (or the second scan driving part 134 ) may supply the second scan signal EB to the i-th initialization scan line SL2 i during the first period T1 .

[0082] The light emitting driving part 160 may supply the light emitting control signal EM to the light emitting control line ELk during the third period T3 .

[0083] The first period T1 is a period in which the voltage of the initialization power supply Vint is supplied to the second node N2. During the first period T1, the anode electrode of the light emitting element LD can be initialized. That is, during the first period T1, the second node N2 can be initialized. This first period T1 can be called an initialization period.

[0084] The second period T2 may be a period in which the voltage Vdata of the data signal is supplied to the third node N3. Such a second period T2 may be referred to as a data signal writing period.

[0085] During the third period T3, the first transistor M1 controls the amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light-emitting element LD in response to the voltage of the third node N3. In this case, during the third period T3, the light-emitting element LD can emit light at a brightness corresponding to the amount of current supplied from the first transistor M1. This third period T3 can be named a light-emitting period.

[0086] In addition, the first transistor M1 operates in response to the voltage of the third node N3 reflecting the voltage difference of the first node N1 between the second period T2 and the third period T3 and the voltage difference of the second node N2 between the second period T2 and the third period T3, so that during the third period T3, the threshold voltage of the first transistor M1 can be compensated.

[0087] Figures 6 to 8 It shows that according to Figure 5 Circuit diagram of the pixel working process of the signal. Figures 6 to 8 The pixel circuit PC can correspond to Figure 5 The pixel circuit PC.

[0088] Reference Figure 6 During the first period T1, the third transistor M3 is set to a turned-off state by the light emitting control signal EM supplied to the light emitting control line ELk, during the first period T1, the second transistor M2 is set to a turned-off state by the first scan signal GW supplied to the i-th write scan line SL1i, and during the first period T1, the fourth transistor M4 is set to a turned-on state by the second scan signal EB supplied to the i-th initialization scan line SL2i.

[0089] When the second transistor M2 is turned off, the electrical connection between the data line DLj and the third node N3 is cut off. When the third transistor M3 is turned off, the electrical connection between the first power line PL1 and the first node N1 is cut off.

[0090] When the fourth transistor M4 is turned on, the voltage of the initialization power supply Vint is supplied to the second node N2. If the voltage of the initialization power supply Vint is supplied to the second node N2, the light-emitting element LD can be initialized. For example, if the voltage of the initialization power supply Vint is supplied, a parasitic capacitor (not shown) of the light-emitting element LD can be discharged. Here, the voltage of the initialization power supply Vint is set to a voltage at which the light-emitting element LD is turned off (or non-emitting), thereby setting the light-emitting element LD to a non-emitting state.

[0091] In addition, if the voltage of the initialization power source Vint is supplied to the second node N2, the source electrode N2 of the first transistor M1 may be set to a voltage lower than the body electrode of the first transistor M1.

[0092] Reference Figure 7 During the second period T2, the second transistor M2 may be turned on by the first scan signal GW supplied to the i-th write scan line SL1i.

[0093] Then, during the second period T2, the fourth transistor M4 is kept in the off state by the second scan signal EB supplied to the i-th initialization scan line SL2i, and during the second period T2, the third transistor M3 is kept in the off state by the emission control signal EM supplied to the emission control line ELk.

[0094] During the second period T2 , the second transistor M2 is set to a turn-on state, and thus supplies the voltage Vdata of the data signal from the data line DLj to the third node N3 .

[0095] Reference Figure 8During the third period T3, the second transistor M2 may be kept in the off state by the first scan signal GW supplied to the i-th write scan line SL1i, and during the third period T3, the fourth transistor M4 may be kept in the off state by the second scan signal EB supplied to the i-th initialization scan line SL2i.

[0096] Also, during the third period T3 , the third transistor M3 may be turned on by the light emitting control signal EM supplied to the light emitting control line ELk.

[0097] During the third period T3 , the third transistor M3 is set to a turn-on state, and thus the first transistor M1 controls the amount of current supplied from the first driving power source VDD to the second node N2 in response to a voltage applied to the third node N3 .

[0098] Reference Figure 8 According to an embodiment of the utility model of the present application, a process of reflecting the variation difference of the drain electrode N1 and the source electrode N2 of the first transistor M1 to the gate electrode N3 of the first transistor M1 to compensate for the threshold voltage of the first transistor M1 is described in detail.

[0099] First, the voltage of the gate electrode N3 of the first transistor M1 calculated reflecting the voltage change amount of the first node N1 may be set as in Math. 1.

[0100] [Mathematical formula 1]

[0101] VN3=VN1+△VN1×(c2 / c1+c2)

[0102] Referring to Mathematical Formula 1, VN3 may represent the voltage of the third node N3 reflecting the voltage change of the first node N1 during the third period T3. VN1 may represent the voltage of the first node N1 during the third period T3. ΔVN1 may represent the voltage change of the first node N1 during the second period T2 and the third period T3. c1 may represent the capacitance value of the first capacitor C1. c2 may represent the capacitance value of the second capacitor C2.

[0103] In the voltage VN3 of the gate electrode N3 of the first transistor M1 calculated in reflection of the voltage change amount of the first node N1, a mathematical expression reflecting the voltage change amount of the second node N2 may be set as in Math. 2.

[0104] [Mathematical formula 2]

[0105] VN3'=VN3+△VN2×(c1 / c1+c2)

[0106] Referring to Math 2, VN3′ may represent the voltage of the third node N3 reflecting the voltage changes of the first node N1 and the second node N2 in the third period T3. ΔVN2 may represent the voltage changes of the second node N2 in the second and third periods T2 and T3.

[0107] As shown in Mathematical Formulas 1 and 2, the voltage level of the third node N3 in the third period T3 can be calculated by reflecting the amount of change in the voltage of the first node N1 and the amount of change in the voltage of the second node N2. Therefore, during the second period T2 and the third period T3, even if the voltage of the first node N1 and the voltage of the second node N2 change, the magnitude of the current flowing from the first node N1 to the second node N2 can be maintained constant.

[0108] According to an embodiment of the present invention, it is possible to execute Figure 2 For example, the threshold voltage of each of the first transistors M1 in the pixel PX is compensated. Figure 2 Each pixel PX in the pixel unit 110 may include a first transistor. In this case, during the driving process of the display device 100, the first transistor in each pixel PX may have a different threshold voltage. In this case, the voltage change amount of the first and second nodes N1 and N2 of the pixel PX may also be set to be different according to the threshold voltage of each first transistor. The voltage change amount of the first and second nodes N1 and N2 is reflected to the third node N3, thereby compensating for the difference in the threshold voltage of the first transistor included in each pixel PX.

[0109] In this way, the threshold voltage of the first transistor M1, which functions as a driving transistor, is compensated to the third node N3, thereby minimizing or at least reducing the effect of the change in the threshold voltage of the first transistor M1 on the current flowing through the first transistor M1 to the light-emitting element LD. Therefore, the display device 100 can have improved grayscale expression.

[0110] Figure 9 It shows Figure 4 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0111] Reference Figure 2 、 Figure 4 as well as Figure 9 , a horizontal period 1H (or a specific horizontal period) for supplying data signals to pixels PXij located on the i-th horizontal line and the j-th vertical line can be divided into a first period T1, a second period T2, and a fourth period T4. The start time point of the fourth period T4 may be after the end time point of the second period T2. The end time point of the fourth period T4 may be before the start time point of the third period T3.

[0112] the following, Figure 9 The first time period T1, the second time period T2 and the third time period T3 can be described as Figure 4 The first time period T1, the second time period T2 and the third time period T3 are similar, and repeated descriptions are simplified or omitted.

[0113] The data driving part 140 may supply a voltage Vdata of a data signal to the data line DLj during the first to third periods T1 to T3 .

[0114] The scan driving part 130 (or the first scan driving part 132 ) may supply the first scan signal GW to the i-th write scan line SL1 i during the second period T2 and the fourth period T4 .

[0115] The scan driving part 130 (or the second scan driving part 134 ) may supply the second scan signal EB to the i-th initialization scan line SL2 i during the first period T1 .

[0116] The light emitting driving part 160 may supply the light emitting control signal EM to the light emitting control line ELk during the fourth period T4 and the third period T3 .

[0117] The fourth period T4 is a period for ensuring the timing margin of the light emitting operation. According to the fourth period T4, even if a time delay occurs during the transmission of the signals EM, GW, and EB, the light emitting element can stably emit light in the third period T3. In addition, the reliability of the threshold voltage compensation operation of the first transistor M1 can be improved. This fourth period T4 can be called a timing margin period. The length of the fourth period T4 is not limited to Figure 9 , which can vary depending on the user's settings.

[0118] The second transistor M2 may be kept on by the first scan signal GW supplied to the i-th write scan line SL1i during the fourth period T4, and the third transistor M3 may be turned on by the emission control signal EM supplied to the emission control line ELk during the fourth period T4.

[0119] Also, during the fourth period T4 , the fourth transistor M4 may maintain a turned-off state by the second scan signal EB supplied to the i-th initialization scan line SL2 i .

[0120] As the third transistor M3 is turned on, the light emitting element LD may emit light with a small amount of brightness in response to the amount of current supplied from the first transistor M1 during the fourth period T4.

[0121] It should be noted that the technical concept of the present invention is specifically described based on the aforementioned embodiments, but the embodiments are for illustration only and are not intended to limit the present invention. A person with ordinary knowledge in the technical field of the present invention will understand that various modifications can be made within the scope of the technical concept of the present invention.

[0122] The scope of the present invention is not limited to the contents described in the detailed description of the specification, but is determined by the claims. The meaning and scope of the claims, as well as all modifications or variations derived from their equivalents, are to be construed as being included within the scope of the present invention.

Claims

1. A pixel, characterized in that: include: a first transistor, wherein a first electrode is connected to the first node, a second electrode is connected to the second node, and a gate electrode is connected to the third node; a second transistor connected between the data line and the third node, with a gate electrode electrically connected to the first scan line; a third transistor connected between a first power line supplying a voltage of a first driving power source and the first node, with a gate electrode electrically connected to a light emitting control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; as well as The light emitting element is connected between the second node and a second power supply line for supplying a second driving power source.

2. The pixel according to claim 1, wherein The pixel further comprises: The fourth transistor has a first electrode connected to the second node, a second electrode electrically connected to a third power line for supplying initialization power, and a gate electrode electrically connected to the second scan line.

3. The pixel according to claim 2, wherein: When the voltage of the initialization power source is supplied to the second node, the light emitting element is turned off.

4. The pixel according to claim 2, wherein: Each of the first to fourth transistors is a MOSFET including a body electrode.

5. The pixel according to claim 4, wherein: Each of the first to fourth transistors is an N-type transistor.

6. The pixel according to claim 4, wherein: A ground voltage is supplied to a body electrode of each of the first to fourth transistors.

7. A display device, characterized in that: include: Pixels are connected to the write scan line, initialization scan line, data line and light emitting control line. The pixels located in the i-th pixel row and the j-th pixel column include: a first transistor, wherein a first electrode is connected to the first node, a second electrode is connected to the second node, and a gate electrode is connected to the third node; a second transistor connected between a j-th data line among the data lines and the third node, and turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line supplying a voltage of a first driving power source and the first node, and turned on when a light emitting control signal is supplied to a kth light emitting control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; and A light emitting element is connected between the second node and a second power supply line for supplying a second driving power source, wherein i is a positive number greater than or equal to 0, j is a positive number greater than or equal to 0, and k is a positive number greater than or equal to 0.

8. The display device according to claim 7, wherein: The pixels located in the i-th pixel row and the j-th pixel column further include: The fourth transistor has a first electrode connected to the second node, a second electrode electrically connected to a third power line supplying an initialization power source, and is turned on when a second scan signal is supplied to the second scan line.

9. The display device according to claim 8, wherein Each of the first to fourth transistors is a MOSFET including a body electrode to which a ground voltage is supplied.

10. The display device according to claim 8, wherein Each of the first to fourth transistors is an N-type transistor.

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