Layout structure of all-digital transmitter suitable for UWB chip

Abstract

The utility model discloses a layout structure of an all-digital transmitter suitable for a UWB chip, comprising a first digital baseband and a second digital baseband which are used for outputting first and second digital baseband clock signals, and the first and second digital baseband clock signals are respectively the input of a first bandwidth controller and the input of a second bandwidth controller. The output ends of the first bandwidth controller and the second bandwidth controller are respectively connected with the input ends of the first digital deserialization pulse shaper and the second digital deserialization pulse shaper, and the output ends of the first digital deserialization pulse shaper and the second digital deserialization pulse shaper are respectively connected with the input end of the digital pulse synthesizer. The output end of the digital pulse synthesizer is connected with the input end of the first switched capacitor power amplifier and the input end of the second switched capacitor power amplifier, and the output end of the first switched capacitor power amplifier and the output end of the second switched capacitor power amplifier are connected with the on-chip passive balun. According to the layout structure of the all-digital transmitter suitable for the UWB chip provided by the utility model, the layout of the all-digital transmitter is compact, and the size miniaturization is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of UWB chips, in particular to a layout structure of a full-digital transmitter suitable for UWB chips. Background Art

[0002] Ultra-Wideband (UWB) is applicable to a wide range of wireless systems. Among them, IR-UWB (Impulse Radio - Ultra-Wideband) technology is a promising solution for high-precision ranging and positioning. Unlike existing narrowband solutions like Bluetooth, IR-UWB uses time-of-flight ranging technology to provide high-precision ranging and precise positioning in applications requiring spatial awareness, such as secure access, indoor positioning, and augmented reality (AR) / virtual reality (VR).

[0003] Traditional IR-UWB transmitters use digital baseband pulse-shaping filters, whose output is up-converted to RF via an IQ (In-Phase and Quadrature) mixer. This is then transmitted using a linear power amplifier. To meet spectrum mask requirements, these transmitters typically consume high power, limiting battery life and, in turn, their application scope. With the digitization of wireless communications and advancements in semiconductor technology, programmable logic devices are becoming increasingly larger and smaller, while also requiring increasingly stringent operational stability. This necessitates a new layout structure for fully digital transmitters to meet these requirements. Utility Model Content

[0004] In view of the problems and shortcomings of the prior art, the utility model provides a layout structure of a full-digital transmitter suitable for a UWB chip. The full-digital transmitter has a compact layout and is miniaturized.

[0005] The utility model provides a layout structure of a full-digital transmitter suitable for a UWB chip, which is characterized in that it includes a first digital baseband, a second digital baseband, a first bandwidth controller, a second bandwidth controller, a first digital deserialization pulse shaper, a second digital deserialization pulse shaper, a digital pulse synthesizer, a first switched capacitor power amplifier and a second switched capacitor power amplifier;

[0006] The first digital baseband and the second digital baseband are used to output a first digital baseband clock signal and a second digital baseband clock signal, respectively. The first digital baseband clock signal and the second digital baseband clock signal are input to a first bandwidth controller and a second bandwidth controller, respectively. The output ends of the first bandwidth controller and the second bandwidth controller are connected to the input ends of a first digital deserialized pulse shaper and a second digital deserialized pulse shaper, respectively. The output ends of the first digital deserialized pulse shaper and the first digital deserialized pulse shaper are connected to the input end of a digital pulse synthesizer, respectively. The output end of the digital pulse synthesizer is connected to the input end of the first switched capacitor power amplifier and the second switched capacitor power amplifier, respectively. The output ends of the first switched capacitor power amplifier and the second switched capacitor power amplifier are connected to an on-chip passive balun.

[0007] Preferably, the first bandwidth controller, the second bandwidth controller, the first digital deserialization pulse shaper, the second digital deserialization pulse shaper, the first switched capacitor power amplifier, the second switched capacitor power amplifier and the digital pulse synthesizer are arranged on the inner side of the baseband module, and the radio frequency unit is arranged on the outer side of the baseband module.

[0008] Preferably, the digital pulse synthesizer is arranged at the center position of the baseband module, the first digital deserialization pulse shaper is arranged on the upper side of the digital pulse synthesizer, the second digital deserialization pulse shaper is arranged on the lower side of the digital pulse synthesizer, the first switched capacitor power amplifier is arranged on the upper side of the first digital deserialization pulse shaper, and the second switched capacitor power amplifier is arranged on the lower side of the second digital deserialization pulse shaper.

[0009] Preferably, the widths of the first digital deserialization pulse shaper, the second digital deserialization pulse shaper, the first switched capacitor power amplifier, the second switched capacitor power amplifier and the digital pulse synthesizer are all equal, and the widths of the internal sub-modules of the first digital deserialization pulse shaper, the second digital deserialization pulse shaper, the first switched capacitor power amplifier, the second switched capacitor power amplifier and the digital pulse synthesizer are all equal.

[0010] Preferably, the first digital deserialization pulse shaper and the second digital deserialization pulse shaper respectively include FIR filters with multiple delay taps for generating multi-path pulse signals.

[0011] Preferably, the first digital deserialization pulse shaper and the second digital deserialization pulse shaper respectively include a delay unit for controlling a unit delay and a frequency measurement unit for measuring and calibrating the unit delay.

[0012] Preferably, the first switched capacitor power amplifier and the second switched capacitor power amplifier are both differential structures.

[0013] Preferably, the first switched capacitor power amplifier and the second switched capacitor power amplifier each include a plurality of power amplifier units operating in parallel, and any of the power amplifier units each include a plurality of subunits for configuring output power levels.

[0014] The positive progress effect of this utility model is:

[0015] The utility model provides a full-digital transmitter suitable for a UWB chip, comprising a first digital baseband, a second digital baseband, a first bandwidth controller, a second bandwidth controller, a first digital deserialized pulse shaper, a second digital deserialized pulse shaper, a digital pulse synthesizer, a first switched capacitor power amplifier, and a second switched capacitor power amplifier; wherein the first digital baseband and the second digital baseband are respectively used to output a first digital baseband clock signal and a second digital baseband clock signal, the first digital baseband clock signal and the second digital baseband clock signal are respectively input to the first bandwidth controller and the second bandwidth controller, the output ends of the first bandwidth controller and the second bandwidth controller are respectively connected to the input ends of the first digital deserialized pulse shaper and the second digital deserialized pulse shaper, the output ends of the first digital deserialized pulse shaper and the first digital deserialized pulse shaper are respectively connected to the input end of the digital pulse synthesizer, the output end of the digital pulse synthesizer is respectively connected to the input ends of the first switched capacitor power amplifier and the second switched capacitor power amplifier, and the output ends of the first switched capacitor power amplifier and the second switched capacitor power amplifier are connected to an on-chip passive balun. Thus, the compact layout enables miniaturization and stable operation.

[0016] Furthermore, by arranging the radio frequency unit outside the baseband module, signal coupling caused when the signal path of the baseband module passes through the radio frequency unit can be avoided.

[0017] Furthermore, the digital pulse synthesizer is centrally located, with the first and second digital deserialized pulse shapers positioned above and below it, respectively. This layout ensures that the multiple delayed sub-pulses generated by the first and second digital deserialized pulse shapers follow identical paths to the digital pulse synthesizer. Consequently, layout parasitics are also identical, maximizing spectrum utilization.

[0018] Furthermore, the first switched capacitor power amplifier and the second switched capacitor power amplifier are located above the first digital deserialized pulse shaper and below the second digital deserialized pulse shaper, respectively. This layout prevents the baseband module's wiring from passing through the radio frequency unit. Furthermore, the input and output wiring of the first switched capacitor power amplifier and the second switched capacitor power amplifier do not pass through the first digital deserialized pulse shaper, the second digital deserialized pulse shaper, and the digital pulse synthesizer, thus avoiding parallel routing of signal lines between the baseband module and the radio frequency unit.

[0019] Furthermore, the widths of each module and submodule are equal. This layout ensures that the digital pulse synthesizer is highly symmetrical with respect to the subunits of the first and second switched capacitor power amplifiers, ensuring that the multi-path delayed sub-pulses of the digital pulse synthesizer reach both amplifiers along identical paths, and that the layout parasitic effects are also completely consistent. As a result, the quantization window function pulse shape formed by the digital pulse synthesizer is identical when it reaches the first and second switched capacitor power amplifiers, achieving excellent pulse up-conversion performance.

[0020] Furthermore, the all-digital transmitter uses digital deserialization technology to effectively reduce inter-symbol interference (ISI) while maintaining the efficiency of the power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0022] Figure 1 FIG. 1 is a schematic diagram of the architecture of a fully digital transmitter suitable for a UWB chip according to a preferred embodiment.

[0023] Figure 2 This is a schematic diagram of the layout structure of a fully digital transmitter suitable for a UWB chip in a preferred embodiment.

[0024] Description of reference numerals:

[0025] 1. Baseband module; 11. First bandwidth controller; 12. Second bandwidth controller; 13. First digital deserialization pulse shaper; 14. Second digital deserialization pulse shaper; 15. Digital pulse synthesizer; 16. First switched capacitor power amplifier; 17. Second switched capacitor power amplifier;

[0026] 2. a first digital baseband clock signal;

[0027] 3. A second digital baseband clock signal;

[0028] 4. Radio frequency unit. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0030] The technical solution of the present utility model is described in detail below with reference to specific embodiments.

[0031] In view of the problems existing in the prior art, an embodiment of the present utility model provides a full-digital transmitter suitable for a UWB chip. The full-digital transmitter has a compact layout and is miniaturized.

[0032] Based on the problems existing in the prior art, an embodiment of the present invention provides a fully digital transmitter suitable for a UWB chip, including a first digital baseband, a second digital baseband, a first bandwidth controller (BW_CTRL0) 11, a second bandwidth controller (BW_CTRL1) 12, a first digital deserialized pulse shaper (PS0) 13, a second digital deserialized pulse shaper (PS1) 14, a digital pulse synthesizer (PS_CMB) 15, a first switched capacitor power amplifier (SCPA0) 16, and a second switched capacitor power amplifier (SCPA1) 17.

[0033] like Figure 1 As shown, in this embodiment, the first bandwidth controller 11, the second bandwidth controller 12, the first digital deserialization pulse shaper 13, the second digital deserialization pulse shaper 14, the digital pulse synthesizer 15, the first switched capacitor power amplifier 16, and the second switched capacitor power amplifier 17 are arranged on the inner side of the baseband module 1, and the radio frequency unit (TXRF) 4 is arranged on the outer side of the baseband module (TX) 1.

[0034] First, the first and second digital baseband signals output a first digital baseband clock signal (DBB clock0) 2 and a second digital baseband clock signal (DBB_clock1) 3 at high-speed clock frequencies, respectively. These signals represent the amplitude and phase required for binary phase shift keying (BPSK) encoded signals. The first and second digital baseband clock signals 2 and 31 serve as inputs to the first and second bandwidth controllers 11 and 12. Because the rectangular pulse shapes of the first and second digital baseband clock signals 2 and 3 lack good spectral characteristics and their sidebands violate most standard mask requirements, the first and second bandwidth controllers 11 and 12 are required to perform pulse shaping. These controllers are responsible for adjusting the pulse widths of the first and second digital baseband clock signals 2 and 3.

[0035] Then, the pulse-shaped first digital baseband clock signal 2 and the second digital baseband clock signal 3 are respectively passed through the first digital deserialization pulse shaper 13 and the second digital deserialization pulse shaper 14 to generate multiple pulse signals. These multiple pulse signals together form a quantized pulse shape, thereby maximizing the use of the spectrum. Therefore, the output ends of the first bandwidth controller 11 and the second bandwidth controller 12 are respectively connected to the input ends of the first digital deserialization pulse shaper 13 and the second digital deserialization pulse shaper 14. Among them, the first digital deserialization pulse shaper 13 and the second digital deserialization pulse shaper 14 each include a FIR (Finite Impulse Response) filter with multiple delay taps for generating multiple pulse signals.

[0036] Next, the outputs of the first and second digital deserialized pulse shapers 13 and 14 are connected to the inputs of a digital pulse synthesizer 15 (PCMB, Pulse Code Modulation-Based). The digital pulse synthesizer 15 adds or subtracts the pulses output by the first and second digital deserialized pulse shapers 13 and 14 according to the phase polarity provided by the phase encoding, thereby achieving pulse serialization. The first and second digital deserialized pulse shapers 13 and 14 each include a delay unit for controlling the unit delay and a frequency measurement unit for measuring and calibrating the unit delay.

[0037] The multi-channel signal bus output by the digital pulse synthesizer 15 is then fed to the first switched capacitor power amplifier 16 (SCPA1) and the second switched capacitor power amplifier 17 (SCPA2). The sum of these buses represents the envelope of the output RF signal. The output of the digital pulse synthesizer 15 is connected to the inputs of the first switched capacitor power amplifier 16 and the second switched capacitor power amplifier 17, respectively. The output signal of the digital pulse synthesizer 15 is mixed with the RF carriers in the first and second switched capacitor power amplifiers 16, 17. The switched capacitor power amplifiers implement charge-domain summation of the output buses of the digital pulse synthesizer 15, thereby creating the required envelope for the RF signal output by the RF unit 4. The first and second switched capacitor power amplifiers 16, 17 both have differential structures. They each include multiple power amplifier units operating in parallel, with each power amplifier unit comprising multiple subunits for configuring the output power level.

[0038] Finally, the output ends of the first switched capacitor power amplifier 16 and the second switched capacitor power amplifier 17 are connected to the on-chip passive balun to realize the transmission of the first digital baseband clock signal 2 and the second digital baseband clock signal 3.

[0039] Furthermore, the unit delay of the first digital deserialized pulse shaper 13 and the second digital deserialized pulse shaper 14 can be controlled via a multi-bit programmable bias current unit. The all-digital transmitter undergoes on-chip calibration when inactive due to voltage or temperature variations. In this calibration mode, the output of the delay line is fed back to the input via a multiplexer, converting it into a ring oscillator. A frequency measurement unit measures and calibrates the unit delay by optimizing the current bias settings of the first and second digital deserialized pulse shapers 13 and 14, thereby optimizing the pulse shape and ensuring proper operation of the all-digital transmitter in high-bandwidth mode. The multiple output signals of the first and second digital deserialized pulse shapers 13 and 14 are used to activate one of the corresponding multiple parallel power amplifier units. Each power amplifier unit is composed of multiple power amplifier sub-units and can be configured with multiple output power control levels to meet the -41.3dBm / MHz power spectral density requirement for different mPRFs.

[0040] like Figure 2As shown, in this embodiment, the digital pulse synthesizer 15 is located in the center of the baseband module 1, the first digital deserialized pulse shaper 13 is located above the digital pulse synthesizer 15, and the second digital deserialized pulse shaper 14 is located below the digital pulse synthesizer 15. This layout ensures that the multiple delayed sub-pulses generated by the first digital deserialized pulse shaper 13 and the second digital deserialized pulse shaper 14 take identical paths to reach the digital pulse synthesizer 15. Consequently, the layout parasitic effects are also identical, maximizing spectrum utilization.

[0041] Furthermore, the first switched capacitor power amplifier 16 is disposed above the first digital deserialization pulse shaper 13, and the second switched capacitor power amplifier 17 is disposed below the second digital deserialization pulse shaper 14. This layout prevents the wiring of the baseband module 1 from passing through the radio frequency unit 4. Furthermore, the input and output wiring of the first switched capacitor power amplifier 16 and the second switched capacitor power amplifier 17 do not pass through the first digital deserialization pulse shaper 13, the second digital deserialization pulse shaper 14, and the digital pulse synthesizer 15, thus avoiding parallel routing of signal lines between the baseband module 1 and the radio frequency unit 4.

[0042] Furthermore, the widths of the first digital deserialized pulse shaper 13, the second digital deserialized pulse shaper 14, the first switched capacitor power amplifier 16, the second switched capacitor power amplifier 17, and the digital pulse synthesizer 15 are all equal, and the widths of the internal submodules of the first digital deserialized pulse shaper 13, the second digital deserialized pulse shaper 14, the first switched capacitor power amplifier 16, the second switched capacitor power amplifier 17, and the digital pulse synthesizer 15 are all equal. This layout ensures that the digital pulse synthesizer 15 is highly symmetrical with respect to the subunits of the first switched capacitor power amplifier 16 and the second switched capacitor power amplifier 17, so that the paths of the multi-path delayed sub-pulses of the digital pulse synthesizer 15 reaching the first switched capacitor power amplifier 16 and the second switched capacitor power amplifier 17 are exactly the same, and the layout parasitic effects are also completely consistent. Therefore, the quantization window function pulse shape formed by the digital pulse synthesizer 15 is exactly the same when it reaches the first switched capacitor power amplifier 16 and the second switched capacitor power amplifier 17, thereby achieving excellent pulse up-conversion function.

[0043] In order to avoid signal coupling between the first digital baseband signal 2 and the second digital baseband signal 3 through the radio frequency unit 4, the utility model provides a full-digital transmitter suitable for a UWB chip, including a first digital baseband, a second digital baseband, a first bandwidth controller, a second bandwidth controller, a first digital deserialization pulse shaper, a second digital deserialization pulse shaper, a digital pulse synthesizer, a first switched capacitor power amplifier and a second switched capacitor power amplifier; wherein: the first digital baseband and the second digital baseband are used to output a first digital baseband clock signal and a second digital baseband clock signal, respectively, and the first digital baseband clock signal and the second digital baseband clock signal are used to output a first digital baseband clock signal and a second digital baseband clock signal, respectively. The signals are input to the first bandwidth controller and the second bandwidth controller, respectively. The outputs of the first bandwidth controller and the second bandwidth controller are connected to the inputs of the first digital deserialized pulse shaper and the second digital deserialized pulse shaper, respectively. The outputs of the first digital deserialized pulse shaper and the first digital deserialized pulse shaper are connected to the input of the digital pulse synthesizer, respectively. The outputs of the digital pulse synthesizer are connected to the inputs of the first switched capacitor power amplifier and the second switched capacitor power amplifier, respectively. The outputs of the first switched capacitor power amplifier and the second switched capacitor power amplifier are connected to an on-chip passive balun. Thus, miniaturization and stable operation are achieved through a compact layout.

[0044] Furthermore, by arranging the radio frequency unit outside the baseband module, signal coupling caused when the signal path of the baseband module passes through the radio frequency unit can be avoided.

[0045] Furthermore, the digital pulse synthesizer is centrally located, with the first and second digital deserialized pulse shapers positioned above and below it, respectively. This layout ensures that the multiple delayed sub-pulses generated by the first and second digital deserialized pulse shapers follow identical paths to the digital pulse synthesizer. Consequently, layout parasitics are also identical, maximizing spectrum utilization.

[0046] Furthermore, the first switched capacitor power amplifier and the second switched capacitor power amplifier are located above the first digital deserialized pulse shaper and below the second digital deserialized pulse shaper, respectively. This layout prevents the baseband module's wiring from passing through the radio frequency unit. Furthermore, the input and output wiring of the first switched capacitor power amplifier and the second switched capacitor power amplifier do not pass through the first digital deserialized pulse shaper, the second digital deserialized pulse shaper, and the digital pulse synthesizer, thus avoiding parallel routing of signal lines between the baseband module and the radio frequency unit.

[0047] Furthermore, the widths of each module and submodule are equal. This layout ensures that the digital pulse synthesizer is highly symmetrical with respect to the subunits of the first and second switched capacitor power amplifiers, ensuring that the multi-path delayed sub-pulses of the digital pulse synthesizer reach both amplifiers along identical paths, and that the layout parasitic effects are also completely consistent. As a result, the quantization window function pulse shape formed by the digital pulse synthesizer is identical when it reaches the first and second switched capacitor power amplifiers, achieving excellent pulse up-conversion performance.

[0048] Furthermore, the all-digital transmitter uses digital deserialization technology to effectively reduce inter-symbol interference (ISI) while maintaining the efficiency of the power amplifier.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A layout structure of a fully digital transmitter suitable for a UWB chip, characterized in that: The system comprises a first digital baseband, a second digital baseband, a first bandwidth controller, a second bandwidth controller, a first digital deserialization pulse shaper, a second digital deserialization pulse shaper, a digital pulse synthesizer, a first switched capacitor power amplifier and a second switched capacitor power amplifier; The first digital baseband and the second digital baseband are used to output a first digital baseband clock signal and a second digital baseband clock signal, respectively. The first digital baseband clock signal and the second digital baseband clock signal are input to a first bandwidth controller and a second bandwidth controller, respectively. The output ends of the first bandwidth controller and the second bandwidth controller are connected to the input ends of a first digital deserialized pulse shaper and a second digital deserialized pulse shaper, respectively. The output ends of the first digital deserialized pulse shaper and the second digital deserialized pulse shaper are connected to the input ends of a digital pulse synthesizer, respectively. The output ends of the digital pulse synthesizer are connected to the input ends of the first switched capacitor power amplifier and the second switched capacitor power amplifier, respectively. The output ends of the first switched capacitor power amplifier and the second switched capacitor power amplifier are connected to an on-chip passive balun.

2. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 1, characterized in that: The first bandwidth controller, the second bandwidth controller, the first digital deserialization pulse shaper, the second digital deserialization pulse shaper, the first switched capacitor power amplifier, the second switched capacitor power amplifier and the digital pulse synthesizer are arranged on the inner side of the baseband module, and the radio frequency unit is arranged on the outer side of the baseband module.

3. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 2, characterized in that: The digital pulse synthesizer is arranged at the center position of the baseband module, the first digital deserialization pulse shaper is arranged on the upper side of the digital pulse synthesizer, the second digital deserialization pulse shaper is arranged on the lower side of the digital pulse synthesizer, the first switched capacitor power amplifier is arranged on the upper side of the first digital deserialization pulse shaper, and the second switched capacitor power amplifier is arranged on the lower side of the second digital deserialization pulse shaper.

4. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 3, characterized in that: The widths of the first digital deserialization pulse shaper, the second digital deserialization pulse shaper, the first switched capacitor power amplifier, the second switched capacitor power amplifier and the digital pulse synthesizer are all equal, and the widths of the internal sub-modules of the first digital deserialization pulse shaper, the second digital deserialization pulse shaper, the first switched capacitor power amplifier, the second switched capacitor power amplifier and the digital pulse synthesizer are all equal.

5. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 1, characterized in that: The first digital deserialization pulse shaper and the second digital deserialization pulse shaper each include a FIR filter with multiple delay taps for generating a multi-path pulse signal.

6. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 1, characterized in that: The first digital deserialization pulse shaper and the second digital deserialization pulse shaper respectively include a delay unit for controlling a unit delay and a frequency measurement unit for measuring and calibrating the unit delay.

7. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 1, characterized in that: The first switched capacitor power amplifier and the second switched capacitor power amplifier are both differential structures.

8. The layout structure of a fully digital transmitter suitable for a UWB chip according to claim 5, characterized in that: The first switched capacitor power amplifier and the second switched capacitor power amplifier each include a plurality of power amplifier units operating in parallel, and each of the power amplifier units includes a plurality of subunits for configuring output power levels.

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