Vertical light emitting diode chip

Abstract

The utility model discloses a vertical light emitting diode chip, and belongs to the technical field of diode chips. The vertical light-emitting diode chip comprises a P electrode, and further comprises conductive metal, a first DBR layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer and a dielectric layer which are sequentially stacked on the P electrode from bottom to top, an N electrode is fixedly connected above the dielectric layer, and a second DBR layer is connected below the N electrode; a third DBR layer is arranged above the protruding part of the P-type semiconductor layer; the outer side between the P-type semiconductor layer and the conductive metal is wrapped with a P-type ohmic contact semiconductor layer; according to the utility model, through diffuse reflection of the plurality of DBR light reflecting layers, the emergent angle of light can be changed, scattering of a light source is reduced, shielding of the light source by an electrode is avoided, and the utilization rate of the chip light source is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of diode chips, in particular to a vertical light emitting diode chip. Background Art

[0002] Vertical light-emitting diode chips are specially designed semiconductor devices. Their structural feature is that the current flows almost entirely vertically through the epitaxial layer, thereby optimizing current distribution and improving luminous efficiency. With their unique structure and advantages, vertical light-emitting diode chips have shown broad application prospects in fields such as lighting, display, and communications. With the continuous advancement of technology, their performance and application scope will be further expanded.

[0003] Currently, substrate transfer technology is commonly used to connect the light-emitting epitaxial stack to a conductive substrate through a metal bonding layer to form a high-brightness vertical light-emitting diode. Chips with this structure cannot use metal reflection technology to improve the light output rate, and the light output rate is mostly improved through a current blocking layer. This current blocking layer made of a single material can only block current and cannot reflect light. Based on this, the present utility model is proposed. Utility Model Content

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a vertical light emitting diode chip that can overcome the above problems or at least partially solve the above problems.

[0005] In order to achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A vertical light-emitting diode chip includes a P-electrode, and further includes: a conductive metal, a first DBR layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and a dielectric layer stacked in sequence from bottom to top above the P-electrode; an N-electrode fixedly connected above the dielectric layer, and a second DBR layer connected below the N-electrode; a third DBR layer provided above the protruding portion of the P-type semiconductor layer; and a P-type ohmic contact semiconductor layer wrapped around the outer side between the P-type semiconductor layer and the conductive metal.

[0007] Preferably, a protective layer is wrapped around the outer side between the P-type semiconductor layer and the second DBR layer.

[0008] Preferably, the first DBR layer ( ) and the second DBR layer ( ) both include multiple layers of cross-stacked SiO2 layers and Si3N4 layers.

[0009] Furthermore, the second DBR layer is embedded in the middle of the dielectric layer in a cone shape, and the bottom end of the second DBR layer is similar in shape to the N electrode.

[0010] Preferably, the side surface of the third DBR layer is in the shape of a right triangle and the inclined surface faces the light-emitting layer.

[0011] Preferably, a metal reflective layer is provided above the conductive metal.

[0012] Preferably, the P-type semiconductor layer is convex and the convex portion is in contact with the P-type ohmic contact semiconductor layer.

[0013] Furthermore, the third DBR layer is provided on the upper end surface of the raised portion of the P-type semiconductor layer.

[0014] Compared with the prior art, the present invention provides a vertical light-emitting diode chip with the following advantages:

[0015] 1. This vertical light-emitting diode chip can reflect part of the downward-irradiating light source to the irradiation surface through the reflection of the first and third DBR layers, thereby avoiding the loss of light source. The reflection of the second DBR layer can reflect part of the light source blocked by the N electrode downward. Combined with the reflection of the first and second DBR layers, the light source emitted by the diode can be maximized.

[0016] 2. The vertical light-emitting diode chip can increase the contact area between the current and the P-type semiconductor layer through the P-type ohmic contact semiconductor layer, thereby avoiding the problem of excessive heat generation caused by too small a current conduction area.

[0017] The parts not involved in the device are the same as those in the prior art or can be implemented using the prior art. The utility model increases the luminous efficiency of the chip and can avoid the problem of excessive heat generation due to a small current conduction area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the overall structure of a vertical light-emitting diode chip proposed in the present invention;

[0019] Figure 2 This is a cross-sectional view of a vertical light-emitting diode chip proposed in the present invention;

[0020] Figure 3 This is a bottom view of a vertical light-emitting diode chip proposed in the present invention;

[0021] Figure 4 This is a top view of a vertical light emitting diode chip proposed in the present invention;

[0022] Figure 5 This is a side view of a vertical light emitting diode chip proposed by the present invention.

[0023] In the figure: 1. P electrode; 2. Conductive metal; 3. Metal reflective layer; 4. First DBR layer; 5. P-type semiconductor layer; 6. Light-emitting layer; 7. N-type semiconductor layer; 8. Dielectric layer; 9. Second DBR layer; 10. N electrode; 11. Protective layer; 12. Third DBR layer; 13. P-type ohmic contact semiconductor layer. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0025] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the present invention.

[0026] Example 1:

[0027] Reference Figure 1-Figure 5 A vertical light-emitting diode chip includes a P electrode 1, and further includes: a conductive metal 2, a first DBR layer 4, a P-type semiconductor layer 5, a light-emitting layer 6, an N-type semiconductor layer 7, and a dielectric layer 8 are stacked one above the P electrode 1; an N-electrode 10 is fixedly connected above the dielectric layer 8, and a second DBR layer 9 is connected below the N-electrode 10; a third DBR layer 12 is provided above the protruding portion of the P-type semiconductor layer 5; and a P-type ohmic contact semiconductor layer 13 is wrapped around the outer side between the P-type semiconductor layer 5 and the conductive metal 2.

[0028] In the present invention, current is guided by the P-electrode 1 and transmitted to the conductive metal 2. It then conducts through the P-type ohmic contact semiconductor layer 13 and enters the P-type semiconductor layer 5. As it passes through the P-type semiconductor layer 5 and the N-type semiconductor layer 7, electrons recombine in the light-emitting layer 6, radiating excess energy as photons. The current then flows through the dielectric layer 8 and out of the N-electrode 10. A recessed region is formed through the dielectric layer 8, communicating with the N-type semiconductor layer 4. The recessed region faces the N-electrode 10. A second DBR layer 9 is formed within the recessed region, with the top surface of the second DBR layer 9 flush with the top surface of the dielectric layer 8. The N-electrode 10 is mounted on the top surfaces of the second DBR layer 9 and the dielectric layer 8. The dielectric layer 8 is a commonly used ITO layer. The conductive metal 2 is made of a material with excellent electrical and thermal conductivity, thereby dissipating heat from the chip during conduction. Conduction through the P-type ohmic contact semiconductor layer 13 increases the contact area between the current and the P-type semiconductor layer 5, thereby avoiding the problem of excessive heat generation due to a small current conduction area.

[0029] Example 2:

[0030] Reference Figure 1-Figure 5 , which is basically the same as Example 1, and furthermore, a protective layer 11 is wrapped around the outer side between the P-type semiconductor layer 5 and the second DBR layer 9, the first DBR layer (4) and the second DBR layer (9) both include multiple layers of cross-stacked SiO2 layers and Si3N4 layers, the second DBR layer 9 is conical and embedded in the middle of the dielectric layer 8, the bottom end of the second DBR layer 9 is similar in shape to the N electrode 10, the side surface of the third DBR layer 12 is in the shape of a right triangle and the inclined surface faces the light-emitting layer 6, a metal reflective layer 3 is provided above the conductive metal 2, the P-type semiconductor layer 5 is convex and the convex portion is in contact with the P-type ohmic contact semiconductor layer 13, and the third DBR layer 12 is provided on the upper end surface of the convex portion of the P-type semiconductor layer 5.

[0031] In the present invention, a protective layer 11 is deposited on the exposed surface above the P-type semiconductor layer 5 to prevent the chip from leaking electricity and to protect the inside of the chip. The protective layer 11 covers the upper surfaces of the P-type semiconductor layer 5, the light-emitting layer 6, the N-type semiconductor layer 7 and the dielectric layer 8.

[0032] The SiO2 layer and the Si3N4 layer are both excellent insulating materials that can act as current blocking layers. Therefore, they can be used as the main material of the DBR layer. A metal reflective film is then coated on the reflective surface of the DBR layer through vacuum deposition to obtain a complete DBR layer. The second DBR layer 9 can reflect light that is blocked by the N electrode 10 and cannot be emitted back into the chip, and the first DBR layer 4 and the third DBR layer 12 reflect it out of the chip. At the same time, the first DBR layer 4 and the third DBR layer 12 can reflect the light source emitted downward by the light-emitting layer 6 out of the chip.

[0033] The metal reflective layer 3 can reflect and absorb the light that penetrates the first DBR layer 4 to prevent excess light from passing through the bottom plate.

[0034] The boss design of the P-type semiconductor layer 5 can effectively increase the contact area between the P-type ohmic contact semiconductor layer 13 and the P-type semiconductor layer 5, thereby increasing the current flow area, increasing the power of the chip, and reducing the generated heat.

[0035] When manufacturing the third DBR layer 12 , the slope of the third DBR layer 12 can be changed according to the distance between the third DBR layer 12 and the light-emitting layer 6 , so that the third DBR layer 12 can reflect the light source directly upward.

[0036] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any technician familiar with the technical field within the technical scope disclosed by the present invention can make equivalent replacements or changes based on the technical solution and utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A vertical light emitting diode chip, comprising a P electrode (1), characterized in that: Also includes: A conductive metal (2), a first DBR layer (4), a P-type semiconductor layer (5), a light-emitting layer (6), an N-type semiconductor layer (7), and a dielectric layer (8) are stacked in sequence from bottom to top above the P electrode (1); An N-electrode (10) is fixedly connected above the dielectric layer (8), and a second DBR layer (9) is connected below the N-electrode (10); A third DBR layer (12) is provided above the protruding portion of the P-type semiconductor layer (5); The outer side between the P-type semiconductor layer (5) and the conductive metal (2) is wrapped with a P-type ohmic contact semiconductor layer (13).

2. The vertical light emitting diode chip according to claim 1, characterized in that: The outer sides between the P-type semiconductor layer (5) and the second DBR layer (9) are wrapped with a protective layer (11).

3. The vertical light emitting diode chip according to claim 1, characterized in that: The first DBR layer (4) and the second DBR layer (9) both comprise multiple layers of cross-stacked SiO2 layers and Si3N4 layers.

4. The vertical light emitting diode chip according to claim 3, characterized in that: The second DBR layer (9) is embedded in the middle of the dielectric layer (8) in a cone shape, and the bottom end of the second DBR layer (9) is similar in shape to the N electrode (10).

5. The vertical light emitting diode chip according to claim 1, characterized in that: The side surface of the third DBR layer (12) is in the shape of a right triangle, and the inclined surface faces the light-emitting layer (6).

6. The vertical light emitting diode chip according to claim 1, characterized in that: A metal reflective layer (3) is provided above the conductive metal (2).

7. The vertical light emitting diode chip according to claim 1, characterized in that: The P-type semiconductor layer (5) is convex, and the convex portion is in contact with the P-type ohmic contact semiconductor layer (13).

8. The vertical light emitting diode chip according to claim 7, characterized in that: The third DBR layer (12) is provided on the upper end surface of the raised portion of the P-type semiconductor layer (5).

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