Photosensitive pixel element containing P-type thin film transistor transmission gate and image sensor

Abstract

The invention discloses a photosensitive pixel element containing a P-type thin film transistor transmission gate and an image sensor. The photosensitive pixel element comprises a substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the single-layer or double-layer P-type thin film semiconductor layer is positioned above the dielectric layer and is in ohmic contact with the signal reading electrode through the opening part; the photoelectric conversion layer is located above the P-type thin film semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic device technology, and more specifically, to a photosensitive pixel element and image sensor containing a P-type thin-film transistor transmission gate. Background Technology

[0002] Due to their ability to be directly integrated with CMOS readout circuit chips, stacked thin-film photodetectors have attracted attention as image sensors in recent years. Stacked thin-film photodetectors typically consist of a bottom electrode, a lower charge transport layer, a photoelectric conversion layer, an upper charge transport layer, and a top electrode, stacked sequentially from bottom to top. The photoelectric conversion layer utilizes a direct bandgap semiconductor material (such as organic semiconductor thin films or quantum dot semiconductor thin films). Due to its 10... 5 cm -1 The strong light absorption coefficient and high-efficiency photoelectric conversion layer can be achieved with a sub-micron thickness, meaning the thickness of the photoelectric conversion layer is smaller than or much smaller than the pixel scale. These characteristics greatly simplify the overall structure and fabrication process of image sensors. For example, the patterning process of the photoelectric conversion layer can be omitted, allowing the entire PIN-type thin-film photodetector array to be realized in a single photolithography step (e.g., patent "A Thin-Film Device, Photosensitive Device and Display Device for Suppressing Inter-Pixel Signal Crosstalk", publication number CN119342914A, publication date 2025-01-21). Using multi-component heterojunction (BHJ) organic semiconductor thin films with complementary light absorption regions (e.g., patent "An Organic Photodiode and its Array, and a Method for Fabricating the Organic Photodiode", publication number CN113823744A, publication date 2021-12-21) can also achieve a wider spectral response than traditional silicon-based image sensors. This simplifies the number of cameras in portable products, reduces weight, and lowers system power consumption.

[0003] Traditional CIS photodetectors consist of photosensitive pixels and pixel readout circuits both constructed from CMOS circuitry on the surface of a silicon wafer. Due to the absorption limitation of the PN junction used as the photosensitive region, the actual photosensitive region is limited to the visible region. Back-illuminated CIS moves the PIN photosensitive layer below the pixel readout circuit, forming a stacked three-dimensional structure. By increasing the duty cycle of the photosensitive pixels and increasing the thickness of the photosensitive layer, the response of CIS in the near-infrared region (>700nm) can be improved. However, even with these measures, its photoelectric conversion efficiency in the infrared region is still far lower than that in the visible region. Therefore, integrating a stacked thin-film photoelectric conversion array onto the CMOS pixel readout circuit allows for new cameras that not only increase the pixel density of digital cameras but also enable low-cost, high-sensitivity infrared cameras and broadband cameras from ultraviolet to infrared.

[0004] Compared to traditional 3T active pixel sensor (APS) pixel readout circuits, 4T pixel readout circuits separate the pixel sensing unit in the pinned photodiode from the charge collection and readout node via a transmission gate TX (see SPIE Proceedings, Vol. 7021, "High Energy, Optical and Infrared Detectors for Astronomy III," p. 702103, 2008). This design achieves higher charge-to-voltage conversion gain, lower pixel noise, and improved dynamic range. In addition to being suitable for CMOS image sensors (CIS) where each pixel employs a pinned silicon PIN diode structure, this 4T pixel readout circuit can also be used in CMOS image sensors integrating thin-film photodetector arrays (such as organic semiconductor thin films or quantum dot thin-film arrays). These thin-film detector arrays, with their high photoelectric conversion efficiency and low dark current, enable these CMOS image sensors to be used in low-light applications ranging from high-light (microwatts / cm²) to nanowatts / cm².

[0005] To enhance dynamic performance under strong light, storage capacitors can be added to the metal / insulator wiring layer of a CMOS image sensor. For example, the patent "Pixel Detector, Stacked Pixel Detector, and Solid-State Imaging Device" (Publication No.: CN111033741A, Publication Date: 2020-04-17) discloses a stacked photodetector array structure: an N-type amorphous metal oxide layer (such as InGaZnO), a dielectric oxide layer, and a conductive metal layer are stacked below an organic thin-film photoelectric conversion layer. A charge storage unit and a transmission gate (TX) are fabricated using these three layers. During the transmission gate's off period, the signal charge generated by the photoelectric conversion layer is stored in the charge storage unit. When the transmission gate is open, the signal charge in the charge storage unit can be transferred to the pixel readout circuit. Incomplete charge transfer can cause image ghosting.

[0006] The image sensor disclosed in the aforementioned patent uses the same N-type amorphous metal oxide layer as the pixel electrode beneath the organic thin-film photoelectric conversion layer, and also serves as the channel layer for the transmission gate (TX). However, in practical applications, many situations require the underlying pixel electrode to be a P-type semiconductor to achieve optimal photoelectric conversion efficiency and the lowest dark current.

[0007] Therefore, there is an urgent need for a P-type thin-film semiconductor layer that can simultaneously serve as a P-type pixel electrode below the photoelectric conversion layer, and as a channel layer for the transmission gate of a bottom contact gate, source, and drain electrode type thin-film transistor. Summary of the Invention

[0008] This invention provides a photosensitive pixel element and an image sensor containing a P-type thin-film transistor transmission gate. The P-type thin-film semiconductor layer can also serve as the P-type pixel electrode below the photoelectric conversion layer, and as the channel layer for the bottom contact gate, source, and drain electrode type thin-film transistor transmission gate. This structure is suitable for photodetector arrays where the pixel electrode below the photoelectric conversion layer is P-type and the upper contact layer is N-type.

[0009] The technical solution adopted in this invention is:

[0010] A photosensitive pixel element containing a P-type thin-film transistor transmission gate, the photosensitive pixel element comprising:

[0011] Substrate;

[0012] Charge accumulation electrode, transmission control electrode, and signal readout electrode are located on the same side of the substrate and reflect incident light.

[0013] A dielectric layer covers the charge accumulation electrode, the transmission control electrode, and the signal readout electrode, and has an opening at the position corresponding to the signal readout electrode.

[0014] A single or double-layered P-type thin-film semiconductor layer is located above the dielectric layer and makes ohmic contact with the signal readout electrode through an opening.

[0015] The photoelectric conversion layer is located above the P-type thin-film semiconductor layer;

[0016] The top electrode for incident light transmission is located above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, transmission control electrode, and signal readout electrode.

[0017] Preferably, when the P-type thin-film semiconductor layer is a single-layer structure, the P-type thin-film semiconductor layer includes: organic semiconductor material, organometallic semiconductor material, or metal compound semiconductor material.

[0018] Furthermore, the carrier concentration of the P-type thin-film semiconductor layer is 10 16 -10 19 hole / cm 3 Hole mobility greater than 10 -1 cm 2 / Vs, thickness 5-100nm.

[0019] Preferably, when the P-type thin-film semiconductor layer is a double-layer structure, it includes a first P-type thin-film semiconductor layer located on the dielectric layer and a second P-type thin-film semiconductor layer located on the first P-type thin-film semiconductor layer.

[0020] Furthermore, the first P-type thin-film semiconductor layer includes: an organic semiconductor material, an organometallic semiconductor material, or a metal compound semiconductor material.

[0021] Furthermore, the organic semiconductor materials include pentacene, rubrene, C6-DBTDT-C6, DBTDT, C10-BTBT-C10, C8-BTBT-C8, C6-BTBT-C6, BTBT, DPh-DNTT, PPCD, TBT, and C6-TBT-C;

[0022] The organometallic semiconductor material includes a metal-centered phthalocyanine complex; the metal includes iron, cobalt, nickel, copper, zinc, tin, titanium, and combinations thereof;

[0023] The metal compound semiconductor materials include tin oxide (SnO), cuprous oxide (Cu2O), copper sulfide (CuS), zinc selenide (ZnSe), nickel oxide (NiO), cuprous iodide (CuI), molybdenum disulfide (MoS2), and tellurium selenide composite oxide (Se:TeOx).

[0024] The metal compound semiconductor materials also include YBa2Cu3O6, La2CuO4, (Bi,Pb)2Sr2CaCu2O8, and other undoped or weakly doped oxide semiconductors containing a two-dimensional cuprous oxide layer that exhibit superconductivity when deeply oxygen-doped.

[0025] Furthermore, the second P-type thin-film semiconductor layer comprises one or more independently selected from organic compound 2, inorganic compound 2, or combinations thereof;

[0026] The organic compound 2 includes 4,4'-cyclohexylbis[N,N'-di(4-methylphenyl)aniline], N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-benzidine, N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-2,7-diamino9,9-spirodifluorene, 2,2',7,7'-tetra[N,N-di(4-methoxyphenyl)amino]-9,9'-spirodifluorene, 4,4',4"-tris(carbazole-9-yl)triphenylamine, poly(4-butyltriphenylamine), polyvinylcarbazole, and polystyrene-N,N'-diphenyl-N,N'-bis-(3-methylphenyl)-(1,1)-biphenyl-4,4 One or more of the following: '-diamine perfluorocyclobutane, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonic acid), and poly[bis(4-phenyl)(4-butylphenyl)amine];

[0027] The inorganic compound 2 includes tungsten oxide, molybdenum oxide, vanadium oxide, chromium oxide, nickel oxide, copper oxide, cuprous oxide, cuprous thiocyanate, copper sulfide, copper iodide, copper phthalocyanine, or a mixture or complex of the above materials.

[0028] Furthermore, the carrier concentration of the first P-type thin-film semiconductor layer is 10 16 -10 19 hole / cm 3 Hole mobility greater than 10 -1 cm 2 / Vs, thickness 5-100nm;

[0029] The carrier concentration of the second P-type thin-film semiconductor layer is 10 16 -10 18 hole / cm 3 Hole mobility greater than 10 -3 cm 2 / Vs, thickness 5-20 nm.

[0030] Furthermore, the photosensitive pixel element also includes an N-type semiconductor layer located between the photoelectric conversion layer and the top electrode.

[0031] Furthermore, the photosensitive pixel element further includes: a first SAM layer disposed between the P-type thin-film semiconductor layer and the photoelectric conversion layer, and / or a second SAM layer disposed between the photoelectric conversion layer and the top electrode.

[0032] Furthermore, the first SAM layer includes: carbazole molecules containing phosphonic acid or carboxyl anchoring groups, aromatic amine molecules, fluorene, or thiophene.

[0033] Furthermore, the second SAM layer comprises: a fullerene with a hydrophilic group, an aromatic group or aromatic heterocyclic group, an aliphatic chain, or a metal-quinoline ol salt; the hydrophilic group includes a carboxyl group, a hydroxyl group, an amino group, or an amine group; and an alkylthiol monolayer containing an amide group.

[0034] An image sensor includes a plurality of photosensitive pixel elements, as described above, containing P-type thin-film transistor transmission gates, forming an image array. The photosensitive pixel elements include:

[0035] Substrate;

[0036] Charge accumulation electrode, transmission control electrode, and signal readout electrode are located on the same side of the substrate and reflect incident light.

[0037] A dielectric layer covers the charge accumulation electrode, the transmission control electrode, and the signal readout electrode, and has an opening at the position corresponding to the signal readout electrode.

[0038] A patterned single or double-layered P-type thin-film semiconductor layer is located above the dielectric layer and makes ohmic contact with the signal readout electrode through an opening.

[0039] The photoelectric conversion layer is located above the P-type thin-film semiconductor layer and is shared by all photosensitive pixel elements in the image array;

[0040] The top electrode, which transmits incident light, is located above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, transmission control electrode, and signal readout electrode, and is shared by each photosensitive pixel element in the image array.

[0041] Preferably, the photosensitive pixel element further includes an N-type semiconductor layer located between the photoelectric conversion layer and the top electrode, and this layer is shared among the various photosensitive pixel elements in the image array.

[0042] Furthermore, an array of color filter layers consisting of multiple color filters is integrated above the top electrode, wherein each color filter layer covers a photosensitive pixel element below it.

[0043] Furthermore, a microlens array consisting of multiple microlenses is integrated above the color filter array, wherein each microlens corresponds to covering a photosensitive pixel element below.

[0044] Furthermore, a microlens array consisting of multiple microlenses is integrated above the top electrode, wherein each microlens covers a photosensitive pixel element below.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] This invention provides a photosensitive pixel element that utilizes a transmission control electrode, a charge accumulation electrode, a signal readout electrode, a dielectric layer, and a P-type thin-film semiconductor layer to form a P-type thin-film transistor transmission gate. The P-type thin-film semiconductor layer also serves as the channel layer for the thin-film transistor transmission gate and the pixel electrode beneath the photoelectric conversion layer. This invention optimizes the parameters of the P-type thin-film semiconductor layer, thereby optimizing the performance of both the thin-film transistor transmission gate and the thin-film photodetector array. Attached Figure Description

[0047] Figure 1 This is a cross-sectional view of the structure of a single-layer P-type thin-film semiconductor photosensitive pixel element provided by the present invention.

[0048] Figure 2 This is a cross-sectional view of the structure of a photosensitive pixel element with a double-layer P-type thin-film semiconductor layer provided by the present invention.

[0049] Figure 3 This is a cross-sectional view of the structure of a PIN-type photosensitive pixel element provided by the present invention.

[0050] Figure 4 This is a cross-sectional view of the structure of a photosensitive pixel element having a first SAM layer and a second SAM layer provided by the present invention.

[0051] Figure 5 This is a cross-sectional view of the structure of a photosensitive pixel element with a color filter layer provided by the present invention.

[0052] Figure 6 This is a circuit diagram of a pixel readout circuit provided by the present invention.

[0053] Figure 7 This is a cross-sectional view of the structure of an image sensor provided by the present invention.

[0054] Figure 8 This is a top view of the image array in the image sensor provided by the present invention.

[0055] In the figure, 1-charge accumulation electrode, 101-second connecting metal pillar, 102-second bonding pad, 2-signal readout electrode, 201-opening, 202-first connecting metal pillar, 203-first bonding pad, 3-top electrode, 4-photoelectric conversion layer, 5-P-type thin film semiconductor layer, 501-first P-type thin film semiconductor layer, 502-second P-type thin film semiconductor layer, 6-dielectric layer, 7-encapsulation layer, 8-microlens, 9-first interlayer dielectric layer, 10-transmission control electrode, 1001-third connecting metal pillar, 1002-third bonding pad, 11-substrate, 111-circuit layer, 112-metal wiring layer, 12-N-type semiconductor layer, 13-first SAM layer, 14-second SAM layer, 15-color filter layer, 100-photosensitive pixel element, FD1-floating diffusion node. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0057] It should be understood that, when used in this specification, the terms “comprising” and “including” indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0058] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms.

[0059] It should also be further understood that the term "and / or" as used in this specification refers to any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations.

[0060] Example 1

[0061] like Figure 1 , Figure 2 As shown, the present invention provides a photosensitive pixel element containing a P-type thin-film transistor transmission gate, the photosensitive pixel element comprising:

[0062] Substrate 11

[0063] The charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2 are located on the same side of the substrate 11 and reflect the incident light.

[0064] The dielectric layer 6 covers the charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2, and has an opening 201 at the position corresponding to the signal readout electrode 2.

[0065] A single or double-layered P-type thin-film semiconductor layer 5 is located above the dielectric layer 6 and is in ohmic contact with the signal readout electrode 2 through the opening 201.

[0066] Photoelectric conversion layer 4 is located above the P-type thin-film semiconductor layer 5;

[0067] The top electrode 3, which transmits incident light, is located above the photoelectric conversion layer 4 and is arranged opposite to the charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2.

[0068] In this embodiment, the normally transparent top electrode 3 can also be directly used as the N-layer of a PIN-type photoelectric conversion pixel to effectively collect electrons generated by photoexcitation. If the Fermi level of the top electrode 3 does not match the conduction band bottom of the photoelectric conversion layer 4, an additional N-type semiconductor layer can be inserted at the interface between the top electrode 3 and the photoelectric conversion layer 4. This results in a top electrode layer with a dual-layer structure, comprising an N-type semiconductor layer and a top electrode layer.

[0069] In an image sensor according to an embodiment of the present invention, the signal readout electrode 2 may be formed to extend in an opening 201 disposed in the dielectric layer 6 to be connected to the P-type thin-film semiconductor layer 5. Optionally, the P-type thin-film semiconductor layer 5 may also be formed to extend in an opening 201 disposed in the dielectric layer 6 to be connected to the signal readout electrode 2. The cross-section of the opening 201 may be rectangular or trapezoidal, such as an isosceles trapezoid or a right trapezoid. The longitudinal section of the opening 201 may be circular, square, or polygonal.

[0070] The working principle of this invention is as follows: This invention utilizes the transmission control electrode 10, charge accumulation electrode 1, signal readout electrode 2, dielectric layer 6, and P-type thin-film semiconductor layer 5 to form a P-type thin-film transistor transmission gate; the P-type thin-film semiconductor layer 5 serves as the P-channel layer of the P-type thin-film transistor transmission gate; the charge accumulation electrode 1, the dielectric layer 6 located on the charge accumulation electrode 1, and the portion of the P-type thin-film semiconductor layer 5 opposite to the charge accumulation electrode 1 form a thin-film capacitor; the dielectric layer 6 serves as the dielectric of the thin-film capacitor. Holes dissociated through the photoelectric conversion layer 4 are stored and accumulated in the P-type thin-film semiconductor layer 5, and electrons dissociated through the photoelectric conversion layer 4 are transported to the top electrode 3; the holes stored and accumulated in the P-type thin-film semiconductor layer 5 serve as signal charges.

[0071] In this embodiment, the size of the charge accumulation electrode 1 is larger than the size of the signal readout electrode 2, that is, the area of ​​the charge accumulation electrode 1 is larger than the area of ​​the signal readout electrode 2. The size of the transmission control electrode 10 can be smaller than or equal to the size of the signal readout electrode 2. The size of the effective pixel in the photosensitive pixel element is defined by the size of the P-type thin-film semiconductor layer 5.

[0072] In a specific embodiment, such as Figure 1 As shown, when the P-type thin-film semiconductor layer 5 is a single-layer structure, the P-type thin-film semiconductor layer 5 includes: organic semiconductor material, organometallic semiconductor material, or metal compound semiconductor material.

[0073] The organic semiconductor materials include pentacene, rubrene, C6-DBTDT-C6, DBTDT, C10-BTBT-C10, C8-BTBT-C8, C6-BTBT-C6, BTBT, DPh-DNTT, PPCD, TBT, and C6-TBT-C6.

[0074] The organometallic semiconductor material includes a metal-centered phthalocyanine complex; the metal includes iron, cobalt, nickel, copper, zinc, tin, titanium, and combinations thereof. Specifically, the organometallic semiconductor material can be understood to include titanium phthalocyanine, copper phthalocyanine, zinc phthalocyanine, tin phthalocyanine, iron phthalocyanine, cobalt phthalocyanine, and nickel phthalocyanine.

[0075] The metal compound semiconductor materials include tin oxide (SnO), cuprous oxide (Cu2O), copper sulfide (CuS), zinc selenide (ZnSe), nickel oxide (NiO), cuprous iodide (CuI), molybdenum disulfide (MoS2), and tellurium selenide composite oxide (Se:TeOx).

[0076] The metal compound semiconductor materials also include YBa2Cu3O6, La2CuO4, (Bi,Pb)2Sr2CaCu2O8, and other undoped or weakly doped oxide semiconductors containing a two-dimensional cuprous oxide layer that exhibit superconductivity when deeply oxygen-doped.

[0077] In this embodiment, the carrier concentration of the P-type thin-film semiconductor layer 5 is 10. 16 -10 19 hole / cm 3 Hole mobility greater than 10 -1 cm 2 / Vs, thickness 5-100nm. Preferably, the hole mobility of the p-type thin-film semiconductor layer 5 is 1-50cm. 2 / Vs.

[0078] In one embodiment, the p-type thin-film semiconductor layer is a SnO (tin suboxide) thin film. SnO thin films typically prepared below 350°C have an amorphous or nanocrystalline morphology and exhibit p-type conductivity, with tin ions in a divalent state. Preparation conditions, post-annealing treatment, and film thickness can be used to optimize the microstructure, surface morphology, and TFT performance of the film. P-doping of the SnO thin film (e.g., doping with Sb, Tm, Y, Ag, or hydrogen) can also be used to form fs and ps orbital hybridization to obtain a delocalized valence band top and high hole mobility.

[0079] The SnO thin films can be prepared using various methods, including RF sputtering, IBAD, ALD, thermal evaporation, and liquid deposition. Regardless of the method, post-annealing under effectively controlled conditions is crucial for film quality. Notably, the above preparation and processing conditions are compatible with the CMOS-BEOL process environment. The hole mobility of the SnO thin films obtained using the above preparation and processing conditions can reach 1-50 cm⁻¹. 2 / Vs.

[0080] In another embodiment, the p-type thin-film semiconductor layer 5 is made of NiOx thin film. NiOx thin films obtained by different preparation and post-processing methods have different hole concentrations and mobilities, typically ranging from 0.1 to 20 cm⁻¹. 2 / Vs range. For example, a NiOx thin film prepared by solution method on a 20nm Al2O3 gate insulating layer (i.e., dielectric layer) can achieve a 4.4 cm⁻¹ thickness at a -2V bias. 2 Hole mobility per unit volume (Vs). NiOx doping can further optimize hole concentration and mobility. For example, an 18 at% copper-doped NiOx film prepared by solution method, after 250 °C... After heat treatment, the hole concentration is 7×10⁻⁶. 16 cm -3 Hole mobility reaches 45 cm 2 / Vs. In the process of preparing NiOx thin films by the IBAD (ion-beam assisted deposition) method, the hole concentration of the NiOx thin film can be controlled by the oxygen ion beam bias voltage.

[0081] Since the Fermi level of the aforementioned P-type metal oxide can be tuned between -5.0 and -5.6 eV, its upper surface can be directly used as the contact surface with the photoelectric conversion layer.

[0082] In another embodiment, the p-type thin-film semiconductor layer 5 can be a tellurium selenide composite oxide (Se:TeOx). High-mobility selenium is incorporated into an amorphous tellurium sub-oxide film. With the valence band top delocalized by the 5p band of tellurium, the selenium doping concentration can simultaneously adjust the hole concentration and optimize the connectivity of the p orbitals, thereby enabling high-mobility p-type semiconductors at 225 nm. High-performance p-type channel thin-film transistors (TFTs) were fabricated under post-annealing conditions. Testing revealed superior performance in TeO₂ doped with 25 at% selenium (Se). 1.44 The average field-effect hole mobility of the corresponding transistor in the thin-film channel is approximately 15 cm²·V. -1 ・s -1 The switching current ratio reaches 10. 7 .

[0083] When necessary, the turn-off current of these P-type metal oxides can be further reduced by the following methods. For example, a high bandgap interface layer can be inserted between the S / D contact surface and the SnO channel interface, allowing majority carriers (holes in this embodiment) to pass through but blocking minority carriers (electrons in this embodiment). For example, Cu or Ni can be used as the S / D electrode layer, and a Cu2O or NiOx surface can be formed through surface oxidation to contact the P-type metal oxide channel. Experiments have shown that the turn-off current can be significantly reduced, and the current-to-once ratio can be increased to 10. 8 above.

[0084] Besides the aforementioned p-type metal oxides, Cu₂O is also a promising channel material for p-type oxide TFTs. It features low cost, high stability, and compatibility with existing CMOS-BEOL processes (such as copper lead fabrication processes). Achieving a high on / off ratio can be achieved by controlling hole carriers and reducing the concentration of defect states within the bandgap.

[0085] In addition, YBa2Cu3O6, La2CuO4, (Bi,Pb)2Sr2CaCu2O8, and other undoped or weakly doped oxide semiconductors containing two-dimensional cuprous oxide layers that exhibit superconductivity when deeply doped with oxygen can also be used to fabricate P-type metal oxide thin film transistors.

[0086] Besides p-type metal oxides, many metal compounds also possess p-type semiconductor properties and can be used as... Figure 1 The channel layer of a switching transistor. Specific examples include Cu:ZnS, CuS, CuSe, CuI, etc.

[0087] It is worth noting that in known P-type metal-oxide-slim thin-film transistors, the gate electrode and source / drain electrodes are typically located above the metal-oxide channel layer. However, in... Figure 1 In the structure shown, the channel layer is located above the gate electrode, source / drain electrode, and gate electrode surface.

[0088] Many organic semiconductor thin films also exhibit P-type conductivity characteristics, and P-type organic semiconductor thin film transistors, with their high hole mobility, high on / off ratio, and low off-state current, are also suitable for use as transistors. Figure 1 Switching devices in P-type organic semiconductor thin-film transistors. The table below lists some characteristic parameters of P-type organic semiconductor thin-film transistors.

[0089] Table 1

[0090]

[0091] In the past, high mobility in organic semiconductor-based TFTs could only be observed under relatively high gate-source and drain-source voltages; however, this problem can be solved by optimizing the contact between the source / drain and the channel, optimizing the gate insulating layer, and reducing defect states at the interface with the channel layer. Charge mobility can be optimized by utilizing the orientation between organic semiconductor molecules and their orientation with an external field. A significant difference from inorganic semiconductors is that the molecular orientation of organic semiconductors can be achieved at lower temperatures. Furthermore, mechanical friction or optically induced orientation on the film surface can cause thermally evaporated or solution-formed organic semiconductor molecules to align orderly along the channel direction, achieving charge mobility and operating voltage comparable to those of polycrystalline inorganic semiconductor thin-film transistors. To reduce the off-state current of P-type organic thin-film transistors, an effective strategy is to insert a P-type self-assembled monolayer between the bottom source / drain electrode surface and the P-type organic semiconductor thin film. This P-type self-assembled monolayer possesses wide bandgap characteristics and P-type semiconductor behavior, ensuring that majority carriers (holes) can conduct from the source to the drain in the channel while blocking minority carriers from reaching the source / drain electrodes. This strategy is not only applicable to organic semiconductor channels, but can also be extended to all P-type semiconductor channel systems, including metal compounds and organometallic compounds.

[0092] In addition, the gate insulating layer (GI) (also known as the dielectric layer) can be prepared using SiO2 (silicon dioxide), SiN (silicon nitride), SiON (silicon oxynitride), Al2O3 (alumina), ZrO2 (zirconia), or HfO2 (hafnium oxide), or organic insulating materials such as polystyrene, polyimide, CL-PVP, PVPy, and polystyrene (PS). It is particularly noteworthy that employing a double-layer or multi-layer gate insulating layer structure and selecting a wide bandgap dielectric material with low interface defect states (such as polystyrene (PS), polyimide (PI), and SiO2) can significantly reduce the off-state current (Ig). OFF ) and operating voltage.

[0093] Based on the above strategy, high mobility (1-50 cm) has been successfully prepared. 2 / V·s), low operating voltage (<5V) and high current switching ratio (10 6 -10 10 The organic thin-film transistor (OTFT) has performance that fully meets the application requirements of transmission transistors (TX) in high pixel density image arrays.

[0094] In another specific embodiment, such as Figure 2 As shown, when the P-type thin film semiconductor layer 5 has a double-layer structure, it includes a first P-type thin film semiconductor layer 501 located on the dielectric layer and a second P-type thin film semiconductor layer 502 located on the first P-type thin film semiconductor layer 501.

[0095] The first P-type thin-film semiconductor layer 501 includes an organic semiconductor material, an organometallic semiconductor material, or a metal compound semiconductor material;

[0096] The organic semiconductor materials include pentacene, rubrene, C6-DBTDT-C6, DBTDT, C10-BTBT-C10, C8-BTBT-C8, C6-BTBT-C6, BTBT, DPh-DNTT, PPCD, TBT, and C6-TBT-C6;

[0097] The organometallic semiconductor material includes a metal-centered phthalocyanine complex; the metal includes iron, cobalt, nickel, copper, zinc, tin, titanium, and combinations thereof. Specifically, the organometallic semiconductor material can be understood to include titanium phthalocyanine, copper phthalocyanine, zinc phthalocyanine, tin phthalocyanine, iron phthalocyanine, cobalt phthalocyanine, and nickel phthalocyanine.

[0098] The metal compound semiconductor materials include tin oxide (SnO), cuprous oxide (Cu2O), copper sulfide (CuS), zinc selenide (ZnSe), nickel oxide (NiO), cuprous iodide (CuI), molybdenum disulfide (MoS2), and tellurium selenide composite oxide (Se:TeOx).

[0099] The metal compound semiconductor materials also include YBa2Cu3O6, La2CuO4, (Bi,Pb)2Sr2CaCu2O8, and other undoped or weakly doped oxide semiconductors containing a two-dimensional cuprous oxide layer that exhibit superconductivity when deeply oxygen-doped.

[0100] The second P-type thin-film semiconductor layer 502 comprises one or more independently selected from organic compound 2, inorganic compound 2, or combinations thereof;

[0101] The organic compound 2 includes 4,4'-cyclohexylbis[N,N'-di(4-methylphenyl)aniline], N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-benzidine, N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-2,7-diamino9,9-spirodifluorene, 2,2',7,7'-tetra[N,N-di(4-methoxyphenyl)amino]-9,9'-spirodifluorene, 4,4',4"-tris(carbazole-9-yl)triphenylamine, poly(4-butyltriphenylamine), polyvinylcarbazole, and polystyrene-N,N'-diphenyl-N,N'-bis-(3-methylphenyl)-(1,1)-biphenyl-4,4 One or more of the following: '-diamine perfluorocyclobutane, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonic acid), and poly[bis(4-phenyl)(4-butylphenyl)amine];

[0102] The inorganic compound 2 includes tungsten oxide, molybdenum oxide, vanadium oxide, chromium oxide, nickel oxide, copper oxide, cuprous oxide, cuprous thiocyanate, copper sulfide, copper iodide, copper phthalocyanine, or a mixture or complex of the above materials.

[0103] Furthermore, the carrier concentration of the first P-type thin-film semiconductor layer 501 is 10 16 -10 19 hole / cm 3 Hole mobility greater than 10 -1 cm 2 / Vs, thickness 5-100nm; preferably, the hole mobility of the first P-type thin-film semiconductor layer 501 is 1-50 cm⁻¹. 2 / Vs.

[0104] The carrier concentration of the second P-type thin-film semiconductor layer 502 is 10. 16 -10 18 hole / cm 3 Hole mobility greater than 10 -3 cm 2 / Vs, thickness 5-30nm; preferably, the hole mobility of the second P-type thin-film semiconductor layer 502 is 10 -2 -10cm 2 / Vs.

[0105] By setting a double-layered P-type thin-film semiconductor layer 5, the present invention can further optimize the high mobility, low operating voltage and high current switching ratio of the formed P-type channel.

[0106] By applying different potentials to the transmission control electrode 10, this invention can achieve the accumulation of holes in the P-type thin-film semiconductor layer 5, or the transmission of holes accumulated in the P-type semiconductor layer 5 to the signal readout electrode 2. To improve the transmission characteristics of the thin-film transistor switch and the corresponding image residual characteristics, this invention can improve the P-type semiconductor.

[0107] In a specific embodiment, such as Figure 3 As shown, the photosensitive pixel element also includes an N-type semiconductor layer 12 located between the photoelectric conversion layer 4 and the top electrode 3.

[0108] At this time, the photosensitive pixel element containing a P-type thin-film transistor transmission gate includes:

[0109] Substrate 11;

[0110] The charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2 are located on the same side of the substrate 11 and reflect the incident light.

[0111] The dielectric layer 6 covers the charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2, and has an opening 201 at the position corresponding to the signal readout electrode 2.

[0112] A patterned single or double-layered P-type thin-film semiconductor layer 5 is located above the dielectric layer 6 and makes ohmic contact with the signal readout electrode 2 through the opening 201.

[0113] Photoelectric conversion layer 4 is located above the P-type thin-film semiconductor layer 5;

[0114] The N-type semiconductor layer 12 is located above the photoelectric conversion layer 4;

[0115] The top electrode 3, which transmits incident light, is located above the P-type thin-film semiconductor layer 5 and is arranged opposite to the charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2.

[0116] In this embodiment, the dielectric constant K of the dielectric layer 6 typically ranges from 3.5 (SiO2) to 25 (Al2O3, HfO, ZrO). The thickness of the dielectric layer 6 is usually selected between 8-100 nm, with a preferred range of 8-25 nm.

[0117] The dielectric layer 6 can be formed using sputtering, chemical vapor deposition (CVD) methods (including thermal CVD, metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid phase deposition, etc.).

[0118] The dielectric layer can also be a pure PVPy film, a double-layer PVPy / PS film, or a three-layer CL-PVP / PVPy / PS structure, which is sequentially deposited on the signal readout electrode, the transmission control electrode, and the charge accumulation electrode by spin coating. The CL-PVP layer is cured at 160°C for 120 minutes; the PVPy and PS layers are annealed at 120°C for 120 minutes and 30 minutes, respectively.

[0119] This invention optimizes the dielectric layer structure, enabling thin-film transistors to operate not only at low voltages below 5V but also exhibiting superior performance parameters: a mobility exceeding 10 cm² / V·s. Through this dielectric layer structure optimization, the invention also enables the device to achieve an off-state current (Ig). OFF The further reduction of ) simultaneously improves the switching ratio of the device.

[0120] In this embodiment, light can be incident from the top electrode 3 side, which is configured to be transparent and conductive or semi-transparent and conductive, with a transmittance of more than 60% for incident light; preferably, the transmittance of incident light is more than 70%; more preferably, the transmittance of incident light is more than 80%; and more preferably, the transmittance of incident light is more than 90%.

[0121] The transparent or translucent top electrode 3 is made of a transparent conductive material, such as a transparent conductive oxide (TCO), carbon nanotubes, graphene, a conductive polymer, a metal, or a mixture or alloy of at least two of these compounds. The top electrode 3 may have a single-layer or multi-layer structure.

[0122] Examples of TCOs capable of forming the top electrode 3 are indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), and titanium nitride (TiN). An example of a conductive polymer capable of forming the top electrode 3 is a polymer called PEDOT:PSS, which is a mixture of poly(3,4)-ethylenedioxythiophene, sodium polystyrene sulfonate, and polyaniline (also known as PAni). Examples of metals capable of forming the top electrode 3 are silver, aluminum, gold, copper, nickel, titanium, and chromium. An example of a multilayer structure capable of forming the top electrode 3 is an AZO / Ag / AZO type multilayer AZO and silver structure.

[0123] The thickness of the top electrode 3 can be in the range of 10 nm to 5 μm, for example, about 30 nm. When the top electrode 3 is metal, the thickness of a transparent or translucent top electrode 3 is less than or equal to 20 nm, preferably less than or equal to 10 nm.

[0124] The charge accumulation electrode 1, signal readout electrode 2, and transmission control electrode 10 are all totally reflective electrodes made of an opaque conductive material. The opaque conductive material includes one or more of silver, aluminum, gold, copper, nickel, titanium, and chromium. The thickness of the totally reflective electrode can range from 50 nm to 5 μm.

[0125] For example, the preparation of the electrodes is independently selected from one or more of the following methods: vacuum thermal evaporation, electron beam evaporation, molecular beam evaporation or plasma sputtering, atomic layer deposition or liquid film formation followed by reduction and conversion, electroplating or electrodeposition.

[0126] In this embodiment, the photoelectric conversion layer 4 includes an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blend film, an inorganic semiconductor or compound semiconductor in the form of single-phase or quantum dot nanoparticles, or a combination thereof in a mixed form or a thin film stack; wherein, D represents an organic donor material of electron donor; and A represents an organic acceptor material of electron acceptor.

[0127] The inorganic semiconductors include Si, Ge, SiGe, and CuInS in crystalline or polycrystalline forms. x Se 2-x (0 x 2) Nanoscale quantum dots, nanoscale quantum thin films, or single-phase films of CuInGa(S,Se), PbS, PbI2, PbI3, CuI, ZnI2, and InGaAs.

[0128] The organic semiconductor comprises an organic blend of D / A consisting of one or more organic donor materials used as electron donors (D) and one or more organic acceptor materials used as electron acceptors (A).

[0129] When the photoelectric conversion layer 4 includes organic materials, the photoelectric conversion layer 4 can have one of the following four forms:

[0130] (1) Formed from organic donor materials;

[0131] (2) Formed from organic acceptor materials;

[0132] (3) It is formed by a layered structure of organic donor material layer and organic acceptor material layer;

[0133] A stacked structure is formed consisting of an organic donor material layer, a mixed layer of organic donor material and organic acceptor material (bulk heterostructure), and an organic acceptor material layer;

[0134] The formation of a stacked structure consisting of organic donor material layers and mixed layers of organic donor and acceptor materials (bulk heterostructure), or

[0135] The formation of a stacked structure consisting of an organic acceptor material layer and a mixed layer of organic donor and organic acceptor materials (bulk heterostructure); and

[0136] It is formed by a mixed structure of organic donor and acceptor materials (bulk heterostructure). However, the stacking order can be suitably changed in each component.

[0137] The operating wavelength of the photoelectric conversion layer 4 is within the range of 300nm to 2000nm; that is, the photoelectric conversion layer 4 can detect visible light and / or infrared light. Preferably, the photoelectric conversion layer 4 is configured to detect infrared light. The thickness of the photoelectric conversion layer 4 can be in the range of 50nm to 2μm, for example, it can be about 50nm, 100nm, 150nm, 200nm, 250nm, etc.

[0138] When the photoelectric conversion layer 4 is configured to detect the visible light band, three color filter layers, namely R, G, and B, need to be arranged in parallel in the encapsulation layer 7; each color filter layer covers one photosensitive pixel element below it.

[0139] When the photoelectric conversion layer 4 is configured to detect infrared bands or a wide band including visible and infrared bands, the organic donor material may be one or more of the following:

[0140]

[0141] .

[0142] The organic acceptor material may be one or more of the following:

[0143]

[0144] .

[0145] In addition, the organic donor material can also be small molecule donor materials such as MA6, MA7, MA8, BTR, DR3TBDTT, etc. The organic acceptor material can also be fullerenes and fullerene derivatives, such as C... 60 C 70 and its derivatives, such as PCBM.

[0146] The preparation methods of the photoelectric conversion layer 4 include solution processing methods such as spin coating and inkjet printing, vacuum deposition methods such as thermal evaporation and organic vapor deposition, as well as solution-vacuum coupling or nanoimprinting.

[0147] In this embodiment, the N-type semiconductor layer 12 can serve as an electron transport layer or a hole blocking layer.

[0148] The material of the electron transport layer or hole blocking layer includes organic compound 1, inorganic compound 1, or a combination thereof;

[0149] Wherein, the organic compound 1 includes fullerenes and their derivatives, 4,7-diphenyl-1,10-phenanthroline, polyethyleneimine, polyethoxyethyleneimine, 2,9-dimethyl-4,7-biphenyl-1,10-o-diazaphenanthroline, [9,9-dioctylfluorene-9,9-bis(N,N-dimethylaminopropyl)fluorene], brominated-[9,9-dioctylfluorene-9,9-bis(N,N-dimethylaminopropyl)fluorene], lithium 8-hydroxyquinoline, 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene, bis(2-methyl-8-quinoline)-4-(phenylphenol)aluminum, 1,3,5-tris[(3-pyridyl)-phenyl-3-yl]benzene, naphthalimide bromide, or a mixture or complex of the above materials;

[0150] The inorganic compound 1 includes zinc oxide, tin oxide, aluminum-doped zinc oxide, magnesium-doped zinc oxide, gallium-doped zinc oxide, titanium oxide, tantalum oxide, zinc sulfide, chromium sulfide, or a mixture or composite of the above materials.

[0151] The preparation of the N-type semiconductor layer 12 is independently selected from one or more of solution deposition, sol-gel deposition, vacuum thermal evaporation, atomic layer deposition, chemical vapor deposition, electrodeposition, and anodic oxidation.

[0152] In one specific embodiment, the photosensitive pixel element further includes: a first SAM layer 13 disposed between the P-type thin-film semiconductor layer 5 and the photoelectric conversion layer 4, and / or a second SAM layer disposed between the photoelectric conversion layer 4 and the top electrode. Here, SAM stands for self-assembled monolayer.

[0153] For example, a device structure of the photosensitive pixel element is provided as follows: Figure 4 As shown, it can Figure 2 Based on the device structure shown, a first SAM layer 13 is provided between the P-type thin film semiconductor layer 5 and the photoelectric conversion layer 4, and a second SAM layer 14 is provided between the photoelectric conversion layer 4 and the top electrode.

[0154] For example, another device structure of the photosensitive pixel element is provided, which can be... Figure 2 Based on the device structure shown, a first SAM layer 13 is provided between the P-type thin film semiconductor layer 5 and the photoelectric conversion layer 4.

[0155] For example, another device structure of the photosensitive pixel element is provided, which can be... Figure 2 Based on the device structure shown, a second SAM layer 14 is provided between the photoelectric conversion layer 4 and the top electrode 3.

[0156] Alternatively, it may include an N-type semiconductor layer 12 located between the photoelectric conversion layer 4 and the top electrode 3; or an N-type semiconductor layer 12 located between the second SAM layer 14 and the top electrode 3.

[0157] In this embodiment, the second SAM layer 14 is an N-type SAM, which is an organic or organometallic molecule composed of groups with electronic-like properties and a reduction energy in the range of 4.1 ± 0.3 eV. One end of the molecule is lipophilic and the other end is hydrophilic.

[0158] For example, the second SAM layer 14 includes: a fullerene with a hydrophilic group, an aromatic group or an aromatic heterocyclic group, an aliphatic chain, or a metal-quinoline ol salt; the hydrophilic group includes a carboxyl group, a hydroxyl group, an amino group, or an amine group.

[0159] The metal-quinoline alkoxide includes one or more combinations of Liq (lithium 8-hydroxyquinoline), Bebq2 (bis(10-hydroxybenzo[h]quinoline)beryllium), Alq3 (aluminum tris(8-hydroxyquinoline)), Inq3 (indium tris(8-hydroxyquinoline)), Gaq3 (gallium tris(8-hydroxyquinoline)), Znq4 (zinc tetras(8-hydroxyquinoline)), and Snq4 (tin tetras(8-hydroxyquinoline)).

[0160] The fullerene includes C 20 C 60 C 70 C 76 C 80 One or more combinations thereof;

[0161] The aromatic groups may include one or more combinations of benzene rings, naphthalene, anthracene, and pyrene; the aromatic heterocyclic groups include thiophene or pyrrole, etc.

[0162] Specifically, the second SAM layer 14 can be a C60 with a side chain containing a COOH terminal group, or a phen / thiophene molecule with a COOH terminal group.

[0163] The second SAM layer 14 of the present invention can block all pinholes caused by defect peaks in the P-type thin film semiconductor layer 5, and form a dense pinhole-free layer on the surface of the P-type thin film semiconductor layer 5 or the oleophilic photoelectric conversion layer 4; therefore, it can improve the interface characteristics between the P-type thin film semiconductor layer 5 and the photoelectric conversion layer 4 by passivating the surface and changing the surface polarity.

[0164] The second SAM layer 14 can be an alkylthiol monolayer containing amide groups. This monolayer has the order and stability required for electron transfer through peptide bonds. Its methylene chain is in a microcrystalline environment, and extended interchain hydrogen bonds are formed between the amide groups.

[0165] In this embodiment, the first SAM layer 13 is a P-type SAM, which includes groups with hole-like properties (transmitting holes and blocking electrons), its oxidation energy is in the range of 5-5.5 eV, and one end of the molecule is oleophilic while the other end is hydrophilic.

[0166] For example, the first SAM layer 13 includes carbazole molecules containing phosphonic acid or carboxyl anchoring groups, aromatic amine molecules, fluorene, or thiophene. Specifically, it can be carbazole molecules containing phosphonic acid anchoring groups (such as the PACz series) or triarylamine molecules containing phosphonic acid anchoring groups (such as MPA-CPA, whose molecular structure is based on a triarylamine and connected to a phosphate anchoring group).

[0167] In this embodiment, as Figures 1-5As shown, the photosensitive pixel element also includes an encapsulation layer 7 to ensure stable operation of the photosensitive pixel element under various operating environments and during its target lifespan. The encapsulation layer 7 covers the top electrode 3. Since light is incident from the top electrode 3, the encapsulation layer 7 should be transparent in the operating wavelength range and should be made of a material that transmits incident light.

[0168] The encapsulation layer 7 can be formed using various vacuum deposition methods, such as thermal evaporation, molecular beam deposition, plasma sputtering, or atomic layer deposition. It can also be prepared using liquid deposition methods, such as drop coating, dip coating, spin coating, and various printing methods. Besides using a single material, the encapsulation layer 7 can also be formed using alternating multilayer films. In addition to improving encapsulation performance, this alternating film structure can also be used to optimize the optical resonant cavity structure of the image sensor in the operating wavelength band, thereby optimizing its photosensitiveness and specific detectivity.

[0169] The encapsulation layer 7 commonly uses organic transparent materials including borosilicates, quartz, sapphire, cyclic olefin polymers, polymethyl methacrylate, polycarbonate, parylene, polysiloxane, polystyrene, and polyethylene oxide. Commonly used inorganic transparent materials include silicon dioxide, magnesium fluoride, aluminum oxide, magnesium oxide, silicon nitride, silicon oxynitride, and zirconium oxide.

[0170] In this embodiment, as Figure 1 , Figure 2 , Figure 3 , Figure 5 As shown, the photosensitive pixel element also includes a microlens 8 disposed above the encapsulation layer 7. The microlens 8 is located above the charge accumulation electrode 1 and the top electrode 3, and is used to collect light entering the on-chip microlens 8 onto the charge accumulation electrode 1.

[0171] In a photosensitive pixel element, the size of the microlens 8 in the xy plane is greater than or equal to the size of the charge accumulation electrode 1; in addition, the size of the microlens 8 in the xy plane is less than or equal to the size of the charge accumulation electrode 1, the distance between the charge accumulation electrode 1 and the signal readout electrode 2, and the distance between the charge accumulation electrode 1 and another adjacent charge accumulation electrode 1; it can be understood that the size of the microlens 8 is set between the signal readout electrode 2 and another adjacent charge accumulation electrode 1.

[0172] For example, the device structure of a photosensitive pixel element provided in this embodiment is as follows: Figure 5As shown, a color filter layer 15 is provided above the top electrode 3, with each color filter layer 15 corresponding to and covering a photosensitive pixel element below it; the encapsulation layer 7 covers the color filter layer 15; a microlens 8 can also be integrated above the color filter layer 15; each microlens 8 corresponding to and covering a photosensitive pixel element below it. In practice, the microlens 8 may not be necessary. The purpose of providing the microlens 8 is to focus the incident light onto the charge accumulation electrode 1, thereby improving photoelectric conversion efficiency.

[0173] In this invention, the substrate includes a circuit layer and a metal wiring layer; the photosensitive pixel element further includes a pixel readout circuit, which is integrated in the circuit layer of the substrate 11, and the signal readout electrode 2, the transmission control electrode 10 and the charge accumulation electrode 1 are all connected to the pixel readout circuit.

[0174] The floating diffusion node FD1, amplifying transistor TR2, reset transistor TR1, and select transistor TR3 constituting the pixel readout circuit can be configured and structured similarly to those of a conventional floating diffusion node, conventional amplifying transistor, conventional reset transistor, and conventional select transistor. Alternatively, other types of pixel readout circuits can be employed. The pixel readout circuit can be constructed using NMOS, PMOS, or CMOS circuitry.

[0175] In this embodiment, it should be noted that FD1 (floating diffusion node) is directly connected to the signal readout electrode 2 of the photosensitive pixel element. During reset, FD1 is reset to Vss or a level near it by TR1, which is in the on state. The reset transistor TR1 can be a P-type MOSTFET or an N-type MOSFET. During charge accumulation, electrons generated in the photoelectric conversion layer 4 are collected by the top electrode 3, and holes are transferred to the P-type thin-film semiconductor layer 5. This hole flow causes the potential of the P-type thin-film semiconductor layer 5 to rise. During the transmission gate opening period formed by the transmission control electrode 10 and the signal readout electrode 2, the charge in the P-type thin-film semiconductor layer 5 above the corresponding electrode 1 is transferred to FD1.

[0176] The signal readout electrode 2 is connected to the floating diffusion node FD1 via a first connecting metal pillar 202 and a first pad portion 202 disposed in the first interlayer dielectric layer 9.

[0177] The first connecting metal pillar, the second connecting metal pillar, and the third connecting metal pillar mentioned above can be formed by a single photolithography process, and the materials can be selected from W, Cu, Al, Ni, Ti, Au, etc.

[0178] The charge accumulation electrode 1 consists of a second connecting metal pillar 101 and a second pad portion 102 disposed within the first interlayer dielectric layer 9, and a wiring V OA Connected to the pixel readout circuit.

[0179] The transmission control electrode 10 is connected via a third connecting metal pillar 231, a third solder pad portion 232 and wiring V disposed in the first dielectric layer 9. OT Connected to the pixel readout circuit.

[0180] The top electrode 3 is connected via wiring V OU Connected to the pixel readout circuit, that is, the holes generated by photoelectric conversion are transmitted from the top electrode 3 through wiring V. OU The data is transmitted to the pixel readout circuit.

[0181] like Figure 6 As shown, during charge accumulation, the pixel readout circuit sets the first potential V... 11 Applying the second potential V to signal readout electrode 2 12 Apply to charge accumulation electrode 1, and set the third potential V 13 A positive potential is applied to the transmission control electrode 10; a positive potential is applied to the top electrode 3. When incident light is incident on the photoelectric conversion layer 4, the incident light undergoes photoelectric conversion in the photoelectric conversion layer 4. Electrons generated through photoelectric conversion are transmitted via wiring V. OU The signal is transmitted from the top electrode 3 to the pixel readout circuit. On the other hand, since the potential of the signal readout electrode 2 is set lower than that of the top electrode 3—in other words, for example, a negative potential is applied to the signal readout electrode 2 while a positive potential is applied to the top electrode 3—the potential relationship is set to V. 12 V 11 (For example, the potential satisfies the following relationship: V) 12 V 11 V 13 Therefore, the holes generated through photoelectric conversion are attracted by the charge accumulation electrode 1, and thus the holes remain in the region of the P-type thin-film semiconductor layer 5 facing the charge accumulation electrode 1. In other words, the holes are stored and accumulated in the P-type thin-film semiconductor layer 5. Due to V 12 V 13 This reliably prevents holes generated in the photoelectric conversion layer 4 from moving toward the signal readout electrode 2; that is, holes generated inside the photoelectric conversion layer 4 will not move toward the signal readout electrode 2. As photoelectric conversion proceeds, the potential of the region facing the charge accumulation electrode 1 of the P-type thin-film semiconductor layer 5 becomes a more positive value.

[0182] A reset operation is performed at the end of the charge accumulation period. Therefore, the potential of the floating diffusion node FD1 is reset, and the potential of the floating diffusion node FD1 becomes the potential Vss of the power source, or a potential in its vicinity.

[0183] Charge readout occurs after the reset operation is complete. In other words, during charge transfer, the fourth potential V is read out from the pixel readout circuit. 21 Applying the fifth potential V to signal readout electrode 2 22 Apply to charge accumulation electrode 1 and set the sixth potential V 23 An application is made to the transmission control electrode 10 to read out the holes accumulated in the P-type thin-film semiconductor layer 5 to the pixel readout circuit via the signal readout electrode 2. At this time, the potential satisfies the following relationship: V 22 V 23 V 21 In this way, holes remaining in the region of the P-type thin-film semiconductor layer 5 facing the charge accumulation electrode 1 are read out to the signal readout electrode 2, and further read out to the floating diffusion node FD1. In other words, the holes stored in the P-type thin-film semiconductor layer 5 are read out to the pixel readout circuit.

[0184] By including a dielectric layer 6 located between the charge accumulation electrode 1 and the signal readout electrode 2, the dielectric layer 6 can reduce the potential of the corresponding P-type thin film semiconductor layer 5, effectively confining holes to the region of the P-type thin film semiconductor layer 5 corresponding to the charge accumulation electrode 1, and also reducing circuit leakage.

[0185] In this embodiment, the charge accumulation electrode 1 is disposed separately from the signal readout electrode 2, and a dielectric layer 6 is also provided between the charge accumulation electrode 1 and its corresponding P-type thin-film semiconductor layer 5. Therefore, when light illuminates the photoelectric conversion unit and photoelectric conversion occurs in the photoelectric conversion unit, the P-type thin-film semiconductor layer 5, the dielectric layer 6, and the charge accumulation electrode 1 form a capacitor, allowing charge to be stored and accumulated in the N-type semiconductor layer 5. Therefore, at the start of exposure, the charge can be cleared by completely depleting the charge storage unit. Thus, the occurrence of phenomena such as increased KTC noise, random noise degradation, and image quality degradation during imaging can be suppressed. Furthermore, since all pixels can be reset at once, a global shutter function can be realized.

[0186] For the pixel readout circuit, a transistor TR4 can be connected in series between the reset transistor and the floating diffusion node to achieve gain adjustment.

[0187] Example 2

[0188] like Figure 7 As shown, this embodiment also provides an image sensor, including a plurality of photosensitive pixel elements 100 containing P-type thin-film transistor transmission gates as described in Embodiment 1, forming an image array. The photosensitive pixel element 100 includes:

[0189] Substrate 11;

[0190] The charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2 are located on the same side of the substrate 11 and reflect the incident light.

[0191] The dielectric layer 6 covers the charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2, and has an opening 201 at the position corresponding to the signal readout electrode 2.

[0192] A patterned single or double-layered P-type thin-film semiconductor layer 5 is located above the dielectric layer 6 and makes ohmic contact with the signal readout electrode 2 through the opening 201.

[0193] The photoelectric conversion layer 4 is located above the P-type thin film semiconductor layer 5 and is shared by each photosensitive pixel element in the image array;

[0194] The top electrode 3, which transmits incident light, is located above the photoelectric conversion layer 4 and is arranged opposite to the charge accumulation electrode 1, the transmission control electrode 10, and the signal readout electrode 2, and is shared by each photosensitive pixel element in the image array.

[0195] In this embodiment, the image array corresponding to the photosensitive pixel element 100 in the image sensor is, for example... Figure 8 The image shown is a top view of an image sensor array, which includes several photosensitive pixel elements containing P-type thin-film transistor transmission gates as described above. Figure 8 In the image array described above, the charge accumulation electrode 1, signal readout electrode 2, and transmission control electrode 10 of each photosensitive pixel element are independent of each other. At this time, the P-type thin film semiconductor layer 5 is patterned, and the photoelectric conversion layer 4, top electrode 3, etc. can be shared by multiple photosensitive pixel elements.

[0196] The device structure of the photosensitive pixel element 100 is described in detail in Embodiment 1, and will not be repeated here.

[0197] In this invention, the P-type thin-film semiconductor layers 5 in each photosensitive pixel element of the image array are independent of each other, that is, patterned P-type thin-film semiconductor layers 5; two adjacent P-type thin-film semiconductor layers 5 can be isolated by an insulating spacer layer. The material of the insulating spacer layer can be one of the dielectric layer materials listed above.

[0198] In addition, the image sensor described above may also include an N-type semiconductor layer 12 disposed between the photoelectric conversion layer 4 and the top electrode 3, wherein the N-type semiconductor layer 12 may be shared among the photosensitive pixel elements 100 in the image array.

[0199] In one specific embodiment, the photosensitive pixel element 100 further includes: a first SAM layer 13 disposed between the P-type thin-film semiconductor layer 5 and the photoelectric conversion layer 4, and / or a second SAM layer 14 disposed between the photoelectric conversion layer 4 and the top electrode 3. The first SAM layer 13 and the second SAM layer 14 can be configured to be shared among the individual photosensitive pixel elements 100 in the image array.

[0200] In one specific embodiment, a color filter array consisting of multiple color filter layers 15 is integrated above the top electrode 3, wherein each color filter layer 15 covers a photosensitive pixel element below it.

[0201] In one specific embodiment, a microlens array consisting of multiple microlenses 8 is integrated above the color filter layer array, wherein each microlens 8 covers a photosensitive pixel element below.

[0202] In one specific embodiment, a microlens array consisting of multiple microlenses 8 is integrated above the top electrode 3, wherein each microlens 8 covers a photosensitive pixel element below it.

[0203] That is, the photosensitive pixel element in the image sensor can be adopted as follows: Figures 1-8 Any device structure, or any combination of the photosensitive pixel element device structures listed in the present invention, falls within the protection scope of the present invention, and will not be listed one by one here.

[0204] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A photosensitive pixel element comprising a P-type thin film transistor pass gate, characterized by: The photosensitive pixel element comprises: a substrate (11); a charge accumulation electrode (1), a transfer control electrode (10), and a signal readout electrode (2) located on the same side of the substrate (11) and reflecting incident light; a dielectric layer (6) covering the charge accumulation electrode (1), the transfer control electrode (10), and the signal readout electrode (2) and having an opening part at a position corresponding to the signal readout electrode (2); a single-layer or double-layer P-type thin film semiconductor layer (5) located above the dielectric layer (6) and in ohmic contact with the signal readout electrode (2) through the opening part; a photoelectric conversion layer (4) located above the P-type thin film semiconductor layer (5); a top electrode (3) located above the photoelectric conversion layer (4) and arranged opposite to the charge accumulation electrode (1), the transfer control electrode (10), and the signal readout electrode (2).

2. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 1, characterized by: When the P-type thin film semiconductor layer (5) is a single-layer structure, the P-type thin film semiconductor layer (5) comprises an organic semiconductor material, an organic metal semiconductor material, or a metal compound semiconductor material.

3. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 2, characterized in that: The carrier concentration of the P-type thin film semiconductor layer (5) is 10 16 -10 19 hole / cm 3 , the hole mobility is higher than 10 -1 cm 2 / Vs, and the thickness is 5-100 nm.

4. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 1, characterized by: When the P-type thin film semiconductor layer (5) is a double-layer structure, the P-type thin film semiconductor layer (5) comprises a first P-type thin film semiconductor layer (501) located on the dielectric layer (6) and a second P-type thin film semiconductor layer (502) located on the first P-type thin film semiconductor layer (501).

5. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 4, characterized in that: The first P-type thin film semiconductor layer (501) comprises an organic semiconductor material, an organic metal semiconductor material, or a metal compound semiconductor material.

6. The photosensitive pixel element containing a P-type thin film transistor pass gate according to any one of claims 2 or 5, characterized in that: The organic semiconductor material comprises pentacene, rubrene, C6-DBTDT-C6, DBTDT, C10-BTBT-C10, C8-BTBT-C8, C6-BTBT-C6, BTBT, DPh-DNTT, PPCD, TBT, C6-TBT-C6; The organic metal semiconductor material comprises a metal-centered phthalocyanine complex; the metal comprises iron, cobalt, nickel, copper, zinc, tin, titanium, and combinations thereof; The metal compound semiconductor material comprises stannous oxide, cuprous oxide, copper sulfide, zinc selenide, nickel oxide, cuprous iodide, molybdenum disulfide, tellurium-selenium composite oxide; The metal compound semiconductor material further comprises YBa2Cu3O6, La2CuO4, (Bi, Pb)2Sr2CaCu2O8, and other non-doped or weakly doped oxide semiconductors containing a two-dimensional cuprous oxide layer that have superconductivity when doped with oxygen.

7. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 4, characterized in that: The second P-type thin film semiconductor layer (502) comprises one or more independently selected from an organic compound 2, an inorganic compound 2, or a combination thereof. The organic compound 2 includes one or more of 4,4'-cyclohexylbis[N,N'-di(4-methylphenyl)aniline], N,N'-bis(naphthalen-1-yl)-N,N'-bis(phenyl)-benzidine, N,N'-bis(naphthalen-1-yl)-N,N'-bis(phenyl)-2,7-diamino 9,9-spirobifluorene, 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene, 4,4',4"-tris(carbazol-9-yl)triphenylamine, poly(4-butyltriphenylamine), polyvinylcarbazole, polystyrene-N,N'-diphenyl-N,N'-bis-(3-methylphenyl)-(1,1)-biphenyl-4,4'-diamine perfluorocyclobutane, poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid), poly[bis(4-phenyl)(4-butylphenyl)amine]; The inorganic compound 2 includes tungsten oxide, molybdenum oxide, vanadium oxide, chromium oxide, nickel oxide, copper oxide, cuprous oxide, cuprous thiocyanate, copper sulfide, copper iodide, copper phthalocyanine, or a mixture or composite of the above materials.

8. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 4, characterized in that: The carrier concentration of the first P-type thin film semiconductor layer (501) is 10 16 -10 19 hole / cm 3 , and the hole mobility is higher than 10 -1 cm 2 / Vs, and the thickness is 5-100 nm. The carrier concentration of the second P-type thin film semiconductor layer (502) is 10 16 -10 18 hole / cm 3 , the hole mobility is higher than 10 -3 cm 2 / Vs, and the thickness is 5-20 nm.

9. The photosensitive pixel element containing a P-type thin film transistor pass gate according to any one of claims 1 to 8, characterized in that: The light-sensing pixel element further comprises an N-type semiconductor layer (12) between the photoelectric conversion layer (4) and the top electrode (3).

10. The photosensitive pixel element containing a P-type thin film transistor pass gate according to any one of claims 1 to 8, characterized in that: The light-sensing pixel element further comprises a first SAM layer (13) disposed between the P-type thin film semiconductor layer (5) and the photoelectric conversion layer (4), and / or a second SAM layer (14) disposed between the photoelectric conversion layer (4) and the top electrode (3).

11. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 10, wherein: The first SAM layer (13) comprises carbazole molecules containing phosphonic acid or carboxyl anchoring groups, aromatic amine molecules, fluorene, or thiophene.

12. The photosensitive pixel element containing a P-type thin film transistor pass gate according to claim 10, wherein: The second SAM layer (14) comprises fullerene with hydrophilic groups, aromatic groups or aromatic heterocyclic groups, aliphatic chains, or metal-quinolinol salts; the hydrophilic groups include carboxyl, hydroxyl, amino, amine groups; an alkylthiol monolayer containing amide groups.

13. An image sensor, comprising: The light-sensing pixel element comprising a P-type thin film transistor transmission gate according to any one of claims 1-12 forms an image array, and the light-sensing pixel element comprises: a substrate (11); a charge accumulation electrode (1), a transmission control electrode (10), and a signal readout electrode (2) on the same side of the substrate (11) and reflecting incident light; a dielectric layer (6) covering the three electrodes (1, 10, 2) and having an opening (201) at the position corresponding to the signal readout electrode (2); a patterned single-layer or double-layer P-type thin film semiconductor layer (5) on the dielectric layer (6) and in ohmic contact with the signal readout electrode (2) through the opening (201); a photoelectric conversion layer (4) on the P-type thin film semiconductor layer (5) and shared by each light-sensing pixel element in the image array; A top electrode (3) transmits incident light, is located above the photoelectric conversion layer (4), and is arranged opposite the charge accumulation electrode (1), the transfer control electrode (10), and the signal readout electrode (2), and is shared among the individual light-sensitive pixel elements in the image array.

14. The image sensor of claim 13, wherein: The light-sensitive pixel element further comprises an N-type semiconductor layer (12) (21) between the photoelectric conversion layer (4) and the top electrode (3), and is shared among the individual light-sensitive pixel elements in the image array.

15. The image sensor of claim 13, wherein: A color filter layer array composed of a plurality of color filter layers (15) is integrated above the top electrode (3), wherein each color filter layer (15) corresponds to cover an underlying light-sensitive pixel element.

16. The image sensor of claim 15, wherein: A microlens array composed of a plurality of microlenses (8) is integrated above the color filter layer array, wherein each microlens (8) corresponds to cover an underlying light-sensitive pixel element.

17. The image sensor of claim 13, wherein: A microlens array composed of a plurality of microlenses (8) is integrated above the top electrode (3), wherein each microlens (8) corresponds to cover an underlying light-sensitive pixel element.

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