A seven-cells based two-node flip flop self-restoring latch

Abstract

The present application mainly aims at solving the problems of large area overhead, high power consumption and difficulty in realizing double-node self-recovery of the existing self-recovery latch, and discloses a double-node flip self-recovery latch based on seven C cells, which comprises a double-loop structure storage module and three transmission gates, and the double-loop structure storage module is composed of seven two-input C cells and two inverters. The present application has high reliability, can tolerate any double-node flip and can be completely self-recovered, and improves the tolerance capacity of the latch; uses fewer MOS tubes, reduces the area overhead and power consumption overhead; there is only one transmission gate between the input end and the output end, the path is more efficient, and the transmission delay is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit anti-interference technology, specifically to a dual-node flip-and-recovery latch based on seven C cells. Background Technology

[0002] With the rapid development of hardware technology, integrated circuits have gradually entered a new era. Nanotechnology is no longer a novelty, and the requirements for transistors have become increasingly stringent, most notably in terms of transistor size. Nanoscale transistors have enabled significant advancements in integrated circuits in terms of area and power consumption. However, this has also created some disadvantages. For example, space radiation can interfere with integrated circuits, causing soft errors during operation. Soft errors refer to changes in the logic state of circuit nodes due to external interference, primarily from high-energy particles in space radiation, such as neutrons, alpha particles, protons, heavy ions, and electrons.

[0003] In the field of radiation hardening techniques for circuits, most researchers tend to focus on modifying the circuit design because latches have a relatively simple structure compared to complex internal logic. However, with nanoscale technology, latches operate in complex environments for extended periods. When interference immunity is high, single-node or even multi-node flipping can occur in the latch, leading to malfunctions. Therefore, hardening the circuit while simultaneously improving its interference immunity is crucial.

[0004] From the current technological perspective, many latches can achieve single-node self-recovery, while multi-node self-recovery implementations are relatively rare. These multi-node implementations generally suffer from two problems: first, most self-recovery latches have large area overhead and high power consumption; second, when two nodes undergo logic flipping, it is difficult for the latch to achieve simultaneous self-recovery for both nodes, thus preventing normal operation. Therefore, this will be a significant challenge for designers. Summary of the Invention

[0005] This invention primarily addresses the problems of existing self-recovering latches, such as large area overhead, high power consumption, and difficulty in achieving simultaneous self-recovery of two nodes. It provides a dual-node flip-flop self-recovering latch based on seven C-cells, comprising a dual-loop structure storage module and three transmission gates. The dual-loop structure storage module consists of seven two-input C-cells and two inverters. This invention offers high reliability, tolerates arbitrary dual-node flip-flops, and can fully self-recover, improving the latch's tolerance capability. It uses fewer MOSFETs, reducing area and power overhead. With only one transmission gate between the input and output terminals, the path is more efficient, reducing transmission delay.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A dual-node flip-and-recovery latch based on seven C-cells includes a dual-loop structure storage module and three transmission gates. The dual-loop structure storage module consists of seven two-input C-cells and two inverters. The seven two-input C-cells include a first C-cell CE1, a second C-cell CE2, a third C-cell CE3, a fourth C-cell CE4, a fifth C-cell CE5, a sixth C-cell CE6, and a seventh C-cell CE7. The two inverters include a first inverter T1 and a second inverter T2. The three transmission gates include a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3. The input terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are all used as the data input terminals D of the latch, and the output terminals of the sixth C-cell CE6 and the third transmission gate TG3 are all used as the data output terminals of the latch. This invention offers high reliability, tolerates arbitrary dual-node flipping and is fully self-recovering, improving latch tolerance and providing superior performance. It uses fewer MOS transistors, reducing area and power consumption compared to existing latches. It also features low latency because in transparent mode, there is only one transmission gate between the input and output, establishing a more efficient path and thus resulting in low transmission delay.

[0008] Preferably, the first input terminal of the first C unit CE1 is connected to the output terminal N2 of the second C unit CE2, the second input terminal of the first C unit CE1 is connected to the output terminal N4 of the fourth C unit CE4, and the output terminal N1 of the first C unit CE1 is connected to the second input terminal of the sixth C unit CE6; the first input terminal of the second C unit CE2 is connected to the output terminal N7 of the seventh C unit CE7, the second input terminal of the second C unit CE2 is connected to the output terminal N5 of the fifth C unit CE5, and the output terminal N2 of the second C unit CE2 is also connected to the first input terminal of the third C unit CE3; the second input terminal of the third C unit CE3 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N3 of the third C unit CE3 is connected to... The second input terminal of the fourth C unit CE4 is connected to the input terminal of the second inverter T2; the first input terminal of the fourth C unit CE4 is connected to the output terminal N7 of the seventh C unit CE7, and the output terminal N4 of the fourth C unit CE4 is also connected to the first input terminal of the fifth C unit CE5; the second input terminal of the fifth C unit CE5 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N5 of the fifth C unit CE5 is also connected to the input terminal of the first inverter T1; the first input terminal of the sixth C unit CE6 is connected to the output terminal N7 of the seventh C unit CE7; the first input terminal of the seventh C unit CE7 is connected to the output terminal of the second inverter T2, and the second input terminal of the seventh C unit CE7 is connected to the output terminal of the first inverter T1. For the dual-loop structure storage module of this invention, if the input terminal of the next C unit connected to each C unit within the loop is not fed back, the output terminal of that C unit feeds back to the input terminals of these C units that need to be fed back, until all the corresponding input terminals of all C units within the loop have been fed back. Finally, all input terminals of all C units receive feedback, achieving cyclic interlocking.

[0009] Preferably, the output terminal of the first transmission gate TG1 is connected to the first input terminal of the first C unit CE1 and the first input terminal of the third C unit CE3, respectively; the output terminal of the second transmission gate TG2 is connected to the second input terminal of the first C unit CE1 and the first input terminal of the fifth C unit CE5, respectively; and the output terminal of the third transmission gate TG3 is connected to the second input terminal of the fifth C unit CE5 and the second input terminal of the third C unit CE3, respectively.

[0010] Preferably, the seven two-input C units have the same structure, each consisting of two PMOS transistors and two NMOS transistors.

[0011] Preferably, the C unit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2; wherein, the gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and the connection point is the first input terminal of the C unit; the gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2, and the connection point is the second input terminal of the C unit; the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2; the drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1, and the connection point is the output terminal of the C unit; the source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2; the source of the first PMOS transistor MP1, the substrate of the first PMOS transistor MP1, and the substrate of the second PMOS transistor MP2 are all connected to the power supply VDD; the substrate of the first NMOS transistor MN1, the substrate of the second NMOS transistor MN2, and the source of the second NMOS transistor MN2 are all grounded.

[0012] Preferably, the three transmission gates have the same structure, each consisting of a PMOS transistor and an NMOS transistor.

[0013] Preferably, the transmission gate includes a third PMOS transistor MP3 and a third NMOS transistor MN3; wherein the source of the third PMOS transistor MP3 is connected to the source of the third NMOS transistor MN3, and the connection point is the input terminal of the transmission gate; the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and the connection point is the output terminal of the transmission gate; the gate of the third NMOS transistor MN3 is connected to the system clock signal CLK, and the gate of the third PMOS transistor MP3 is connected to the inverted system clock signal NCK.

[0014] Preferably, when the system clock signal CLK = 0 and the reverse system clock signal NCK = 1, the output terminal N6 of the sixth C unit CE6 serves as the data output terminal of the latch; when the system clock signal CLK = 1 and the reverse system clock signal NCK = 0, the output terminal of the third transmission gate TG3 serves as the data output terminal of the latch.

[0015] Preferably, the two inverters have the same structure, each consisting of a PMOS transistor and an NMOS transistor.

[0016] Preferably, the inverter includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4; wherein the gate of the fourth PMOS transistor MP4 and the gate of the fourth NMOS transistor MN4 are connected, and the connection point is the output terminal N3 of the third C unit CE3; the drain of the fourth PMOS transistor MP4 and the drain of the fourth NMOS transistor MN4 are connected, and the connection point is the second input terminal of the seventh C unit CE7; the source and the substrate of the fourth PMOS transistor MP4 are both connected to the power supply VDD; the source and the substrate of the fourth NMOS transistor MN4 are both grounded.

[0017] Therefore, the advantages of the present invention are:

[0018] (1) High reliability, can tolerate arbitrary double node flipping and can fully self-recover, which improves the latch tolerance and has superior performance;

[0019] (2) Using fewer MOSFETs reduces area overhead and power consumption compared to existing latches;

[0020] (3) It has low latency. In transparent mode, there is only one transmission gate between the input and output, which establishes a more efficient path, so the transmission latency is low. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a dual-node flip-and-recovery latch based on seven C units in an embodiment of the present invention.

[0022] Figure 2 This is a circuit diagram of the three transmission gates in an embodiment of the present invention.

[0023] Figure 3 This is a circuit schematic diagram of unit C in an embodiment of the present invention.

[0024] Figure 4 This is a circuit diagram of the inverter in an embodiment of the present invention.

[0025] 1. Dual-loop storage module 2. Transmission gate. Detailed Implementation

[0026] The present invention will now be further described with reference to the accompanying drawings and specific embodiments.

[0027] A dual-node flip-flop self-recovery latch based on seven C units, such as Figure 1As shown, the device includes a dual-loop structure storage module 1 and three transmission gates 2. The dual-loop structure storage module 1 consists of seven two-input C units and two inverters. The seven two-input C units include a first C unit CE1, a second C unit CE2, a third C unit CE3, a fourth C unit CE4, a fifth C unit CE5, a sixth C unit CE6, and a seventh C unit CE7. The two inverters include a first inverter T1 and a second inverter T2. The three transmission gates include a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3. The input terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are all used as the data input terminals D of the latch, and the output terminals of the sixth C unit CE6 and the third transmission gate TG3 are all used as the data output terminals of the latch.

[0028] like Figure 1 As shown, the first input terminal of the first C unit CE1 is connected to the output terminal N2 of the second C unit CE2, the second input terminal of the first C unit CE1 is connected to the output terminal N4 of the fourth C unit CE4, and the output terminal N1 of the first C unit CE1 is connected to the second input terminal of the sixth C unit CE6; the first input terminal of the second C unit CE2 is connected to the output terminal N7 of the seventh C unit CE7, the second input terminal of the second C unit CE2 is connected to the output terminal N5 of the fifth C unit CE5, and the output terminal N2 of the second C unit CE2 is also connected to the first input terminal of the third C unit CE3; the second input terminal of the third C unit CE3 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N3 of the third C unit CE3 is connected to... The second input terminal of the fourth C unit CE4 is connected to the input terminal of the second inverter T2; the first input terminal of the fourth C unit CE4 is connected to the output terminal N7 of the seventh C unit CE7, and the output terminal N4 of the fourth C unit CE4 is also connected to the first input terminal of the fifth C unit CE5; the second input terminal of the fifth C unit CE5 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N5 of the fifth C unit CE5 is also connected to the input terminal of the first inverter T1; the first input terminal of the sixth C unit CE6 is connected to the output terminal N7 of the seventh C unit CE7; the first input terminal of the seventh C unit CE7 is connected to the output terminal of the second inverter T2, and the second input terminal of the seventh C unit CE7 is connected to the output terminal of the first inverter T1. For the dual-loop structure storage module of this embodiment, if the input terminal of the next C unit connected to each C unit within the loop is not fed back, the output terminal of that C unit feeds back to the input terminals of these C units that need to be fed back, until all the corresponding input terminals of all C units within the loop have been fed back. Finally, all input terminals of all C units receive feedback, achieving cyclic interlocking.

[0029] like Figure 1As shown, the output of the first transmission gate TG1 is connected to the first input of the first C unit CE1 and the first input of the third C unit CE3, respectively; the output of the second transmission gate TG2 is connected to the second input of the first C unit CE1 and the first input of the fifth C unit CE5, respectively; and the output of the third transmission gate TG3 is connected to the second input of the fifth C unit CE5 and the second input of the third C unit CE3, respectively.

[0030] The seven two-input C units have the same structure, each consisting of two PMOS transistors and two NMOS transistors.

[0031] like Figure 3 As shown, cell C includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and the connection point is the first input terminal of cell C. The gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2, and the connection point is the second input terminal of cell C. The drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1, and the connection point is the output terminal of cell C. The source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2. The source of the first PMOS transistor MP1, the substrate of the first PMOS transistor MP1, and the substrate of the second PMOS transistor MP2 are all connected to the power supply VDD. The substrate of the first NMOS transistor MN1, the substrate of the second NMOS transistor MN2, and the source of the second NMOS transistor MN2 are all grounded.

[0032] The truth table for the two input C units (first C unit CE1 to seventh C unit CE7) is shown in Table 1 below:

[0033] Table 1 Truth Table for Input Unit C

[0034]

[0035] As shown in the table, for a two-input C unit, when the logic values ​​of the first and second inputs are the same, the output will output a logic value opposite to the input; when the logic values ​​of the first and second inputs are different, the output will enter a hold state, outputting the logic value from the previous state. Therefore, two-input C units (CE1 to CE7) can be used to mask the logic value flipping of nodes, preventing the flipping of some logic values ​​at the inputs from propagating to the output. When the logic values ​​of both inputs flip, the logic value of the output will also flip. Therefore, the logic value of the output will only return to its original value when the logic values ​​of both inputs have returned to their original values.

[0036] The three transmission gates have the same structure, each consisting of a PMOS transistor and an NMOS transistor.

[0037] The transmission gates include the third PMOS transistor MP3 and the third NMOS transistor MN3; such as Figure 2 As shown, the source of the third PMOS transistor MP3 is connected to the source of the third NMOS transistor MN3, and the connection point is the input terminal of the transmission gate; the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and the connection point is the output terminal of the transmission gate; the gate of the third NMOS transistor MN3 is connected to the system clock signal CLK, and the gate of the third PMOS transistor MP3 is connected to the inverted system clock signal NCK.

[0038] When the system clock signal CLK = 0 and the inverted system clock signal NCK = 1, the output terminal N6 of the sixth C unit CE6 serves as the data output terminal of the latch; when the system clock signal CLK = 1 and the inverted system clock signal NCK = 0, the output terminal of the third transmission gate TG3 serves as the data output terminal of the latch.

[0039] The two inverters have the same structure, each consisting of a PMOS transistor and an NMOS transistor.

[0040] like Figure 4 As shown, the inverter includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4; the gates of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected at the output terminal N3 of the third C unit CE3; the drains of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected at the second input terminal (Na3) of the seventh C unit CE7; the source and substrate of the fourth PMOS transistor MP4 are both connected to the power supply VDD; the source and substrate of the fourth NMOS transistor MN4 are both grounded.

[0041] The normal operating principle of the latch proposed in this invention will be explained below.

[0042] When CLK = 1 and NCK = 0, the structure operates in transparent mode. At this time, the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are turned on, and N2, N4, and N6 (Q) are initialized to the value of D. The previously initialized nodes are then determined by the C unit. Figure 1 The values ​​of nodes N1, N3, N5, and N7 are initialized, meaning all nodes are initialized.

[0043] When CLK = 0 and NCK = 1, the latch operates in latching mode. The first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are closed. Therefore, N2 is determined by the output of the second C unit CE2, N4 by the output of the fourth C unit CE4, and N6(Q) by the output of the sixth C unit CE6. Since the values ​​of nodes N1, N3, N5, and N7 are initialized in transparent mode, in the dual-loop storage module, nodes N2, N4, and N6(Q) feed back to nodes N1, N3, and N5 through three two-input C units; nodes N3 and N5 feed back to node N7 through one two-input C unit; and nodes N3, N5, and N7 feed back to nodes N2, N4, and N6(Q) through three two-input C units. This cyclic feedback forms several feedback loops. Therefore, the latch can effectively store data. In summary, the latch functions normally.

[0044] The fault-tolerant working principle of the latch proposed in this invention will be explained below. First, the case of internal two-node flip (DNU) will be discussed. Based on the symmetry and cyclic feedback rule of this latch, it can be seen that the outer and inner loops can be considered of the same type, and each node within the loop has the same status. Therefore, only the following two representative cases need to be considered:

[0045] (1) Both nodes experience DNU simultaneously, and they are on the same ring;

[0046] (2) DNU occurs simultaneously on two nodes, one of which is on one ring and the other is on another ring;

[0047] Before analyzing the fault-tolerance principle, let's first introduce three properties:

[0048] Property 1: For any two-input C unit, when all its inputs are correct values, it will output the correct value regardless of whether its output is affected.

[0049] Property 2: For any two-input C unit, when one of its inputs is flipped and its output is not flipped, it will still output the correct value;

[0050] Property 3: For any two-input C unit, when both of its inputs are flipped, it will output an incorrect value; when one of its inputs and output are flipped simultaneously, it will retain the incorrect output. In this case, it is necessary to restore all the flipped inputs first, and then it will output the correct value.

[0051] Regarding the case of (1), due to the cyclic characteristics of the dual-loop storage module, the critical DNU sequence can be selected.<N5,N7> ,<N4,N5> ;

[0052] when<N5,N7> When a DNU occurs, the second C unit CE2 satisfies property 3, the fourth C unit CE4, the sixth C unit CE6, and the seventh C unit CE7 satisfy property 2, and the other C units satisfy property 1. Therefore, all C units except the second C unit CE2 can output the correct value. Obviously, the fourth C unit CE4 and the sixth C unit CE6 will output the correct value, so N5 first restores its original value. Subsequently, the third C unit CE3 and the fifth C unit CE5 output the correct value, and N7 restores its original value. Similarly, N2 also restores to its original value, i.e.<N5,N7> It can be recovered from DNU;

[0053] when<N4,N5> When a DNU occurs, the fifth C unit CE5 satisfies Property 3, the first C unit CE1, the second C unit CE2, and the seventh C unit CE7 satisfy Property 2, and the other C units satisfy Property 1. Therefore, all C units except the fifth C unit CE5 can output the correct value. Obviously, the third C unit CE3 and the seventh C unit CE7 will output the correct value, so N4 will be restored to its original value first. Similarly, N5 can also be restored to its original value, i.e.<N4,N5> It can be recovered from DNU;

[0054] Analysis shows that this latch can achieve the DNU self-recovery function in this situation.

[0055] Regarding scenario (2), due to the cyclic characteristics of the dual-loop storage module, a critical DNU sequence can be selected.<N2, N5> ,<N3,N4> ,<N6,N7> ;

[0056] when<N2,N5> When a DNU occurs, the second C unit CE2 satisfies property 3, the first C unit CE1, the third C unit CE3, and the seventh C unit CE7 satisfy property 2, and the other C units satisfy property 1. Therefore, all C units except the second C unit CE2 can output the correct value. Obviously, the outputs of the third C unit CE3 and the fifth C unit CE5 are still the original values, so N7 is restored to its original value. Similarly, N2 is restored to its original value, i.e.<N2,N5> It can be recovered from DNU;

[0057] when<N3,N4> When a DNU occurs, the fourth C unit CE4 satisfies property 3, the first C unit CE1, the fifth C unit CE5, and the seventh C unit CE7 satisfy property 2, and the other C units satisfy property 1. Therefore, all C units except the fourth C unit CE4 can output the correct value. Obviously, the outputs of the third C unit CE3 and the fifth C unit CE5 are still the original values, so N7 is restored to its original value. Similarly, N4 is restored to its original value, i.e.<N3,N4> It can be recovered from DNU;

[0058] when<N6,N7> When a DNU occurs, the sixth C unit CE6 satisfies property 3, the second C unit CE2, the third C unit CE3, the fourth C unit CE4, and the fifth C unit CE5 satisfy property 2, and all other C units satisfy property 1. Clearly, the third C unit CE3 and the fifth C unit CE5 will output the correct values, so N7 is restored to its original value first. Similarly, N6 is restored to its original value, i.e.<N6,N7> It can be recovered from DNU;

[0059] Analysis shows that this latch can achieve the DNU self-recovery function in this situation.

[0060] As can be seen from the above analysis, this latch is completely self-recoverable when any two nodes flip, and obviously a single node flip must also be self-recoverable.

[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A seven-C-element based two-node flip flop self-restoring latch, characterized by, The device includes a dual-loop storage module and three transmission gates. The dual-loop storage module consists of seven two-input C units and two inverters. The seven two-input C units are: CE1, CE2, CE3, CE4, CE5, CE6, and CE7. The two inverters are: T1 and T2. The three transmission gates are: TG1, TG2, and TG3. The inputs of TG1, TG2, and TG3 serve as data inputs to the latch, and the outputs of CE6 and TG3 serve as data outputs to the latch. The first input terminal of the first C unit CE1 is connected to the output terminal N2 of the second C unit CE2, the second input terminal of the first C unit CE1 is connected to the output terminal N4 of the fourth C unit CE4, and the output terminal N1 of the first C unit CE1 is connected to the second input terminal of the sixth C unit CE6; the first input terminal of the second C unit CE2 is connected to the output terminal N7 of the seventh C unit CE7, the second input terminal of the second C unit CE2 is connected to the output terminal N5 of the fifth C unit CE5, and the output terminal N2 of the second C unit CE2 is also connected to the first input terminal of the third C unit CE3; the second input terminal of the third C unit CE3 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N3 of the third C unit CE3 is connected to the fourth C unit CE4; the second input terminal of the third C unit CE3 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N3 of the third C unit CE3 is connected to the fourth C unit CE4; The second input terminal of unit CE4 is connected to the input terminal of the second inverter T2; the first input terminal of the fourth C unit CE4 is connected to the output terminal N7 of the seventh C unit CE7, and the output terminal N4 of the fourth C unit CE4 is also connected to the first input terminal of the fifth C unit CE5; the second input terminal of the fifth C unit CE5 is connected to the output terminal N6 of the sixth C unit CE6, and the output terminal N5 of the fifth C unit CE5 is also connected to the input terminal of the first inverter T1; the first input terminal of the sixth C unit CE6 is connected to the output terminal N7 of the seventh C unit CE7; the first input terminal of the seventh C unit CE7 is connected to the output terminal of the second inverter T2, and the second input terminal of the seventh C unit CE7 is connected to the output terminal of the first inverter T1; The C unit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2; wherein, the gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and the connection point is the first input terminal of the C unit; the gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2, and the connection point is the second input terminal of the C unit; the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2; the drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1, and the connection point is the output terminal of the C unit; the source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2; the source of the first PMOS transistor MP1, the substrate of the first PMOS transistor MP1, and the substrate of the second PMOS transistor MP2 are all connected to the power supply VDD; the substrate of the first NMOS transistor MN1, the substrate of the second NMOS transistor MN2, and the source of the second NMOS transistor MN2 are all grounded; The three transmission gates have the same structure, each consisting of a PMOS transistor and an NMOS transistor. The two inverters have the same structure, each consisting of a PMOS transistor and an NMOS transistor.

2. A seven-C-element based two-node flip flop self-restoring latch according to claim 1, wherein, The output of the first transmission gate TG1 is connected to the first input of the first C unit CE1 and the first input of the third C unit CE3, respectively; the output of the second transmission gate TG2 is connected to the second input of the first C unit CE1 and the first input of the fifth C unit CE5, respectively; and the output of the third transmission gate TG3 is connected to the second input of the fifth C unit CE5 and the second input of the third C unit CE3, respectively.

3. The seven-C-element based two-node flip flop self-restoring latch according to claim 1, wherein, The transmission gate includes a third PMOS transistor MP3 and a third NMOS transistor MN3; wherein, the source of the third PMOS transistor MP3 is connected to the source of the third NMOS transistor MN3, and the connection point is the input terminal of the transmission gate; the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and the connection point is the output terminal of the transmission gate; the gate of the third NMOS transistor MN3 is connected to the system clock signal CLK, and the gate of the third PMOS transistor MP3 is connected to the inverted system clock signal NCK.

4. A seven-C-element based two-node flip-around self-restoring latch according to claim 3, wherein, When the system clock signal CLK = 0 and the reverse system clock signal NCK = 1, the output terminal N6 of the sixth C unit CE6 serves as the data output terminal of the latch. When the system clock signal CLK = 1 and the reverse system clock signal NCK = 0, the output of the third transmission gate TG3 serves as the data output of the latch.

5. The seven-C-element based two-node flip flop self-restoring latch of claim 1, wherein, The inverter includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4; wherein, the gate of the fourth PMOS transistor MP4 and the gate of the fourth NMOS transistor MN4 are connected, and the connection point is the output terminal N3 of the third C unit CE3; the drain of the fourth PMOS transistor MP4 and the drain of the fourth NMOS transistor MN4 are connected, and the connection point is the second input terminal of the seventh C unit CE7; the source and the substrate of the fourth PMOS transistor MP4 are both connected to the power supply VDD; the source and the substrate of the fourth NMOS transistor MN4 are both grounded.

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