Latch performance detection method and device, and electronic equipment
By measuring the equivalent resistance of the latch, the problem of unstable circuit performance of the latch in the metastable state was solved, and accurate judgment and performance improvement were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-29
- Publication Date
- 2026-06-26
AI Technical Summary
The latch cannot determine the output state in a metastable state, resulting in unstable circuit performance.
By extracting the circuit structure information of the latch, a simulation circuit is established, and the resistance value of the equivalent resistance is measured to determine whether it is greater than the resistance threshold, thus determining the metastable state.
Accurately determine whether the latch is in a metastable state to improve circuit performance.
Smart Images
Figure CN117012263B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a latch performance testing method, apparatus, and electronic device. Background Technology
[0002] A latch is a type of memory cell circuit that is sensitive to pulse levels; it can change its state in response to a specific input pulse level.
[0003] When designing and using latches, the larger the resistance between the drive terminal and the latch terminal, the weaker the drive capability will be, which will cause the latch to be in a metastable state.
[0004] When the latch is in a metastable state, it is impossible to determine whether the output state of the latch is "1" or "0". This unknown state makes the internal state of the latch-related circuits unstable and unable to perform the latching function, thus affecting the performance of the circuit. Summary of the Invention
[0005] This disclosure provides a latch performance testing method, apparatus, and electronic device that can accurately detect whether a latch is in a metastable state, which helps to improve circuit performance.
[0006] In a first aspect, embodiments of this disclosure provide a latch performance testing method, including:
[0007] Extract the circuit structure information of the latch under test. The latch includes a transmission gate and a latching unit. The output terminal of the transmission gate is coupled to the input terminal of the latching unit. The input terminal of the transmission gate is coupled to the output terminal of the corresponding driving unit of the latch.
[0008] The equivalent resistance value of the latch is determined based on the circuit structure information. The first end of the equivalent resistance is the output end of the drive unit, and the second end of the equivalent resistance is the input end of the latch unit.
[0009] The latching performance of the latch is determined based on the resistance value of the equivalent resistance.
[0010] In one feasible implementation, determining the resistance value of the equivalent resistance of the latch based on the circuit structure information includes:
[0011] Based on the circuit structure information, a simulation circuit is established, which includes a parasitic semiconductor device between the output terminal of the driving unit and the input terminal of the latch unit.
[0012] The simulation circuit was tested to determine the value of the equivalent resistance.
[0013] In one feasible implementation, a simulation circuit is established based on the circuit structure information, including:
[0014] Receive a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device;
[0015] Based on the circuit structure information and the first file, the simulation circuit is established.
[0016] In one feasible implementation, the simulation circuit includes the transmission gate.
[0017] In one feasible implementation, the simulation circuit is tested to determine the resistance value of the equivalent resistance, including:
[0018] A working voltage is applied to the output terminal of the drive unit, and a working current is measured at the input terminal of the latch unit to determine the resistance value of the equivalent resistor.
[0019] In one feasible implementation, determining the latching capability of the latch based on the resistance value of the equivalent resistance includes:
[0020] Determine the resistance threshold corresponding to the driving unit;
[0021] Determine whether the resistance value of the equivalent resistance is greater than the resistance threshold. If the resistance value of the equivalent resistance is greater than the resistance threshold, then determine that the latch is in a metastable state.
[0022] In one feasible implementation, determining the resistance threshold corresponding to the driving unit includes:
[0023] Receive a second file, the second file including the resistance threshold corresponding to the driving unit.
[0024] In one feasible implementation, the driving unit includes an inverter, which includes an NMOS transistor and a PMOS transistor, and the output terminal of the driving unit is a drain port shared by the NMOS transistor and the PMOS transistor.
[0025] In one feasible implementation, before extracting the circuit structure information of the latch under test, the method further includes:
[0026] Receive a third file, which includes circuit structure information of multiple latches under test;
[0027] The extraction of circuit structure information of the latch under test includes:
[0028] Extract the circuit structure information of all latches under test from the third file.
[0029] Secondly, embodiments of this disclosure provide a latch performance testing device, comprising:
[0030] An extraction module is used to extract the circuit structure information of the latch under test. The latch includes a transmission gate and a latching unit. The output terminal of the transmission gate is coupled to the input terminal of the latching unit, and the input terminal of the transmission gate is coupled to the output terminal of the corresponding driving unit of the latch.
[0031] The test module is used to determine the resistance value of the equivalent resistance of the latch based on the circuit structure information. The first end of the equivalent resistance is the output end of the drive unit, and the second end of the equivalent resistance is the input end of the latch unit.
[0032] The judgment module is used to determine the latching performance of the latch based on the resistance value of the equivalent resistance.
[0033] In one feasible implementation, the testing module is specifically used for:
[0034] Based on the circuit structure information, a simulation circuit is established, which includes a parasitic semiconductor device between the output terminal of the driving unit and the input terminal of the latch unit.
[0035] The simulation circuit was tested to determine the value of the equivalent resistance.
[0036] In one feasible implementation, the testing module is specifically used for:
[0037] Receive a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device;
[0038] Based on the circuit structure information and the first file, the simulation circuit is established.
[0039] In one feasible implementation, the simulation circuit includes the transmission gate.
[0040] In one feasible implementation, the testing module is specifically used for:
[0041] A working voltage is applied to the output terminal of the drive unit, and a working current is measured at the input terminal of the latch unit to determine the resistance value of the equivalent resistor.
[0042] In one feasible implementation, the determination module is specifically used for:
[0043] Determine the resistance threshold corresponding to the driving unit;
[0044] Determine whether the resistance value of the equivalent resistance is greater than the resistance threshold. If the resistance value of the equivalent resistance is greater than the resistance threshold, then determine that the latch is in a metastable state.
[0045] In one feasible implementation, the determination module is specifically used for:
[0046] Receive a second file, the second file including the resistance threshold corresponding to the driving unit.
[0047] In one feasible implementation, the driving unit includes an inverter, which includes an NMOS transistor and a PMOS transistor, and the output terminal of the driving unit is a drain port shared by the NMOS transistor and the PMOS transistor.
[0048] In one feasible implementation, the extraction module is further configured to:
[0049] Receive a third file, which includes circuit structure information of multiple latches under test;
[0050] Extract the circuit structure information of all latches under test from the third file.
[0051] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;
[0052] The memory stores computer-executed instructions;
[0053] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the latch performance detection method as provided in the first aspect.
[0054] The latch performance testing method, apparatus, and electronic device provided in this disclosure include: determining the equivalent resistance value of the latch by extracting the circuit structure information of the latch under test. Since the equivalent resistance value can accurately represent the resistance value between the drive terminal and the latch terminal of the latch, it is possible to accurately determine whether the latch under test is in a metastable state based on the equivalent resistance value, thereby improving the circuit performance. Attached Figure Description
[0055] Figure 1 This is a schematic diagram of the structure of a latch performance testing system provided in an embodiment of this disclosure;
[0056] Figure 2 This is a schematic diagram of the structure of a transmission gate provided in an embodiment of this disclosure;
[0057] Figure 3 This is a schematic diagram of the structure of a latch unit provided in an embodiment of this disclosure;
[0058] Figure 4 This is a flowchart illustrating the steps of a latch performance testing method provided in this embodiment. Figure 1 ;
[0059] Figure 5 This is a flowchart illustrating the steps of a latch performance testing method provided in this embodiment. Figure 2 ;
[0060] Figure 6 This is a schematic diagram of a simulation circuit provided in an embodiment of this application;
[0061] Figure 7 This is a schematic diagram of the structure of a driving unit 10 provided in an embodiment of this application;
[0062] Figure 8 This is a schematic diagram of the program modules of a latch performance testing device provided in an embodiment of this disclosure;
[0063] Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.
[0065] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.
[0066] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.
[0067] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.
[0068] The term "module" as used in the embodiments of this disclosure refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.
[0069] This disclosure relates to a rapid detection method for latch performance, which can quickly detect whether a latch is in a metastable state.
[0070] For example, the embodiments of this disclosure can be applied to the design of Dynamic Random Access Memory (DRAM), but are not limited to this scope. When designing and using latch modules, the latch performance testing method provided in the embodiments of this disclosure can be used to test the latch module.
[0071] A latch is a storage circuit that is sensitive to pulse levels, and it can change its state under the influence of a specific input pulse level. Latching is the process of temporarily storing a signal to maintain a certain level state; in digital circuits, it can record binary digital signals "0" and "1".
[0072] The functions of latches generally include buffering, solving the asynchrony problem between high-speed controllers and slow peripherals, solving driver problems, and solving the problem of an input / output port being able to both output and input.
[0073] When designing and using latches, the larger the resistance between the drive terminal and the latch terminal, the weaker the drive capability will be, which will cause the latch to be in a metastable state.
[0074] When the latch is in a metastable state, it is impossible to determine whether the output state of the latch is "1" or "0". This unknown state makes the internal state of the latch-related circuits unstable and unable to perform the latching function, thus affecting the performance of the circuit.
[0075] To address the aforementioned technical problems, this disclosure provides a latch performance testing method. By extracting the circuit structure information of the latch under test, the equivalent resistance value of the latch is determined. Since the equivalent resistance value can accurately represent the resistance value between the drive terminal and the latch terminal of the latch, it is possible to accurately determine whether the latch under test is in a metastable state based on the equivalent resistance value, thereby improving the circuit performance.
[0076] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a latch performance testing system provided in an embodiment of this disclosure.
[0077] In some embodiments of this disclosure, the latch performance testing system includes a drive unit 10 and a latch under test 20. The latch under test 20 includes a transmission gate 201 and a latching unit 202. The output terminal of the transmission gate 201 is coupled to the input terminal of the latching unit 202, and the input terminal of the transmission gate 201 is coupled to the output terminal of the drive unit 10.
[0078] In some embodiments of this disclosure, the above coupling methods include direct connection, indirect connection, telecommunication connection and signal communication connection, etc., and no limitation is made in the embodiments of this disclosure.
[0079] In some embodiments of this disclosure, the driving unit 10 includes a complementary metal-oxide-semiconductor (CMOS) inverter, which can make the output obtain a logic value opposite to the input.
[0080] In some embodiments of this disclosure, the transmission gate 201 may employ a transmission gate structure. A transmission gate is a controllable switching circuit capable of transmitting both digital and analog signals.
[0081] For example, the transmission gate 201 described above may include an N-type metal-oxide-semiconductor (NMOS) transistor and a PMOS transistor (positive channel metal-oxide-semiconductor). It has a very low on-resistance (several hundred ohms) and a very high cutoff resistance (greater than 10^9 ohms).
[0082] In this configuration, NMOS is turned on at high voltage and PMOS is turned on at low voltage. That is, when the gate voltage is low, NMOS is turned off and PMOS is turned on; when the gate voltage is high, NMOS is turned on and PMOS is turned off.
[0083] To better understand the embodiments of this application, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of a transmission gate provided in an embodiment of this disclosure.
[0084] exist Figure 2 In the diagram, C and / C are complementary control signals. The sources and drains of the PMOS and NMOS transistors are interconnected, and the structure is symmetrical. Therefore, the input (U) IOutput (U) O They can be used interchangeably.
[0085] When C=1, / C=0, input U I From 0-V DD When the voltage changes, at least one of the PMOS and NMOS transistors is turned on. The gate g of the PMOS transistor is at a low voltage, and the gate g of the NMOS transistor is at a high voltage. The input and output resistances are low.
[0086] When C=0, / C=1, the gate g of the PMOS is at a low voltage, and the gate g of the NMOS is at a high voltage. Neither the PMOS nor the NMOS is turned on, and the input and output are in a high-impedance state.
[0087] That is, when C=1, / C=0, the transmission gate is turned on, U I =U O When C=0, / C=1, the transmission gate is not conducting, and the signal cannot be transmitted. Here, 0 refers to low voltage or ground, and 1 refers to high voltage or power supply voltage.
[0088] It should be noted that, Figure 2 The transmission gate structure shown is merely exemplary. In other embodiments of this disclosure, transmission gates of other structural types may also be used, and no limitation is imposed on the embodiments of this disclosure.
[0089] In some embodiments of this disclosure, the latch unit 202 typically consists of two inverters.
[0090] To better understand the embodiments of this application, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a latching unit provided in an embodiment of this disclosure.
[0091] exist Figure 3 In this latch unit 202, a first inverter 2021 and a second inverter 2022 are included. The input terminal of the first inverter 2021 is connected to the input signal IN, and the output terminal is connected to the input terminal of the second inverter 2022. The output terminal of the second inverter 2022 is connected to the input terminal of the first inverter 2021. The output terminal of the first inverter 2021 serves as the output terminal OUT of the latch unit 202.
[0092] In some embodiments of this disclosure, the input terminal of the first inverter 2021 serves as the input terminal of the latch unit 202, receiving the input signal IN. When the input signal is low, the first inverter 2021 inverts the low level to a high level and transmits the electrical signal to the second inverter 2022; the second inverter 2022 then inverts the electrical signal back to its original low level. When the input signal is high, the first inverter 2021 inverts the high level to a low level and transmits the electrical signal to the second inverter 2022, which inverts the electrical signal back to its original high level. The timing shift register of high and low levels is achieved through the output terminal of the first inverter 2021, i.e., the output terminal OUT of the latch unit 202.
[0093] In some embodiments of this disclosure, the resistance between the output terminal of the drive unit and the input terminal of the latch unit is an equivalent resistance R.
[0094] Reference Figure 4 , Figure 4 This is a flowchart illustrating the steps of a latch performance testing method provided in this embodiment. Figure 1 In some embodiments, the above-described latch performance testing method includes:
[0095] S401. Extract the circuit structure information of the latch under test.
[0096] In some embodiments of this disclosure, circuit structure information of all circuit structures related to the latch in the circuit where the latch under test is located can be extracted, including latch connection information, connection signals, etc.
[0097] S402. Determine the equivalent resistance value of the latch based on the above circuit structure information.
[0098] In some embodiments of this disclosure, after extracting the circuit structure information of the latch under test, parasitic modules can be matched based on the circuit structure information to establish a simulation circuit, and then the resistance value of the equivalent resistance can be measured based on the simulation circuit.
[0099] It is understandable that the establishment and measurement of the above simulation circuit are carried out through netlists and simulation software, without the need to build additional physical circuits.
[0100] The equivalent resistance value includes the parasitic resistance of the connection signal line between the output terminal of the drive unit and the input terminal of the latch unit, and the equivalent resistance of the transmission gate.
[0101] S403. Determine the latching performance of the latch based on the resistance value of the equivalent resistance.
[0102] Since the larger the resistance value between the drive end and the latch end, the less stable the latch is, in some embodiments of this disclosure, the latching performance of the latch can be determined based on the resistance value of the equivalent resistance.
[0103] For example, when the resistance value of the equivalent resistor is greater than a preset threshold, it can be determined that the latch is in a metastable state; when the resistance value of the equivalent resistor is less than or equal to the threshold, it can be determined that the latch is in a stable state.
[0104] The latch performance testing method provided in this embodiment extracts the circuit structure information of the latch under test to determine the equivalent resistance value of the latch. Since the equivalent resistance value can accurately represent the resistance value between the drive terminal and the latch terminal of the latch, it is possible to accurately determine whether the latch under test is in a metastable state based on the equivalent resistance value, thereby improving the circuit performance.
[0105] Based on the content described in the above embodiments, referring to Figure 5 , Figure 5 This is a flowchart illustrating the steps of a latch performance testing method provided in this embodiment. Figure 2 In some embodiments, the above-described latch performance testing method includes:
[0106] S501. Extract the circuit structure information of the latch under test.
[0107] In some embodiments of this disclosure, circuit structure information of all circuit structures related to the latch in the circuit where the latch under test is located can be extracted, including latch connection information, connection signals, etc.
[0108] S502. Determine the equivalent resistance value of the latch based on the above circuit structure information.
[0109] In some embodiments of this disclosure, a simulation circuit can be established based on the circuit structure information described above. This simulation circuit includes a parasitic semiconductor device between the output terminal of the driving unit and the input terminal of the latching unit.
[0110] In some embodiments of this disclosure, the above-described simulation circuit includes the aforementioned transmission gate.
[0111] In one feasible implementation, the method further includes receiving a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device, such as the resistance value and port information of the parasitic resistance of the signal line, the capacitance value and port information of the parasitic capacitance, etc.
[0112] In one feasible implementation, the simulation circuit can be established based on the circuit structure information and the first document described above.
[0113] To better understand the embodiments of this application, please refer to... Figure 6 , Figure 6 This is a schematic diagram of a simulation circuit provided in an embodiment of this application.
[0114] exist Figure 6 In the above simulation circuit, there are a driving unit 10, a transmission gate 201 and a latching unit 202. The output terminal of the transmission gate 201 is coupled to the input terminal of the latching unit 202, and the input terminal of the transmission gate 201 is coupled to the output terminal of the driving unit 10.
[0115] The simulation circuit includes parasitic semiconductor devices such as R1, C1, R2, C2, R3, and C3 between the output terminal of the drive unit 10 and the input terminal of the latch unit 202.
[0116] In addition, the above-mentioned transmission gate is also included in the simulation circuit.
[0117] In some embodiments of this disclosure, after the simulation circuit is established, the simulation circuit is tested to determine the resistance value of the equivalent resistor.
[0118] In one feasible implementation, the equivalent resistance R can be calculated by applying a working voltage V to the output terminal of the drive unit, measuring the working current I at the input terminal of the latch unit, and then calculating the resistance R based on the voltage V and the measured working current I. That is: R = V / I.
[0119] It is understood that the resistance value R of the above equivalent resistance is the sum of the equivalent resistances of the above parasitic semiconductor devices R1, R2, R3, and the above transmission gate.
[0120] S503. Determine the resistance threshold corresponding to the above driving unit.
[0121] It is understandable that, since different driving units have different driving capabilities, the corresponding resistance thresholds of different driving units will also be different.
[0122] For example, refer to Table 1, which is a schematic table of resistance thresholds for different drive units.
[0123] Table 1: Schematic table of resistance thresholds for different drive units
[0124] serial number drive unit Resistance threshold (Ω) 01 CDINVF1 100 02 CDINVF2 200 03 CDINVF4 300
[0125] In some embodiments of this disclosure, a second file may be received in advance before the latch performance is tested. This second file includes the resistance threshold corresponding to the aforementioned drive unit.
[0126] S504. Determine whether the resistance value of the above equivalent resistance is greater than the above resistance threshold.
[0127] In some embodiments of this disclosure, after detecting the resistance value of the equivalent resistance, it is determined whether the resistance value is greater than the resistance threshold. If the resistance value is greater than the resistance threshold, the latch is determined to be in a metastable state; otherwise, the latch is determined to be in a stable state.
[0128] The latch performance testing method provided in this disclosure extracts the circuit structure information of the latch under test to establish a simulation circuit, and then determines the equivalent resistance value by testing the simulation circuit. Since the equivalent resistance value accurately represents the resistance between the drive terminal and the latch terminal of the latch, it is possible to accurately determine whether the latch under test is in a metastable state based on the equivalent resistance value, thereby improving circuit performance.
[0129] Based on the content described in the above embodiments, in some embodiments of this disclosure, the driving unit 10 includes an inverter, which includes an NMOS transistor and a PMOS transistor, and the output terminal of the driving unit 10 is a drain port shared by the NMOS transistor and the PMOS transistor.
[0130] Among them, the NMOS transistor is an N-channel enhancement-mode MOS transistor that uses a P-type substrate. The source (S) and gate (G) circuits require a positive voltage for the output circuit to be turned on. In addition, the substrate needs to be connected to the source or to the lowest potential of the system.
[0131] PMOS transistors are P-channel enhancement-mode MOSFETs that use N-type substrates. The source (S) and gate (G) circuits require a negative voltage for the output circuit to turn on. In addition, the substrate needs to be connected to the source or to the highest potential of the system.
[0132] To better understand the embodiments of this application, please refer to... Figure 7 , Figure 7 This is a schematic diagram of the structure of a driving unit 10 provided in an embodiment of this application.
[0133] exist Figure 7 In the diagram, T1 is a P-channel enhancement-mode MOSFET, and T2 is an N-channel enhancement-mode MOSFET.
[0134] In some embodiments of this disclosure:
[0135] When v1 is low, T1 is on and T2 is off, resulting in a high output; when v1 is high, T2 is on and T1 is off, resulting in a low output.
[0136] In particular, since one of T1 and T2 is always cut off under static conditions, whether it is a high level or a low level, and the cut-off internal resistance is extremely high, the current flowing through it is extremely small, so the static power consumption of the CMOS inverter is very low.
[0137] It is understandable that the magnitude of parasitic resistance and capacitance is related to the frequency of the connection signal. Therefore, for registers, the parasitic resistance and capacitance corresponding to different connection signals will be different, and the driving units corresponding to different connection signals will also be different.
[0138] Based on the content described in the above embodiments, in some embodiments of this disclosure, the latching performance of multiple latches in a circuit can be tested in batches.
[0139] In one feasible implementation, the above-mentioned latch performance testing method includes:
[0140] Step 1: Receive a third file, which contains circuit structure information of multiple latches under test.
[0141] In some embodiments, the third file may include circuit structure information of all latches in the circuit.
[0142] Step 2: Extract the circuit structure information of the latch under test.
[0143] In some embodiments, the circuit structure information of all latches under test in the third file can be extracted one by one or in batches.
[0144] Step 3: Based on the circuit structure information of each latch under test, build the simulation circuit corresponding to each latch under test individually or in batches.
[0145] In some implementations, after extracting the circuit structure information of each latch under test, parasitic modules can be matched based on the circuit structure information of each latch under test, and simulation circuits corresponding to each latch under test can be built in batches. Then, the equivalent resistance value of each latch under test can be measured according to each simulation circuit.
[0146] The simulation circuit mentioned above includes a parasitic semiconductor device between the output terminal of the driving unit of the corresponding latch under test and the input terminal of the latch unit.
[0147] In addition, the simulation circuit mentioned above also includes the transmission gate corresponding to the latch under test.
[0148] It is understandable that the establishment and measurement of the above simulation circuits are carried out through netlists and simulation software, without the need to build additional physical circuits.
[0149] The equivalent resistance value of each latch under test includes the parasitic resistance of the connection signal line between the output terminal of the drive unit and the input terminal of the latch unit of each latch under test, and the equivalent resistance of the transmission gate.
[0150] In one feasible implementation, the method further includes receiving a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device, such as the resistance value and port information of the parasitic resistor, the capacitance value and port information of the parasitic capacitor, etc.
[0151] In one feasible implementation, simulation circuits for each latch under test can be established based on the circuit structure information of each latch under test and the aforementioned first document.
[0152] In one feasible implementation, after establishing the simulation circuits of each latch under test, the simulation circuits of each latch under test are tested one by one or in batches to determine the resistance value of the equivalent resistor in the simulation circuits of each latch under test.
[0153] In one feasible implementation, a working voltage V is applied to the output terminal of the drive unit of each latch under test, and the working current I is measured at the input terminal of the latch unit. Then, based on the voltage V and the measured working current I, the equivalent resistance R corresponding to each latch under test can be calculated. That is: R = V / I.
[0154] Step 3: Determine the resistance threshold of the driving unit corresponding to each of the above-mentioned latches under test.
[0155] It is understandable that the same latch may correspond to different drive units. Since different drive units have different driving capabilities and different resistance thresholds, the latching performance of the same latch may be different when different drive units are used.
[0156] In some embodiments of this disclosure, a second file may be received in advance before the latch performance is tested. This second file includes the resistance thresholds corresponding to each of the aforementioned drive units.
[0157] Step 4: Determine the latching performance of each latch under test.
[0158] Since the larger the resistance value between the driving end and the latching end, the more unstable the latch is, in some embodiments of this disclosure, the latching performance of each latch under test can be determined based on the resistance value of the equivalent resistor in the simulation circuit corresponding to each latch under test.
[0159] In some embodiments of this disclosure, when the resistance value of the equivalent resistor in the simulation circuit corresponding to a certain latch under test is greater than the resistance threshold value corresponding to its driving unit, it can be determined that the latch under test is in a metastable state; when the resistance value of the equivalent resistor in the simulation circuit corresponding to a certain latch under test is less than or equal to the resistance threshold value corresponding to its driving unit, it can be determined that the latch under test is in a stable state.
[0160] In some embodiments of this disclosure, batch measurement results can be recorded, and for latches in a metastable state, the results can be reported to the designer so that the designer can improve the latch.
[0161] For example, refer to Table 2, which is a record of latch performance testing when using batch measurement.
[0162] Table 2: Latch Performance Test Record Table During Batch Measurement
[0163]
[0164] The latch performance testing method provided in this disclosure can batch test whether multiple latches in a circuit are in a metastable state, thereby effectively improving the efficiency of latch performance testing.
[0165] Based on the content described in the above embodiments, this application also provides a latch performance testing device. (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of a program module for a latch performance testing device provided in an embodiment of this application. The latch performance testing device 80 includes:
[0166] Extraction module 801 is used to extract the circuit structure information of the latch under test. The latch includes a transmission gate and a latching unit. The output terminal of the transmission gate is coupled to the input terminal of the latching unit, and the input terminal of the transmission gate is coupled to the output terminal of the corresponding driving unit of the latch.
[0167] The test module 802 is used to determine the resistance value of the equivalent resistance of the latch based on the circuit structure information. The first end of the equivalent resistance is the output end of the drive unit, and the second end of the equivalent resistance is the input end of the latch unit.
[0168] The judgment module 803 is used to determine the latching performance of the latch based on the resistance value of the equivalent resistance.
[0169] The latch performance testing device provided in this embodiment of the present disclosure determines the equivalent resistance value of the latch by extracting the circuit structure information of the latch under test. Since the equivalent resistance value can accurately represent the resistance value between the drive terminal and the latch terminal of the latch, it is possible to accurately determine whether the latch under test is in a metastable state based on the equivalent resistance value, thereby improving the performance of the circuit.
[0170] In some embodiments, the test module 802 is specifically used for:
[0171] Based on the circuit structure information, a simulation circuit is established, which includes a parasitic semiconductor device between the output terminal of the driving unit and the input terminal of the latch unit.
[0172] The simulation circuit was tested to determine the value of the equivalent resistance.
[0173] In some embodiments, the test module 802 is specifically used for:
[0174] Receive a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device;
[0175] Based on the circuit structure information and the first file, the simulation circuit is established.
[0176] In some embodiments, the simulation circuit includes the transmission gate.
[0177] In some embodiments, the test module 802 is specifically used for:
[0178] A working voltage is applied to the output terminal of the drive unit, and a working current is measured at the input terminal of the latch unit to determine the resistance value of the equivalent resistor.
[0179] In some embodiments, the determination module 803 is specifically used for:
[0180] Determine the resistance threshold corresponding to the driving unit;
[0181] Determine whether the resistance value of the equivalent resistance is greater than the resistance threshold. If the resistance value of the equivalent resistance is greater than the resistance threshold, then determine that the latch is in a metastable state.
[0182] In some embodiments, the determination module 803 is specifically used for:
[0183] Receive a second file, the second file including the resistance threshold corresponding to the driving unit.
[0184] In some embodiments, the driving unit includes an inverter, which includes an NMOS transistor and a PMOS transistor, and the output terminal of the driving unit is the drain port of the NMOS transistor and the PMOS transistor.
[0185] In some embodiments, the extraction module 801 is further configured to:
[0186] Receive a third file, which includes circuit structure information of multiple latches under test;
[0187] Extract the circuit structure information of each latch under test from the third file.
[0188] It should be noted that the specific execution of the extraction module 801, the testing module 802, and the judgment module 803 in this embodiment can be found in the [reference needed]. Figures 1 to 7 The relevant content in the illustrated embodiments will not be repeated here.
[0189] Furthermore, based on the content described in the above embodiments, this application also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the latch performance detection method described in the above embodiments, which will not be repeated here.
[0190] To better understand the embodiments of this application, please refer to... Figure 9 , Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application.
[0191] like Figure 9 As shown, the electronic device 90 of this embodiment includes: a processor 901 and a memory 902; wherein:
[0192] Memory 902 is used to store instructions executed by the computer;
[0193] The processor 901 is used to execute computer execution instructions stored in the memory to implement the various steps in the latch performance detection method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.
[0194] Alternatively, the memory 902 can be either standalone or integrated with the processor 901.
[0195] When the memory 902 is set up independently, the device also includes a bus 903 for connecting the memory 902 and the processor 901.
[0196] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.
[0197] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0198] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.
[0199] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application.
[0200] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.
[0201] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.
[0202] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0203] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.
[0204] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.
[0205] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0206] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for testing latch performance, characterized in that, include: Extract the circuit structure information of the latch under test. The latch includes a transmission gate and a latching unit. The output terminal of the transmission gate is coupled to the input terminal of the latching unit. The input terminal of the transmission gate is coupled to the output terminal of the corresponding driving unit of the latch. The equivalent resistance value of the latch is determined based on the circuit structure information. The first end of the equivalent resistance is the output end of the drive unit, and the second end of the equivalent resistance is the input end of the latch unit. The latching performance of the latch is determined based on the resistance value of the equivalent resistance, including: Determine the resistance threshold corresponding to the driving unit; Determine whether the resistance value of the equivalent resistance is greater than the resistance threshold. If the resistance value of the equivalent resistance is greater than the resistance threshold, then determine that the latch is in a metastable state.
2. The method according to claim 1, characterized in that, Determining the equivalent resistance value of the latch based on the circuit structure information includes: Based on the circuit structure information, a simulation circuit is established, which includes a parasitic semiconductor device between the output terminal of the driving unit and the input terminal of the latch unit. The simulation circuit was tested to determine the value of the equivalent resistance.
3. The method according to claim 2, characterized in that, Based on the circuit structure information, a simulation circuit is established, including: Receive a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device; Based on the circuit structure information and the first file, the simulation circuit is established.
4. The method according to claim 2, characterized in that, The simulation circuit includes the transmission gate.
5. The method according to claim 4, characterized in that, The simulation circuit is tested to determine the value of the equivalent resistance, including: A working voltage is applied to the output terminal of the drive unit, and a working current is measured at the input terminal of the latch unit to determine the resistance value of the equivalent resistor.
6. The method according to claim 1, characterized in that, Determining the resistance threshold corresponding to the driving unit includes: Receive a second file, the second file including the resistance threshold corresponding to the driving unit.
7. The method according to claim 1, characterized in that, The driving unit includes an inverter, which includes an NMOS transistor and a PMOS transistor. The output terminal of the driving unit is the drain port of the NMOS transistor and the PMOS transistor.
8. The method according to claim 1, characterized in that, Before extracting the circuit structure information of the latch under test, the process also includes: Receive a third file, which includes circuit structure information of multiple latches under test; The extraction of circuit structure information of the latch under test includes: Extract the circuit structure information of all latches under test from the third file.
9. A latch performance testing device, characterized in that, include: An extraction module is used to extract the circuit structure information of the latch under test. The latch includes a transmission gate and a latching unit. The output terminal of the transmission gate is coupled to the input terminal of the latching unit, and the input terminal of the transmission gate is coupled to the output terminal of the corresponding driving unit of the latch. The test module is used to determine the resistance value of the equivalent resistance of the latch based on the circuit structure information. The first end of the equivalent resistance is the output end of the drive unit, and the second end of the equivalent resistance is the input end of the latch unit. The judgment module is used to determine the latching performance of the latch based on the resistance value of the equivalent resistance; The judgment module is specifically used for: Determine the resistance threshold corresponding to the driving unit; Determine whether the resistance value of the equivalent resistance is greater than the resistance threshold. If the resistance value of the equivalent resistance is greater than the resistance threshold, then determine that the latch is in a metastable state.
10. The apparatus according to claim 9, characterized in that, The testing module is specifically used for: Based on the circuit structure information, a simulation circuit is established, which includes a parasitic semiconductor device between the output terminal of the driving unit and the input terminal of the latch unit. The simulation circuit was tested to determine the value of the equivalent resistance.
11. The apparatus according to claim 10, characterized in that, The testing module is specifically used for: Receive a first file, which includes parasitic parameter information and connection information of the parasitic semiconductor device; Based on the circuit structure information and the first file, the simulation circuit is established.
12. The apparatus according to claim 10, characterized in that, The simulation circuit includes the transmission gate.
13. The apparatus according to claim 12, characterized in that, The testing module is specifically used for: A working voltage is applied to the output terminal of the drive unit, and a working current is measured at the input terminal of the latch unit to determine the resistance value of the equivalent resistor.
14. The apparatus according to claim 9, characterized in that, The judgment module is specifically used for: Receive a second file, the second file including the resistance threshold corresponding to the driving unit.
15. The apparatus according to claim 9, characterized in that, The driving unit includes an inverter, which includes an NMOS transistor and a PMOS transistor. The output terminal of the driving unit is the drain port of the NMOS transistor and the PMOS transistor.
16. The apparatus according to claim 9, characterized in that, The extraction module is also used for: Receive a third file, which includes circuit structure information of multiple latches under test; Extract the circuit structure information of all latches under test from the third file.
17. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the latch performance testing method as described in any one of claims 1 to 8.