Low-power-consumption dual-node flipping-resistant latch
By combining the SRC self-recovery unit with the clocked C unit, a simplified redundant architecture is used to solve the problem of multi-node flipping of traditional latches under modern nanotechnology, thus realizing a low-power, high-performance latch design that resists dual-node flipping.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN UNIV OF TECH
- Filing Date
- 2025-06-06
- Publication Date
- 2026-05-19
AI Technical Summary
Traditional single-node flip-up ruggedization designs cannot effectively address the challenges of multi-node flip-up in modern nanotechnology. Existing designs suffer from issues such as large area overhead, high power consumption, and long latency, making it difficult to meet the demands of high-performance, low-power applications.
A simplified redundant architecture combining an SRC self-recovery unit and a clock-controlled C unit is adopted. The single-node flip self-recovery is achieved through a feedback loop, which dynamically manages redundant paths, reduces the number of redundant nodes, and activates the critical path only in transparent mode through clock control of the feedback loop. Combined with the dynamic switching characteristics of the clock-controlled C unit, power consumption and transmission latency are reduced.
It significantly reduces the latch area and dynamic power consumption, reduces the number of redundant nodes, reduces invalid signal transmission and leakage current, and improves the circuit's radiation resistance and performance.
Smart Images
Figure CN224264956U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of digital integrated circuit design technology, and mainly to a low-power anti-dual-node flip-flop latch. Background Technology
[0002] As semiconductor process dimensions continue to shrink, the sensitivity of integrated circuits to single-event effects (SEE) has increased significantly. Soft errors such as single-event upsets (SEUs) and single-event transients (SETs) have become one of the main factors affecting the stability of highly reliable electronic systems, especially in extreme radiation environments such as aerospace and nuclear energy. Traditional single-node switching (SNU) hardened designs, such as dual interlocked memory cells (DICEs), can no longer meet the requirements of multi-node switching (MNUs) in modern nanoscale processes. Due to charge-sharing effects, high-energy particle impacts can cause adjacent nodes to flip simultaneously, i.e., dual-node switching (DNUs), which further exacerbates the soft error rate of circuits. In recent years, hardened designs for DNUs have become a research hotspot. Existing methods are mainly based on structures such as Muller C-element (MCE), DICEs, and Schmitt flip-flops (STs). MCEs block error propagation through high impedance states, but their floating output states can lead to system-level errors; DICE extended structures suffer from long feedback loop activation times and high power consumption; the radiation resistance of ST structures is limited by the transistor ratio, making it difficult to maintain stability in deep submicron processes. In addition, existing designs generally suffer from problems such as large area overhead, high power consumption, and long latency, making it difficult to meet the needs of high-performance, low-power applications. Utility Model Content
[0003] To address the above problems, this application provides a low-power, dual-node-flip latch, characterized by comprising:
[0004] The input module includes a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate arranged in parallel. The common input terminal of the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate is connected to the input terminal of the latch.
[0005] The anti-dual-node flipping module includes a first path consisting of a first transmission gate, a second transmission gate, and an SRC self-recovery unit, and a second path consisting of a second transmission gate, a third transmission gate, and a first C unit; the SRC self-recovery unit includes a second C unit and at least two cross-coupled feedback loops, each feedback loop including a cascaded inverter, a C unit, and a transmission gate;
[0006] The output module includes a clock control C unit. The two input terminals of the clock control C unit are connected to the output terminals of the first path and the second path, respectively. The output terminal of the fourth transmission gate TG4 and the output terminal of the clock control C unit MCE are connected in parallel to the output terminal Q of the latch.
[0007] The above technical solution employs a simplified redundancy architecture combining a self-recovering SRC unit and a clocked C-unit. The SRC unit achieves single-node flip-over (SNU) self-recovery through a feedback loop, while the clocked C-unit dynamically manages redundant paths, reducing the number of redundant nodes. Ultimately, only 38 transistors are required (39.4% less than DNURL), significantly reducing the area (3.54 μm). 2 This reduces power consumption by 59% compared to DNURL and dynamic power consumption by 0.7672μW (87.3% lower than DNURL). Secondly, traditional designs suffer from high static power consumption due to numerous static feedback loops or complex redundant structures. This structure controls the feedback loop via a clock, activating the critical path only in transparent mode, reducing invalid signal transmission and leakage current. Combined with the dynamic switching characteristics of the clocked C-cell, dynamic power consumption is significantly reduced (25.08% better than HLDTL). Furthermore, the second path formed by the first C-cell can quickly combine logic paths, reducing transmission delay. Additionally, the combination of C-cells and transmission gates in the SRC self-recovery unit further reduces power consumption and transmission delay.
[0008] Preferably, the SRC self-recovery unit includes a first inverter, a second inverter, a third C-cell, a fifth transmission gate, a fourth C-cell, a sixth transmission gate, and a second C-cell. The input of the first inverter is connected to the output of the first transmission gate, and the input of the second inverter is connected to the output of the second transmission gate. The two inputs of the second C-cell are respectively connected to the outputs of the first and second transmission gates, and its output serves as the output of the SRC self-recovery unit. The two inputs of the third C-cell are respectively connected to the outputs of the first inverter and the second C-cell, and its output is connected to the input of the fifth transmission gate. The output of the fifth transmission gate is connected to the output of the second transmission gate. The two inputs of the fourth C-cell are respectively connected to the outputs of the second inverter and the second C-cell, and its output is connected to the input of the sixth transmission gate. The output of the sixth transmission gate is connected to the output of the first transmission gate. The SRC self-recovery unit can eliminate the SNU through a feedback loop, achieving complete SNU immunity. Simultaneously, combining the C-cell and transmission gate in the SRC self-recovery unit reduces power consumption and transmission delay.
[0009] Preferably, the gates of the PMOS transistors of the fifth and sixth transmission gates are connected to the system clock, and the gates of the NMOS transistors of the fifth and sixth transmission gates are connected to the inverted system clock.
[0010] Preferably, the gates of the PMOS transistors of the first, second, third, and fourth transmission gates are connected to the inverted system clock, and the gates of the NMOS transistors of the first, second, third, and fourth transmission gates are connected to the system clock. Through a clock-controlled feedback loop, the critical path is activated only in transparent mode, reducing invalid signal transmission and leakage current.
[0011] Preferably, the C unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The gate of the first PMOS transistor is connected to the first input terminal, its source is connected to the power supply terminal, and its drain is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor is connected to the second input terminal, and its drain is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the first input terminal, and its source is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the second input terminal, and its source is grounded. The C unit achieves self-recovery functionality through a redundant structure and a mutual feedback mechanism.
[0012] Preferably, the clock-controlled C unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gate of the third PMOS transistor is connected to the system clock, its source is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the output of the SRC self-recovery unit, and its drain is connected to the source of the fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the output of the first C unit, and its drain is connected to the drain of the third NMOS transistor and the output of the latch. The gate of the third NMOS transistor is connected to the output of the first C unit, and its source is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the output of the SRC self-recovery unit, and its source is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the inverting system clock, and its source is grounded. The clock-controlled C unit controls the operating mode of the circuit (such as sleep and activation) through the clock signal, significantly reducing leakage current power consumption.
[0013] Compared with the prior art, the beneficial effects of this utility model are as follows:
[0014] A simplified redundancy architecture combining a self-recovering SRC unit and a clocked C-unit is adopted. The SRC unit achieves single-node flip-over (SNU) self-recovery through a feedback loop, while the clocked C-unit dynamically manages redundant paths, reducing the number of redundant nodes. Ultimately, only 38 transistors are required (39.4% less than DNURL), significantly reducing the area (3.54 μm). 2This reduces power consumption by 59% compared to DNURL and dynamic power consumption by 0.7672μW (87.3% lower than DNURL). Secondly, traditional designs suffer from high static power consumption due to numerous static feedback loops or complex redundant structures. This structure controls the feedback loop via a clock, activating the critical path only in transparent mode, reducing invalid signal transmission and leakage current. Combined with the dynamic switching characteristics of the clocked C-cell, dynamic power consumption is significantly reduced (25.08% improvement over HLDTL). Furthermore, the second path, composed of the first C-cell, allows for rapid combination of logic paths, reducing transmission delay. The integration of C-cells and transmission gates in the SRC self-recovery unit further reduces power consumption and transmission delay. Attached Figure Description
[0015] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the present invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.
[0016] Figure 1 This is a circuit diagram of a low-power anti-dual-node flip-flop latch according to an embodiment of this utility model;
[0017] Figure 2 This is a circuit diagram of unit C of an embodiment of this utility model;
[0018] Figure 3 This is a circuit diagram of the clock control C unit according to an embodiment of the present invention;
[0019] Figure 4 This is a comparison chart of simulation parameters for similar latches.
[0020] Explanation of reference numerals in the attached diagram: 100, Input module; 200, Anti-dual node flipping module; 210, SRC self-recovery unit; 300, Output module. Detailed Implementation
[0021] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate illustrative specific embodiments in which the present invention may be practiced. In this regard, directional terms such as “left,” “right,” “up,” “down,” etc., are used with reference to the orientation of the described figures. Because components of the embodiments can be positioned in several different orientations, directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
[0022] This invention proposes a low-power latch that resists dual-node flip-flop operation. Figure 1 This is a circuit diagram of a low-power anti-dual-node flip-flop latch according to an embodiment of this utility model. (Refer to...) Figure 1 ,include:
[0023] The input module 100 includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, and a fourth transmission gate TG4 arranged in parallel. The common input terminal of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 is connected to the input terminal DATA of the latch.
[0024] The anti-dual-node flipping module 200 includes a first path consisting of a first transmission gate TG1 and a second transmission gate TG2 connected to an SRC self-recovery unit 210, and a second path consisting of a second transmission gate TG2 and a third transmission gate TG3 connected to a first C unit CE1; the SRC self-recovery unit 210 includes a second C unit CE2 and at least two cross-coupled feedback loops, each feedback loop including a cascaded inverter, a C unit and a transmission gate;
[0025] The output module 300 includes a clock control unit MCE. The two input terminals of the clock control unit MCE are connected to the output terminals of the first path and the second path, respectively. The output terminal of the fourth transmission gate TG4 is connected in parallel with the output terminal of the clock control unit MCE to the output terminal Q of the latch.
[0026] The proposed latch is based on C-cells, ensuring SNU self-recovery capability. The latch's anti-dual-node-flipping characteristic is primarily achieved by the SRC self-recovery unit 210 and the first C-cell CE1. The SRC self-recovery unit 210 can eliminate SNUs through its feedback loop, achieving complete SNU immunity. Through integration with the clocked C-cell MCE, the latch further achieves DNU tolerance. The second path, composed of the first C-cell, enables rapid combination of logic paths, reducing transmission latency.
[0027] Specifically, the SRC self-recovery unit 210 includes a first inverter I1, a second inverter I2, a third C-cell CE3, a fifth transmission gate TG5, a fourth C-cell CE4, a sixth transmission gate TG6, and a second C-cell CE2. The input terminal of the first inverter I1 is connected to the output terminal of the first transmission gate TG1, and the input terminal of the second inverter I2 is connected to the output terminal of the second transmission gate TG2. The two input terminals of the second C-cell CE2 are respectively connected to the output terminals of the first transmission gate TG1 and the second transmission gate TG2, and the output terminal serves as the SRC self-recovery unit. The output terminals of SRC self-recovery unit 210 are as follows: The two input terminals of the third C unit CE3 are connected to the output terminals of the first inverter I1 and the second C unit CE2, respectively. The output terminal of CE3 is connected to the input terminal of the fifth transmission gate TG5, and the output terminal of TG5 is connected to the output terminal of the second transmission gate TG2. The two input terminals of the fourth C unit CE4 are connected to the output terminals of the second inverter I2 and the second C unit CE2, respectively. The output terminal of CE4 is connected to the input terminal of the sixth transmission gate TG6, and the output terminal of TG6 is connected to the output terminal of the first transmission gate TG1. The two input terminals of the clock-controlled C unit MCE are connected to the output terminals of the first C unit CE1 and the second C unit CE2, respectively. The output terminals of the clock-controlled C unit MCE and the fourth transmission gate TG4 are connected in parallel to the output terminal Q of the latch. SRC self-recovery unit 210 can eliminate SNU through a feedback loop, achieving complete SNU immunity. Furthermore, combining C units and transmission gates in SRC self-recovery unit 210 reduces power consumption and transmission delay, resulting in lower power consumption and transmission delay compared to using clock-controlled C units.
[0028] Specifically, Figure 2 This is a circuit diagram of unit C of an embodiment of this utility model, for reference. Figure 2 Unit C includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The gate of the first PMOS transistor P1 is connected to the first input terminal A, the source is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor P2. The gate of the second PMOS transistor P2 is connected to the second input terminal B, and the drain is connected to the drain of the first NMOS transistor N1. The gate of the first NMOS transistor N1 is connected to the first input terminal A, and the source is connected to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is connected to the second input terminal B, and its source is grounded (GND). Unit C achieves self-recovery functionality through a redundant structure and a mutual feedback mechanism.
[0029] As an example, the first C unit CE1 of the latch has its first input terminal A connected to the output terminal of the second transmission gate TG2, and its second input terminal B connected to the output terminal of the third transmission gate TG3; the CE3 inside the SRC self-recovery unit 210 has its first input terminal A connected to the output terminal of the first inverter I1, and its second input terminal B connected to the output terminal of the second C unit CE2.
[0030] It should be noted that in the latch circuit, the input is DATA, the output is Q, CK is the system clock, and NCK is the inverted system clock.
[0031] Specifically, Figure 3 This is a circuit diagram of the clock control C unit according to an embodiment of this utility model, for reference. Figure 3 The clock-controlled C unit includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The gate of the third PMOS transistor P3 is connected to the system clock CK, its source is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor P4. The gate of the fourth PMOS transistor P4 is connected to the output of the SRC self-recovery unit 210, i.e., the output of the second C unit CE2, and its drain is connected to the source of the fifth PMOS transistor P5. The fifth PMOS transistor P5... The gate of transistor N5 is connected to the output of the first C unit CE1, and its drain is connected to the drain of the third NMOS transistor N3 and the output Q of the latch. The gate of the third NMOS transistor N3 is connected to the output of the first C unit CE1, and its source is connected to the drain of the fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 is connected to the output of the SRC self-recovery unit 210, i.e., the output of the second C unit CE2, and its source is connected to the drain of the fifth NMOS transistor N5. The gate of the fifth NMOS transistor N5 is connected to the inverting system clock NCK, and its source is grounded. The clock-controlled C unit MCE controls the operating mode of the circuit (such as sleep and activation) through the clock signal, significantly reducing leakage current power consumption.
[0032] Specifically, the gates of the PMOS transistors of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are connected to the inverted system clock NCK; the gates of the NMOS transistors of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are connected to the system clock CK; the gates of the PMOS transistors of the fifth transmission gate TG5 and the sixth transmission gate TG6 are connected to the system clock CK, and the gates of the NMOS transistors of the fifth transmission gate TG5 and the sixth transmission gate TG6 are connected to the inverted system clock NCK. Through the clock control feedback loop, the critical path is activated only in transparent mode, reducing invalid signal transmission and leakage current.
[0033] The principle of the low-power anti-dual-node-flip latch in this embodiment is as follows:
[0034] When the system clock CK is high and the inverted system clock NCK is low, the latch operates in transparent mode. DATA is pre-charged to each node of the circuit through the transmission gates and output to Q through the last transmission gate. When the system clock CK is low and the inverted system clock NCK is high, the latch operates in hold mode. In this stage, the input to the SRC self-recovery unit 210 is the pre-charged value DATA from the transparent mode, and the output is driven by the second C unit CE2 within the SRC self-recovery unit 210. Then, the outputs of the SRC self-recovery unit 210 and the first C unit CE1 are fed into the clocked C unit MCE to generate the final output Q.
[0035] The tolerance of latch circuits to DNU can be divided into two cases;
[0036] First case: Dual-node flipping within the SRC self-recovery unit 210 (e.g.,<S1,S2> ,<S1,S4> ,<S2,S4> In this case, all internal nodes of the SRC self-recovery unit 210 will toggle. However, the clocked C unit MCE of the output stage only receives a toggle input, allowing it to retain its previous logic state. This effectively neutralizes the SNU propagated from the SRC self-recovery unit 210. Therefore, the DNU in case one has no effect on the output.
[0037] The second scenario: a single node flips inside the SRC self-recovery unit 210 and another critical node flips externally (e.g.,<S1,S3> ,<S1,S5> ,<S3,S4> ,<S4,S5> ,<S2,S3> ,<S2,S5> For external flips (such as S2 and S3), the first C unit CE1 between S2, S3, and S5 ensures that a single SNU on S2 or S3 will not propagate to S5. Even if S2 and S3 flip simultaneously, errors on S5 will be blocked by the clocked C unit MCE, thus maintaining the correct output Q. Therefore, the latch is fully tolerant of this type of DNU.
[0038] The above technical solution employs a simplified redundant architecture combining the SRC self-recovery unit 210 and the clock-controlled C unit MCE. The SRC self-recovery unit 210 achieves single-node flip (SNU) self-recovery through a feedback loop, while the clock-controlled C unit MCE dynamically manages redundant paths, reducing the number of redundant nodes. Figure 4 This is a comparison chart of simulation parameters for similar latches, for reference. Figure 4 Ultimately, only 38 transistors are needed (39.4% less than DNURL), significantly reducing the area (3.54 μm). 2This reduces power consumption by 59% compared to DNURL and dynamic power consumption by 0.7672μW (87.3% lower than DNURL). Secondly, traditional designs suffer from high static power consumption due to numerous static feedback loops or complex redundant structures. This structure controls the feedback loop via a clock, activating the critical path only in transparent mode, reducing invalid signal transmission and leakage current. Combined with the dynamic switching characteristics of the clocked C-cell (MCE), dynamic power consumption is significantly reduced (25.08% better than HLDTL). Furthermore, the second path, composed of the first C-cell, allows for rapid combination of logic paths, reducing transmission delay. Simultaneously, the integration of C-cells and transmission gates in the SRC self-recovery unit further reduces power consumption and transmission delay.
[0039] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a module or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a module or device. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the module or device that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.
[0040] In this application, the terms “connection,” “coupling,” or any variations thereof mean any direct or indirect connection or coupling between elements, and may encompass the presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element. Coupling and / or connection between elements can be physical, logical, or a combination thereof. As adopted herein, elements can be “connected” or “coupled” together by using one or more wires, cables, and / or printed circuits, and by using electromagnetic energy. Electromagnetic energy can have wavelengths in the radio frequency region, microwave region, and / or light (both visible and invisible) region. The examples above are non-limiting and non-exhaustive.
[0041] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0042] Obviously, those skilled in the art can make various modifications and changes to the embodiments of this utility model without departing from the spirit and scope of this utility model. In this way, this utility model is also intended to cover such modifications and changes if they fall within the scope of the claims of this utility model and their equivalents. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are described in mutually different dependent claims does not indicate that a combination of these measures cannot be used for profit. Any reference numerals in the claims should not be considered as limiting the scope.
Claims
1. A low-power, dual-node-flip latch, characterized in that, include: The input module includes a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate arranged in parallel, and the common input terminal of the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate is connected to the input terminal of the latch; The anti-dual-node flipping module includes a first path consisting of a first transmission gate, a second transmission gate, and an SRC self-recovery unit, and a second path consisting of a second transmission gate, a third transmission gate, and a first C unit; the SRC self-recovery unit includes a second C unit and at least two cross-coupled feedback loops, each of which includes a cascaded inverter, a C unit, and a transmission gate; The output module includes a clock control C unit, the two input terminals of which are respectively connected to the output terminals of the first path and the second path, and the output terminal of the fourth transmission gate is connected in parallel with the output terminal of the clock control C unit to the output terminal of the latch.
2. The low-power anti-dual-node-flip latch according to claim 1, characterized in that, The SRC self-recovery unit includes a first inverter, a second inverter, a third C unit, a fifth transmission gate, a fourth C unit, a sixth transmission gate, and a second C unit; the input terminal of the first inverter is connected to the output terminal of the first transmission gate, and the input terminal of the second inverter is connected to the output terminal of the second transmission gate; the two input terminals of the second C unit are respectively connected to the output terminals of the first transmission gate and the second transmission gate, and the output terminal serves as the output terminal of the SRC self-recovery unit; The two input terminals of the third C unit are respectively connected to the output terminals of the first inverter and the second C unit, and the output terminal is connected to the input terminal of the fifth transmission gate. The output terminal of the fifth transmission gate is connected to the output terminal of the second transmission gate. The two input terminals of the fourth C unit are respectively connected to the output terminals of the second inverter and the second C unit, and the output terminal is connected to the input terminal of the sixth transmission gate. The output terminal of the sixth transmission gate is connected to the output terminal of the first transmission gate.
3. A low-power anti-dual-node flip-flop latch according to claim 2, characterized in that, The PMOS gates of the fifth and sixth transmission gates are connected to the system clock, and the NMOS gates of the fifth and sixth transmission gates are connected to the inverted system clock.
4. A low-power anti-dual-node flip-flop latch according to claim 1, characterized in that, The gates of the PMOS transistors of the first, second, third, and fourth transmission gates are connected to the inverted system clock, and the gates of the NMOS transistors of the first, second, third, and fourth transmission gates are connected to the system clock.
5. A low-power anti-dual-node-flip latch according to any one of claims 1-2, characterized in that, The C unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The gate of the first PMOS transistor is connected to the first input terminal, the source is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor is connected to the second input terminal, and the drain is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the first input terminal, and the source is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the second input terminal, and the source is grounded.
6. A low-power anti-dual-node-flip latch according to claim 1, characterized in that, The clock control C unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gate of the third PMOS transistor is connected to the system clock, its source is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the output of the SRC self-recovery unit, and its drain is connected to the source of the fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the output of the first C unit, and its drain is connected to the drain of the third NMOS transistor and the output of the latch. The gate of the third NMOS transistor is connected to the output of the first C unit, and its source is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the output of the SRC self-recovery unit, and its source is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the inverting system clock, and its source is grounded.