Layout pattern of static random access memory and manufacturing method thereof

Abstract

A layout pattern of a static random access memory includes a first region adjacent to a second region, a first SRAM cell located in the first region, the first region including a first diffusion region, a second SRAM cell located in the second region, the second region including a second diffusion region, a gate structure, and a second SRAM cell located in the second region. The gate structure spans the first diffusion region and forms a first pass gate transistor of the first SRAM cell, the gate structure spans the second diffusion region and forms a second pass gate transistor of the second SRAM cell, and the gate structure extends along a first direction; and the first diffusion region and the second diffusion region which are overlapped with the gate structure are not connected in the first direction.

Description

Technical Field

[0001] This invention relates to a layout pattern for a static random access memory (SRAM), and more particularly to a SRAM layout pattern that reduces leakage current between adjacent regions. Background Technology

[0002] An embedded static random access memory (SRAM) contains logic circuitry and SRAM connected to the logic circuitry. SRAM itself is a type of volatile memory cell, meaning that the stored data is erased when the power supply to the SRAM is lost. SRAM stores data using the conductivity state of transistors within the memory cells. SRAM is designed based on intercoupled transistors, eliminating the need for capacitor discharge and continuous charging to prevent data loss; in other words, it does not require memory updates. This differs from dynamic random access memory (DRAM), which uses capacitors to store data. SRAM offers very fast access speeds and is therefore used in computer systems as cache memory. Summary of the Invention

[0003] The present invention provides a layout pattern for a static random access memory (SRAM), comprising a first region and a second region adjacent to each other, a first SRAM cell located in the first region, the first region including a first diffusion region, a second SRAM cell located in the second region, the second region including a second diffusion region, and a gate structure spanning the first region and the second region. The gate structure spans the first diffusion region and constitutes a first transmission gate transistor of the first SRAM cell, and the gate structure spans the second diffusion region and constitutes a second transmission gate transistor of the second SRAM cell. The gate structure extends along a first direction, and the first diffusion region and the second diffusion region overlapping the gate structure are not connected in the first direction.

[0004] The present invention further provides a method for fabricating a layout pattern of a static random access memory (SRAM), comprising defining a first region and a second region adjacent to each other, forming a first SRAM cell located in the first region, the first region including a first diffusion region, forming a second SRAM cell located in the second region, the second region including a second diffusion region, forming a gate structure spanning the first region and the second region, wherein the gate structure spans the first diffusion region and constitutes a first transmission gate transistor of the first SRAM cell, the gate structure spans the second diffusion region and constitutes a second transmission gate transistor of the second SRAM cell, wherein the gate structure extends along a first direction, and the first diffusion region and the second diffusion region overlapping the gate structure are not connected in the first direction.

[0005] In summary, this invention discloses a layout pattern for 6T-SRAM. When multiple SRAM cells are arranged adjacently, they may share some components, but this may also lead to significant leakage current. The key feature of this invention is that the diffusion regions of the second transmission gate transistors in the first region and the adjacent second region are designed to be separate. However, the gate structures of the second transmission gate transistors in the first region and the adjacent second region are still in contact with each other. When the word line is turned on, although electrons flow into the diffusion region below the gate structure, because the diffusion regions of the two adjacent regions below the gate structure are not connected, leakage current between the two regions can be effectively blocked, thereby improving the quality of the static random access memory. Attached Figure Description

[0006] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed textual descriptions while reading this invention. The specific embodiments described herein, along with the corresponding drawings, are used to explain in detail the specific embodiments of the invention and to elucidate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0007] Figure 1 This is a circuit diagram of a group of six-transistor SRAM (6T-SRAM) memory cells in the static random access memory of the present invention.

[0008] Figure 2 This is a layout diagram of a 6T-SRAM according to an embodiment of the present invention.

[0009] Figures 3 to 4 As an embodiment of the present invention, along Figure 2A cross-sectional view of the second transmission gate transistor PG2 fabricated along the tangent AA' direction.

[0010] Figure 5 The diagram illustrates a layout pattern of a static random access memory (SRAM) according to a second embodiment of the present invention.

[0011] Figure 6 The diagram illustrates a layout pattern of a static random access memory (SRAM) according to a third embodiment of the present invention.

[0012] [Symbol Explanation]

[0013] 10: Six-transistor static random access memory

[0014] 12: Base

[0015] 14: First semiconductor layer

[0016] 16: Insulation layer

[0017] 18: Second semiconductor layer

[0018] 30: Gate dielectric layer

[0019] 32: Gate material layer

[0020] 50: Contact hole etching stop layer

[0021] 52: Interlayer dielectric layer

[0022] 62: High dielectric constant dielectric layer

[0023] 64: Work function metal layer

[0024] 66: Low-resistivity metal layer

[0025] 68: Hard Mask

[0026] 70: Dielectric layer

[0027] 72: Intermetallic dielectric layer

[0028] 74: Metal interconnects

[0029] AA: Active Zone

[0030] BL1: Bitline

[0031] BL2: Bitline

[0032] CT: Contact plug

[0033] CT-B1: Contact plug for connecting bit lines

[0034] CT-B2: Contact plug for connecting bit lines

[0035] D1: Diffusion Region

[0036] D2: Diffusion region

[0037] D3: Diffusion Zone (First Diffusion Zone)

[0038] D4: Diffusion Zone (Second Diffusion Zone)

[0039] Diff: Diffusion region

[0040] G: Gate structure

[0041] G1: Gate structure

[0042] G2: Gate structure

[0043] G3: Gate structure

[0044] G4: Gate structure

[0045] M0: Zeroth metal layer

[0046] N1: Storage node

[0047] N2: Storage node

[0048] N + -Diff: N-type diffusion region

[0049] P0: Extract contact plug

[0050] P1: Extract the contact plug

[0051] P2: Extract the contact plug

[0052] P + -Diff: P-type diffusion region

[0053] PU1: First pull-up transistor

[0054] PU2: Second pull-up transistor

[0055] PD1: First pull-down transistor

[0056] PD2: Second pull-down transistor

[0057] PG1: First transmission gate transistor

[0058] PG2: Second transmission gate transistor

[0059] R: Region

[0060] R1: Region

[0061] R11: Region

[0062] R12: Region

[0063] R13: Region

[0064] R14: Region

[0065] R21: Region

[0066] R22: Region

[0067] R23: Region

[0068] R24: Region

[0069] STI: Shallow Trench Isolation

[0070] STI-1: Shallow Trench Isolation

[0071] STI-2: Shallow Trench Isolation

[0072] Vcc: Voltage source

[0073] Vss: Voltage source

[0074] WL: Wordline Detailed Implementation

[0075] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0076] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0077] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0078] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes something and has an intermediate feature or layer between them, and that “above” or “above” not only means above or above something, but can also include the meaning of having no intermediate feature or layer (i.e., directly on something).

[0079] Furthermore, for ease of description, as illustrated in the figures, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the figures, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0080] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0081] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0082] Please refer to Figure 1 and Figure 2 , Figure 1 This is a circuit diagram of a group of six-transistor SRAM (6T-SRAM) memory cells in the static random access memory of this invention. Figure 2 This is a layout diagram of a 6T-SRAM according to an embodiment of the present invention. Figure 1 and Figure 2 As shown, the static random access memory of the present invention preferably includes at least one set of static random access memory cells, wherein each static random access memory cell includes a six-transistor static random access memory cell (6T-SRAM) 10.

[0083] In this embodiment, each 6T-SRAM memory cell 10 preferably consists of a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1, and a second pass gate transistor PG2 forming a flip-flop. The first pull-up transistor PU1 and the second pull-up transistor PU2, as well as the first pull-down transistor PD1 and the second pull-down transistor PD2, form a latch circuit, allowing data to be latched into storage node N1 or N2. Furthermore, the first pull-up transistor PU1 and the second pull-up transistor PU2 serve as active loads; they can also be replaced by ordinary resistors as pull-up elements, in which case it becomes a four-transistor static random access memory (4T-SRAM). In this embodiment, one source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and one source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0084] Generally, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the 6T-SRAM memory cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors. The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the two ends of the series circuit formed by them are coupled to a voltage source Vcc and a voltage source Vss, respectively. Similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the two ends of the series circuit formed by them are also coupled to a voltage source Vcc and a voltage source Vss, respectively.

[0085] Furthermore, at storage node N1, the gates G of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drains D of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first transmission gate transistor PG1 are electrically connected, respectively. Similarly, at storage node N2, the gates G of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drains D of the second pull-down transistor PD2, the second pull-up transistor PU2, and the second transmission gate transistor PG2 are also electrically connected, respectively. The gates G of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are coupled to the word line WL, respectively, and the sources S of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are coupled to the corresponding bit lines BL1 and BL2, respectively.

[0086] Please refer to the following at the same time: Figures 2 to 4 , Figure 2 The diagram illustrates a layout of a static random access memory (SRAM) cell according to a first embodiment of the present invention. Figures 3 to 4 As an embodiment of the present invention, along Figure 2 A cross-sectional view of the second transmission gate transistor PG2 is shown along the tangent AA' direction. It is worth noting that... Figure 2 The region R shown contains the smallest unit of a static random access memory (SRAM), while Figure 3 and Figure 4 A cross-sectional view of the second transmission gate transistor PG2 in the SRAM cell is shown below, and the method for fabricating the second transmission gate transistor PG2 will be explained in the following paragraphs. It will be understood that, in addition to the second transmission gate transistor PG2, the transistors in the SRAM cells described in the following embodiments can also be fabricated using methods similar to... Figure 3 and Figure 4 The same method is used to form it, so this instruction manual will not elaborate further.

[0087] like Figure 2 and Figure 3 As shown, a substrate 12 made of semiconductor material is first provided, such as a silicon-on-insulator (SOI) substrate 12, which mainly includes a first semiconductor layer 14, an insulating layer 16 disposed on the first semiconductor layer 14, and a second semiconductor layer 18 disposed on the insulating layer 16. In this embodiment, the first semiconductor layer 14 and the second semiconductor layer 18 may contain the same or different materials and may be selected from the group consisting of silicon, germanium, and silicon germanide, respectively. The insulating layer 16 disposed between the first semiconductor layer 14 and the second semiconductor layer 18 preferably contains silicon dioxide (SiO2), but is not limited thereto.

[0088] It should be noted that although a silicon-coated insulating substrate is preferably used as the substrate for the semiconductor device in this embodiment, according to other embodiments of the present invention, the substrate 12 can also be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, or a silicon carbide substrate. These material choices are also within the scope of the present invention. Then, multiple active regions AA can be defined on the substrate 12, such as... Figure 2 As shown, a portion of the second semiconductor layer 18 outside the active region AA is removed to form a shallow trench isolation (STI) surrounding the active region AA or the second semiconductor layer 18. The second semiconductor layer 18 surrounded by the shallow trench isolation (STI) is preferably used to house an active element or a wireless radio frequency element.

[0089] Next, multiple gate structures G are formed on the substrate 12. Viewed from the top angle of the first transmission gate transistor PG1, the gate structures G preferably extend along a first direction (e.g., the X direction) on the substrate 12, and each gate structure is generally elongated. It should be noted that although the gate structure G in this embodiment is elongated, it is not limited to this. According to other embodiments of the present invention, the gate structure G may also exhibit other shapes, such as L-shape, from the top angle, and such variations are also within the scope of the present invention.

[0090] The gate structure G can be fabricated in various ways depending on the manufacturing process requirements, such as a gate-first fabrication process, a gate-last fabrication process (high-k first), or a gate-last fabrication process followed by a high-k last fabrication process. Taking the high-k last fabrication process in this embodiment as an example, a gate dielectric layer 30 or dielectric layer made of silicon oxide, a gate material layer 32 made of polysilicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A patterned photoresist (not shown) is then used as a mask to perform a pattern transfer fabrication process. In a single etching or sequential etching step, part of the gate material layer 32 and part of the gate dielectric layer 30 are removed. Then, the patterned photoresist is stripped to form the gate structure G on the substrate 12, which consists of the patterned gate dielectric layer 30 and the patterned gate material layer 32.

[0091] At least one sidewall (not shown) can then be formed on the sidewall of the gate structure G. In this embodiment, the sidewall can be a single sidewall or a composite sidewall, for example, it can specifically include an off-center sidewall (not shown) and a main sidewall (not shown). The off-center sidewall and the main sidewall preferably contain different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide, but are not limited thereto.

[0092] Next, an ion implantation process can be performed to dope different types of ions in different parts of region R, thereby forming a diffusion region Diff in a portion of the active region AA within region R. This diffusion region Diff serves as the source / drain of each transistor. Specifically, a doping step is performed to form a doped region as the source / drain region on the substrate 12 on both sides of the gate structure G within region R or within the active region AA. Since the first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors, the diffusion region Diff is doped with P-type ions, such as boron (B) ions. Furthermore, since the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 are NMOS transistors, the diffusion region Diff is doped with N-type ions, such as phosphorus (P) ions and arsenic (As) ions. Figure 2 In the middle, with N + -Diff indicates that it is doped with N-type or N-type. + The diffusion region of the dopant, with P + -Diff indicates that it is doped with P-type or P-type. + The diffusion region of the dopant. It is worth noting that after the doping step is completed, from the top view, part of the active region AA overlaps with the diffusion region Diff (the active regions AA not covered by the gate structure G are all doped and become the diffusion region Diff), so they are represented by the same background.

[0093] Then, a selective metallization manufacturing process can be performed to form a metallization layer on the surface of the diffusion region Diff, forming a contact etch stop layer (CESL) 50 made of silicon nitride on the substrate 12 and covering the gate structure G and the surface of the substrate 12, and then forming an inter-dielectric layer 52 on the contact etch stop layer 50.

[0094] Then as Figure 4 As shown, a planarization manufacturing process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 52 and part of the contact hole etch stop layer 50 to make the upper surface of the gate structure G, the upper surface of the contact hole etch stop layer 50 and the upper surface of the interlayer dielectric layer 52 flush.

[0095] Subsequently, a metal gate replacement (RMG) manufacturing process is performed to convert the gate structure G into a metal gate. For example, a selective dry or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 32 in the gate structure G to form a groove (not shown) in the interlayer dielectric layer 52. Then, a high dielectric constant dielectric layer 62 and a conductive layer including at least a work function metal layer 64 and a low impedance metal layer 66 are sequentially formed in the groove. A planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 62, the U-shaped work function metal layer 64, and the low impedance metal layer 66 flush with the surface of the interlayer dielectric layer 52. Preferably, the high dielectric constant dielectric layer 62, the work function metal layer 64, and the low impedance metal layer 66 are the gate electrodes of each transistor or device.

[0096] In this embodiment, the high dielectric constant dielectric layer 62 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide (SrTiO3). SrBi₂Ta₂O₉, SBT, lead zirconate titanate, PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1-x Groups consisting of TiO3, BST, or combinations thereof.

[0097] The work function metal layer 64 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 64 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 64 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 64 and the low impedance metal layer 66. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 66 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since converting a dummy gate into a metal gate according to the metal gate replacement manufacturing process is common knowledge in this field, it will not be elaborated here. Next, a portion of the high dielectric constant dielectric layer 62, a portion of the work function metal layer 64, and a portion of the low impedance metal layer 66 may be removed to form a groove (not shown). Then, a hard mask 68 is filled into the groove and made flush with the surface of the interlayer dielectric layer 52. The hard mask 68 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0098] A contact plug manufacturing process can then be performed. For example, another dielectric layer 70 can be selectively formed on the interlayer dielectric layer 52, followed by a pattern transfer manufacturing process. For example, a patterned mask can be used to remove part of the dielectric layer 70 and part of the hard mask 68 directly above the gate structure G, as well as part of the interlayer dielectric layer 52 and part of the contact hole etching stop layer 50 next to the gate structure G to form multiple contact holes (not shown) and expose the top surface of the gate structure G and the diffusion region Diff surface. Then, the required metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization manufacturing process is then performed, such as chemical mechanical polishing to remove some metal material to form contact plugs (CTs) within each contact hole, electrically connecting the diffusion region Diff (i.e., the source / drain region) and the gate structure G. It is worth noting that the aforementioned contact plugs (CTs) are primarily used to connect components of different layers. However, in some embodiments, the formed contact holes, after being filled with metal material, can also be used to connect components of the same layer. For example, connecting the gate of the second pull-up transistor PU2 to the drain of the first pull-up transistor PU1. In this case, the metal material layer can be defined as the zeroth metal layer (M0). Both the zeroth metal layer M0 and the contact plugs (CTs) have the function of connecting different components, and preferably both contain the same material, but are not limited to this. Furthermore, from... Figure 4 The cross-sectional view does not show the contact hole located on the top surface of the gate structure G, but it is understood that the gate structure G may contain contact holes in other places to facilitate the subsequent formation of contact plugs to electrically connect the gate structure G.

[0099] Following this, a downstream metal interconnect fabrication process can be performed. For example, an intermetallic dielectric layer 72 can be formed on the dielectric layer 70, and one or more photolithography and etching processes can be performed to remove part of the intermetallic dielectric layer 72 to form contact holes (not shown). Then, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 74 connecting to the underlying contact plugs CT. As with the contact plugs CT formed as described above, each metal interconnect 74 can be embedded within the intermetallic dielectric layer 72 using a single-damascene or double-damascene fabrication process. For example, each metal interconnect 74 can more specifically include a barrier layer and a metal layer. The barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited to these. Since single-damascene or dual-damascene manufacturing processes are common knowledge in the field, they will not be described in detail here. This completes the fabrication of the semiconductor element according to the first embodiment of the present invention.

[0100] The above Figure 2 The layout pattern shown is that of a single smallest SRAM cell. In actual manufactured electronic products, the layout pattern typically includes an array of many SRAM cells. When multiple SRAM cell patterns are arranged in an array, adjacent SRAM cells may share some components. For example, Figure 5 The diagram illustrates a layout pattern of a static random access memory (SRAM) according to a second embodiment of the present invention. Figure 5 As shown, it comprises four adjacent regions R11, R12, R13, and R14, which are joined together. Each of regions R11-R14 contains one SRAM cell. To more clearly illustrate the features of this embodiment, only a portion of the SRAM cell patterns in each region R11-R14 are shown, such as the second pull-down transistor PD2 and the second transmission gate transistor PG2. The patterns in regions R11 and R12 are mirrored vertically, the patterns in regions R11 and R13 are mirrored horizontally, and the patterns in regions R13 and R14 are mirrored vertically. Additionally, see also [reference needed]. Figure 2 The region R1 shown is where Figure 5 The second pull-down transistor PD2 and the second transmission gate transistor PG2 in region R11 are arranged in a similar direction. Figure 2 The arrangement direction of the second pull-down transistor PD2 and the second transmission gate transistor PG2 in region R1 shown, therefore... Figure 5 The transistors not shown can also be obtained from the reference. Figure 2 Its location was known. It is worth noting that, in Figure 5 In the diagram, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the first transmission gate transistor PG1 are located outside the shown area and are therefore not drawn. However, it is understood that these components should exist in the SRAM pattern, and their layout and position can be referenced. Figure 2 As shown, I will not elaborate further in this paragraph.

[0101] It is worth noting that when multiple SRAM cells are interconnected, a portion of the components can be shared to reduce the overall area of ​​the semiconductor structure, for example... Figure 5 In the SRAM cells in regions R11-R14, the diffusion region Diff and the gate structure G can span different regions, and a portion of the contact plug CT can be located between multiple regions, so that the SRAM cells in these multiple adjacent regions are connected to a contact plug CT and connected to the same signal source.

[0102] For example, Figure 5 The gate structure G, which forms the second transmission gate transistor PG2 within region R11, is defined as gate structure G1, and the diffusion region Diff spanned by gate structure G1 is defined as diffusion region D1. Furthermore, Figure 5 The gate structure G, which forms the second transmission gate transistor PG2 within region R12, is defined as gate structure G2, and the diffusion region Diff, which is spanned by gate structure G2, is defined as diffusion region D2. For example... Figure 5 As shown, gate structures G1 and G2 are interconnected and in contact with each other, and diffusion regions D1 and D2 are also interconnected and in direct contact with each other. In this way, SRAM cells in regions R11 and R12 can share some components, such as contact plugs for connecting word lines WL. Figure 5 The winning bid is for the contact plug CT next to WL, or a contact plug used to release excess accumulated charge. Figure 5 (The extraction contact plug is labeled P0). In addition, in order to clearly describe the connection relationship between the components, some components such as word lines WL, voltage sources Vss, bit lines BL2, etc. are directly labeled next to the contact structure CT of the layout pattern in the figures of this invention.

[0103] In this embodiment, to clearly describe the shapes of diffusion regions D1 and D2, enlarged patterns of diffusion regions D1 and D2 are drawn next to the layout pattern. From the top view, diffusion regions D1 and D2 are, for example, a square shape composed of four long strip patterns. Diffusion regions D1 and D2 are connected to each other and share a long strip pattern. For example, the long strip pattern on the right side of diffusion region D1 is shared with the long strip pattern on the left side of diffusion region D2, and the extraction contact plug P0 is located on this shared long strip pattern.

[0104] like Figure 5 As shown, taking regions R11 and R12 as examples, although regions R11 and R12 share some components, allowing for a reduction in the overall semiconductor structure area, this also causes some problems. Specifically, the applicant has found that leakage current is more likely to occur between adjacent regions. More specifically, the applicant has found that the leakage current is caused by… Figure 5 In the design, gate structures G1 and G2 are interconnected, spanning regions R11 and R12. Similarly, diffusion regions D1 and D2 are also interconnected, spanning regions R11 and R12. Therefore, when a voltage is applied to the word line WL (when the word line WL is turned on), the channels below gate structures G1 and G2 are opened, allowing electrons to flow into diffusion regions D1 and D2 below them. Since diffusion regions D1 and D2 are interconnected and span different regions, the electrons flowing into D1 and D2 can easily generate leakage current and affect adjacent SRAM cells, especially when the word line WL is turned on, the intensity of the leakage current may significantly affect the operation of the SRAM cells. Taking the applicant's experimental results as an example, regarding... Figure 5 The structure shown was measured, and with the word line WL disabled, the measured leakage current intensity was approximately 10. -14 Around A, however, after turning on the word line WL, the measured leakage current intensity increased significantly to approximately 10. -7 Around A, this leakage current intensity is sufficient to affect the operation of SRAM cells and further impact the overall quality of semiconductor devices.

[0105] In order to reduce Figure 5 To address the leakage current problem in static random access memory (SRAM), this invention provides another embodiment. Please refer to... Figure 6 , Figure 6 The diagram illustrates a layout pattern of a static random access memory (SRAM) according to a third embodiment of the present invention. Figure 6As shown, the static random access memory (SRAM) layout pattern provided in this embodiment also includes four adjacent regions R21, R22, R23, and R24, which are joined together. Each of regions R21-R24 contains one SRAM cell. To more clearly illustrate the features of this embodiment, only a portion of the SRAM cell pattern in each region R21-R24 is shown, such as the second pull-up transistor PU2, the second pull-down transistor PD2, and the second transmission gate transistor PG2. The patterns in regions R21 and R22 are mirrored vertically, the patterns in regions R21 and R23 are mirrored horizontally, and the patterns in regions R23 and R24 are mirrored vertically. Additionally, refer to... Figure 2 The layout pattern shown, in which Figure 6 The arrangement of the second pull-up transistor PU2, the second pull-down transistor PD2, and the second transmission gate transistor PG2 in region R21 is similar to that in other regions. Figure 2 The arrangement direction of the second pull-up transistor PU2, the second pull-down transistor PD2, and the second transmission gate transistor PG2 in region R shown is therefore... Figure 5 The transistors not shown can also be obtained from the reference. Figure 2 Its location was known. It is worth noting that, in Figure 5 In the diagram, the first pull-up transistor PU1, the first pull-down transistor PD1, and the first transmission gate transistor PG1 are located outside the shown area and are therefore not drawn. However, it is understood that these components should exist in the SRAM pattern, and their layout and position can be referenced. Figure 2 As shown, I will not elaborate further in this paragraph.

[0106] In this embodiment, Figure 6 The gate structure G, which forms the second transmission gate transistor PG2 within region R21, is defined as gate structure G3. The diffusion region Diff, spanned by gate structure G3, is defined as diffusion region D3. Furthermore... Figure 6 The gate structure G, which forms the second transmission gate transistor PG2 within region R22, is defined as gate structure G4, and the diffusion region Diff, which is spanned by gate structure G4, is defined as diffusion region D4. For example... Figure 6 As shown, gate structure G3 and gate structure G4 are interconnected and in contact with each other, but with Figure 5 The difference is that in this embodiment, diffusion regions D3 and D4 do not contact each other. As a result, the SRAM cells in regions R21 and R22 share gate structures G3 and G4, as well as the contact plugs that share the word line WL. Figure 6The winning designation is the contact plug CT next to WL. However, they do not share the diffusion region; instead, the diffusion regions D3 and D4 within region R21 and region R22 are separated, thus forming two contact plugs for releasing excess accumulated charge. Figure 6 The extraction contact plugs labeled P1 and P2 are placed on the diffusion areas D3 and D4. In addition, in order to clearly describe the connection relationship between the components, some components such as word lines WL, voltage sources Vss, bit lines BL2, etc. are directly labeled next to the contact structure CT of the layout pattern in the figure of this invention.

[0107] In this embodiment, to clearly describe the shapes of diffusion regions D3 and D4, enlarged patterns of diffusion regions D3 and D4 are drawn next to the layout pattern. From the top view, diffusion regions D3 and D4 are, for example, a square shape composed of four long strip patterns. Diffusion regions D3 and D4 do not contact each other. The extraction contact plug P1 is located on the long strip pattern to the right of diffusion region D3, while the extraction contact plug P2 is located on the long strip pattern to the left of diffusion region D4.

[0108] In this embodiment, gate structures G3 and G4 are interconnected, spanning regions R21 and R22. However, diffusion regions D3 and D4 are separate and not connected. Therefore, when a voltage is applied to the word line WL (word line WL is turned on), the channels below gate structures G3 and G4 are opened, and electrons flow into diffusion regions D3 and D4 below gate structures G3 and G4. However, since diffusion regions D3 and D4 are not connected, the electrons flowing into diffusion regions D3 and D4 are less likely to generate leakage current and affect adjacent SRAM cells. Furthermore, to release the charge accumulated in the substrate in their respective regions, this embodiment forms two pull-out contact plugs P1 and P2, respectively connecting diffusion regions D3 and D4. Compared to the above embodiment, this embodiment significantly reduces leakage current and improves the quality of the static random access memory.

[0109] Based on the above description and drawings, this invention provides a layout pattern for a static random access memory (Please refer to...). Figure 6The system comprises a first region R21 and a second region R22 adjacent to each other. A first SRAM (Static Random Access Memory) cell is located in the first region R21, which contains a first diffusion region D3. A second SRAM cell is located in the second region R22, which contains a second diffusion region D4. A gate structure (i.e., connected gate structures G3 and G4, hereinafter defined as gate structure G) spans the first region R21 and the second region R22. The gate structure G spans the first diffusion region D3 and constitutes a first transmission gate transistor PG2 of the first SRAM cell. The gate structure G spans the second diffusion region D4 and constitutes a second transmission gate transistor PG2 of the second SRAM cell. The gate structure G extends along a first direction (X direction), and the first diffusion region D3 and the second diffusion region D4 that overlap with the gate structure G are not connected in the first direction (e.g., ...). Figure 6 As shown, the first diffusion region D3 and the second diffusion region D4 are separated from each other in the X direction.

[0110] In some embodiments of the present invention, the first diffusion region D3 and the second diffusion region D4, viewed from a top view, present a rectangular shape (e.g., ...). Figure 6 ).

[0111] In some embodiments of the present invention, wherein, viewed from the top view, the first diffusion region D3 and the second diffusion region D4 are arranged along a first direction (X direction), and further include a first shallow trench isolation STI-1 located between the first diffusion region D3 and the second diffusion region D4 (e.g., Figure 6 As shown, this is the shallow trench isolation STI located between the first diffusion region D3 and the second diffusion region D4, which is defined here as shallow trench isolation STI-1).

[0112] In some embodiments of the present invention, the gate structure G overlaps with the first diffusion region D3, the second diffusion region D4, and the first shallow trench isolation STI-1, as viewed from the top view.

[0113] In some embodiments of the present invention, it further includes a first bit line contact structure CT-B1 located on the first diffusion region D3 and electrically connected to a bit line (bit line BL2 located in region R21), and a second bit line contact structure CT-B2 located on the second diffusion region D4 and electrically connected to another bit line (bit line BL2 located in region R22).

[0114] In some embodiments of the present invention, it further includes a first extraction contact plug P1 located on a first diffusion region D3, and a second extraction contact plug P2 located on a second diffusion region D4.

[0115] In some embodiments of the present invention, the first diffusion region D3 is rectangular and includes four sides, wherein the first line contact CT-B1 is located on one side of the first diffusion region D3, and the first extraction contact plug P1 is located on the other side of the first diffusion region D3.

[0116] In some embodiments of the present invention, the first line contact structure CT-B1 and the second line contact structure CT-B2 are arranged symmetrically to each other, and the first extraction contact plug P1 and the second extraction contact plug P2 are arranged symmetrically to each other.

[0117] In some embodiments of the present invention, the first diffusion region D3 is rectangular and further includes a second shallow trench isolation STI-2 located within and surrounded by the rectangular first diffusion region D3.

[0118] In some embodiments of the present invention, a line contact is also included ( Figure 6 The contact plug CT of the word line WL is electrically connected to the gate structure G, wherein the word line contact is electrically connected to the word line WL.

[0119] The present invention further provides a method for fabricating a layout pattern of a static random access memory (SRAM), comprising defining a first region R21 and a second region R22 adjacent to each other, forming a first SRAM cell located in the first region R21, the first region R21 containing a first diffusion region D3, forming a second SRAM cell located in the second region R22, the second region R22 containing a second diffusion region D4, forming a gate structure (i.e., connected gate structures G3 and G4, hereinafter defined as gate structure G) spanning the first region R21 and the second region R22, wherein the gate structure G spans the first diffusion region D3 and constitutes a first transmission gate transistor PG2 of the first SRAM cell, the gate structure G spans the second diffusion region D4 and constitutes a second transmission gate transistor PG2 of the second SRAM cell, wherein the gate structure G extends along a first direction (X direction), and the first diffusion region D3 and the second diffusion region D4 overlapping with the gate structure G are not connected in the first direction (e.g., ...). Figure 6 As shown, the first diffusion region D3 and the second diffusion region D4 are separated from each other in the X direction.

[0120] In some embodiments of the present invention, the first diffusion region D3 and the second diffusion region D4, viewed from a top view, present a rectangular shape (e.g., ...). Figure 6 ).

[0121] In some embodiments of the present invention, wherein, viewed from the top view, the first diffusion region D3 and the second diffusion region D4 are arranged along a first direction (X direction), and further comprising forming a first shallow trench isolation STI-1 located between the first diffusion region D3 and the second diffusion region D4 (e.g. Figure 6 As shown, this is the shallow trench isolation STI located between the first diffusion region D3 and the second diffusion region D4, which is defined here as shallow trench isolation STI-1).

[0122] In some embodiments of the present invention, the gate structure G overlaps with the first diffusion region D3, the second diffusion region D4, and the first shallow trench isolation STI-1, as viewed from the top view.

[0123] In some embodiments of the present invention, it further includes forming a first bit line contact structure CT-B1 located on a first diffusion region D3 and electrically connected to a bit line (bit line BL2 located in region R21), and forming a second bit line contact structure CT-B2 located on a second diffusion region D4 and electrically connected to another bit line (bit line BL2 located in region R22).

[0124] In some embodiments of the present invention, it further includes forming a first extraction contact plug P1 located on a first diffusion region D3, and forming a second extraction contact plug P2 located on a second diffusion region D4.

[0125] In some embodiments of the present invention, the first diffusion region D3 is rectangular and includes four sides, wherein the first line contact CT-B1 is located on one side of the first diffusion region D3, and the first extraction contact plug P1 is located on the other side of the first diffusion region D3.

[0126] In some embodiments of the present invention, the first line contact structure CT-B1 and the second line contact structure CT-B2 are arranged symmetrically to each other, and the first extraction contact plug P1 and the second extraction contact plug P2 are arranged symmetrically to each other.

[0127] In some embodiments of the invention, the first diffusion region D3 is rectangular and further includes a second shallow trench isolation STI-2 located within and surrounded by the rectangular first diffusion region D3.

[0128] In some embodiments of the invention, a line contact is further included. Figure 6 The contact plug CT of the word line WL is electrically connected to the gate structure G, wherein the word line contact is electrically connected to the word line WL.

[0129] In summary, this invention discloses a layout pattern for 6T-SRAM. When multiple SRAM cells are arranged adjacently, they may share some components, but this may also lead to significant leakage current. The key feature of this invention is that the diffusion regions of the second transmission gate transistors in the first region and the adjacent second region are designed to be separate. However, the gate structures of the second transmission gate transistors in the first region and the adjacent second region are still in contact with each other. When the word line is turned on, although electrons flow into the diffusion region below the gate structure, because the diffusion regions of the two adjacent regions below the gate structure are not connected, leakage current between the two regions can be effectively blocked, thereby improving the quality of the static random access memory.

[0130] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims should be within the scope of the present invention.

Claims

1. A layout pattern for a static random access memory, comprising: A first region is adjacent to a second region; A first SRAM (Static Random Access Memory) cell is located in the first region, and the first region contains a first diffusion region; A second SRAM (Static Random Access Memory) cell is located in the second region, and the second region contains a second diffusion region; A gate structure spans the first region and the second region, wherein the gate structure spans the first diffusion region and constitutes a first transmission gate transistor of the first SRAM cell, and the gate structure spans the second diffusion region and constitutes a second transmission gate transistor of the second SRAM cell, wherein the gate structure extends along a first direction, and the first diffusion region and the second diffusion region overlapping the gate structure are not connected in the first direction.

2. The layout pattern of the static random access memory as claimed in claim 1, wherein, viewed from a top view, the first diffusion region and the second diffusion region present a square shape.

3. The layout pattern of the static random access memory as claimed in claim 2, wherein, viewed from the top view, the first diffusion region and the second diffusion region are arranged along the first direction, and further includes a first shallow trench isolation located between the first diffusion region and the second diffusion region.

4. The layout pattern of the static random access memory as claimed in claim 3, wherein, viewed from the top view, the gate structure overlaps with the first diffusion region, the second diffusion region, and the first shallow trench isolation.

5. The layout pattern of the static random access memory as claimed in claim 2, further comprising a first bit line contact structure located on the first diffusion region and electrically connected to a bit line, and a second bit line contact structure located on the second diffusion region and electrically connected to another bit line.

6. The layout pattern of the static random access memory as claimed in claim 5, further comprising a first fetch contact plug located on the first diffusion region, and a second fetch contact plug located on the second diffusion region.

7. The layout pattern of the static random access memory as claimed in claim 6, wherein the first diffusion region is square and includes four sides, wherein the first bit line contact is located on one side of the first diffusion region, and the first extraction contact plug is located on the other side of the first diffusion region.

8. The layout pattern of the static random access memory as claimed in claim 6, wherein the first bit line contact structure and the second bit line contact structure are arranged symmetrically to each other, and the first retrieval contact plug and the second retrieval contact plug are arranged symmetrically to each other.

9. The layout pattern of the static random access memory as claimed in claim 2, wherein the first diffusion region is square-shaped and further includes a second shallow trench that isolates the square-shaped first diffusion region and is surrounded by the first diffusion region.

10. The layout pattern of the static random access memory as claimed in claim 1, further comprising a word line contact electrically connected to the gate structure, wherein the word line contact is electrically connected to a word line.

11. A method for fabricating a layout pattern for a static random access memory, comprising: Define a first region and a second region as adjacent; A first SRAM (Static Random Access Memory) cell is formed within the first region, and the first region includes a first diffusion region; A second SRAM (Static Random Access Memory) cell is formed within the second region, and the second region contains a second diffusion region; A gate structure is formed, spanning the first region and the second region, wherein the gate structure spans the first diffusion region and constitutes a first transmission gate transistor of the first SRAM cell, and the gate structure spans the second diffusion region and constitutes a second transmission gate transistor of the second SRAM cell, wherein the gate structure extends along a first direction, and the first diffusion region and the second diffusion region overlapping the gate structure are not connected in the first direction.

12. The method for fabricating the layout pattern of a static random access memory as described in claim 11, wherein, viewed from a top view, the first diffusion region and the second diffusion region present a square shape.

13. The method for fabricating the layout pattern of a static random access memory as described in claim 12, wherein, viewed from the top view, the first diffusion region and the second diffusion region are arranged along the first direction, and further includes a first shallow trench separating the first diffusion region and the second diffusion region.

14. The method for fabricating the layout pattern of a static random access memory as described in claim 13, wherein, viewed from the top view, the gate structure overlaps with the first diffusion region, the second diffusion region, and the first shallow trench isolation.

15. The method for fabricating the layout pattern of a static random access memory as claimed in claim 12, further comprising forming a first bit line contact structure located on the first diffusion region and electrically connected to a bit line, and forming a second bit line contact structure located on the second diffusion region and electrically connected to another bit line.

16. The method for fabricating the layout pattern of a static random access memory as described in claim 15, further comprising forming a first retrieval contact plug located on the first diffusion region, and forming a second retrieval contact plug located on the second diffusion region.

17. The method for fabricating the layout pattern of a static random access memory as described in claim 16, wherein the first diffusion region is square and includes four sides, wherein the first line contact is located on one side of the first diffusion region, and the first extraction contact plug is located on the other side of the first diffusion region.

18. The method for fabricating the layout pattern of a static random access memory as described in claim 16, wherein the first bit line contact structure and the second bit line contact structure are arranged symmetrically to each other, and the first extraction contact plug and the second extraction contact plug are arranged symmetrically to each other.

19. The method for fabricating the layout pattern of a static random access memory as claimed in claim 12, wherein the first diffusion region is square-shaped and further includes a second shallow trench that isolates the square-shaped first diffusion region and is surrounded by the first diffusion region.

20. The method for fabricating the layout pattern of a static random access memory as described in claim 11, further comprising forming a word line contact electrically connected to the gate structure, wherein the word line contact is electrically connected to the word line.

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