Test circuit of intelligent power module

Abstract

The utility model provides a test circuit for an intelligent power module, which comprises a main loop, an upper bridge integrated circuit, a lower bridge integrated circuit, a bootstrap circuit and a first insulated gate bipolar transistor, and is characterized in that the main loop comprises a first capacitor, a load inductor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor; the lower bridge integrated circuit is used for controlling the working state of the third insulated gate bipolar transistor, the upper bridge integrated circuit is used for controlling the working state of the second insulated gate bipolar transistor, and the first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the third insulated gate bipolar transistor are sequentially connected and disconnected by controlling a time sequence. According to the invention, sudden short circuit or surge current and other emergencies in the application process of the intelligent power module can be simulated, and the capability of testing the surge current of the insulated gate bipolar transistor in the intelligent power module in the working process and turning off the insulated gate bipolar transistor in the surge current bearing process is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of intelligent power modules, in particular to a test circuit of an intelligent power module. Background Art

[0002] In practical applications, intelligent power modules (IPMs) may be susceptible to inrush current. At the moment of startup, a significant current peak may occur due to load characteristics or circuit design, resulting in an extremely high current rate of change (di / dt). This rapid current change can generate electromagnetic interference (EMI) through the parasitic inductance and capacitance of the IGBT (Insulated Gate Bipolar Transistor) within the IPM. This can then couple to the high-side output (HO) of the driver integrated circuit (IC) and the gate connection point of the internal IGBT. This coupling effect can cause the gate voltage to rise abnormally. Once it exceeds the threshold voltage of the internal IGBT, it can cause the IGBT to turn on incorrectly. This incorrect turn-on not only disrupts normal circuit operation but can also cause performance degradation or even failure of the IGBT due to overcurrent, overheating, and other factors. It also poses a risk of damage to the driver IC.

[0003] To ensure that intelligent power modules can withstand surge currents and shut down safely within a short period of time in applications, their ability to withstand and shut down large surge currents must be verified during the development process. Existing techniques for testing intelligent power modules' surge current tolerance and shutdown capabilities typically involve a short circuit, allowing the current to rise slowly. This is inconsistent with actual application conditions and poses a harsh test environment, leading to inaccurate test results. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a test circuit for an intelligent power module that overcomes the above problems or at least partially solves the above problems.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a test circuit for an intelligent power module, wherein the circuit includes a main loop, an upper bridge integrated circuit, a lower bridge integrated circuit, a bootstrap circuit, and a first insulated gate bipolar transistor;

[0006] The main circuit includes a first capacitor, a load inductor, a second insulated gate bipolar transistor, and a third insulated gate bipolar transistor; the load inductor is located between the emitter of the second insulated gate bipolar transistor and the collector of the third insulated gate bipolar transistor; one end of the first capacitor is connected to the collector of the second insulated gate bipolar transistor and to the DC voltage input terminal, and the other end is connected to the emitter of the third insulated gate bipolar transistor; the emitter of the third insulated gate bipolar transistor is grounded;

[0007] The first output terminal of the lower bridge integrated circuit is connected to the gate of the third insulated gate bipolar transistor, and is used to receive a first pulse width modulated square wave to control the working state of the third insulated gate bipolar transistor;

[0008] The first output terminal of the upper bridge integrated circuit is connected to the gate of the second insulated gate bipolar transistor, and is used to receive a second pulse width modulated square wave to control the working state of the second insulated gate bipolar transistor;

[0009] The bootstrap circuit is connected to the upper bridge integrated circuit and the emitter of the second insulated gate bipolar transistor, and is configured to generate a voltage difference between the gate and the emitter of the second insulated gate bipolar transistor to turn on the second insulated gate bipolar transistor when the third insulated gate bipolar transistor is turned on and the upper bridge integrated circuit receives a high level;

[0010] The collector of the first insulated gate bipolar transistor is arranged between the emitter of the second insulated gate bipolar transistor and the load inductor, and the emitter is arranged between the collector of the third insulated gate bipolar transistor and the load inductor, and is used to receive a third pulse width modulated square wave. When the received third pulse width modulated square wave is at a high level, the first insulated gate bipolar transistor is turned on to short-circuit the second insulated gate bipolar transistor and the third insulated gate bipolar transistor in the on state, so as to test the short-circuit withstand time, short-circuit current and short-circuit shutdown instantaneous peak voltage of the second insulated gate bipolar transistor and the third insulated gate bipolar transistor.

[0011] Optionally, the bootstrap circuit includes a resistor, a diode and a second capacitor connected in sequence; one end of the second capacitor is arranged between the emitter of the second insulated gate bipolar transistor and the load inductor; one end of the resistor is connected to the power input terminal of the upper bridge integrated circuit; the bootstrap circuit is used to charge the second capacitor when the third insulated gate bipolar transistor is turned on.

[0012] Optionally, the second output terminal of the upper bridge integrated circuit is arranged between the diode and the second capacitor, and the third output terminal is arranged between the second capacitor and the emitter of the second insulated gate bipolar transistor; the upper bridge integrated circuit is used to generate a voltage difference between the first output terminal and the third output terminal of the upper bridge integrated circuit when the received second pulse width modulated square wave is at a high level and the second capacitor is charged to a preset value, so as to control the second insulated gate bipolar transistor to be turned on.

[0013] Optionally, the upper bridge integrated circuit is used to control the second insulated gate bipolar transistor to be disconnected when the second insulated gate bipolar transistor and the third insulated gate bipolar transistor are short-circuited and the received second pulse width modulation square wave is at a low level.

[0014] Optionally, the first input terminal of the lower bridge integrated circuit is used to receive a power supply voltage; the second input terminal is used to receive a first pulse width modulated square wave; and the lower bridge integrated circuit is used to control the third insulated gate bipolar transistor to turn on when the first pulse width modulated square wave received at the second input terminal is at a high level.

[0015] Optionally, the lower bridge integrated circuit is configured to receive a first pulse width modulation square wave of a low level and control the third insulated gate bipolar transistor to be disconnected when the second insulated gate bipolar transistor and the third insulated gate bipolar transistor are short-circuited.

[0016] Optionally, the second output terminal of the lower bridge integrated circuit is used to indicate a detected fault state.

[0017] Optionally, the third output terminal of the lower bridge integrated circuit is used to detect voltage.

[0018] The utility model has the following advantages:

[0019] The utility model provides a test circuit main loop of an intelligent power module, an upper bridge integrated circuit, a lower bridge integrated circuit, a bootstrap circuit and a first insulated gate bipolar transistor. The main loop includes a first capacitor, a load inductor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor. The load inductor is located between the emitter of the second insulated gate bipolar transistor and the collector of the third insulated gate bipolar transistor. One end of the first capacitor is connected to the collector of the second insulated gate bipolar transistor and to a DC voltage input end, and the other end is connected to the emitter of the third insulated gate bipolar transistor. The emitter of the third insulated gate bipolar transistor is grounded. The first output end of the lower bridge integrated circuit is connected to the gate of the third insulated gate bipolar transistor for receiving a first pulse width modulated square wave and controlling the working state of the third insulated gate bipolar transistor. The first output end of the upper bridge integrated circuit is connected to the gate of the second insulated gate bipolar transistor for receiving a second pulse width modulated square wave. Controlling the working state of the second insulated gate bipolar transistor; the bootstrap circuit is connected to the upper bridge integrated circuit and the emitter of the second insulated gate bipolar transistor, and is used to generate a voltage difference between the gate and the emitter of the second insulated gate bipolar transistor to turn on the second insulated gate bipolar transistor when the third insulated gate bipolar transistor is turned on and the upper bridge integrated circuit receives a high level; the collector of the first insulated gate bipolar transistor is arranged between the emitter of the second insulated gate bipolar transistor and the load inductor, and the emitter is arranged between the collector of the third insulated gate bipolar transistor and the load inductor, and is used to receive a third pulse width modulated square wave, and is turned on when the received third pulse width modulated square wave is a high level, so as to short-circuit the second insulated gate bipolar transistor and the third insulated gate bipolar transistor in the turned-on state, so as to test the short-circuit withstand time, short-circuit current and short-circuit turn-off instantaneous peak voltage of the second insulated gate bipolar transistor and the third insulated gate bipolar transistor.

[0020] The utility model can simulate the intelligent power module suddenly encountering emergencies such as short circuit or surge current during application, and realizes the ability of testing the insulated gate bipolar transistor in the intelligent power module encountering surge current during operation and shutting down in the process of bearing the surge current. Before the intelligent power module is packaged, it can be ensured that the intelligent power module has the ability to withstand surge current and shut down safely in a short time during application, avoiding problems of the intelligent power module being solved only during the later verification of the whole machine. The early verification can greatly save verification time and resource costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a schematic structural diagram of a test circuit for an intelligent power module according to an embodiment of the present invention.

[0022] Figure numerals: main circuit 10, first capacitor 11, load inductor 12, second insulated gate bipolar transistor 13, third insulated gate bipolar transistor 14, DC voltage input terminal 15, upper bridge integrated circuit 20, lower bridge integrated circuit 30, bootstrap circuit 40, resistor 41, diode 42, second capacitor 43, first insulated gate bipolar transistor 50. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] To ensure that intelligent power modules can withstand surge currents and shut down safely within a short period of time in applications, their ability to withstand and shut down large surge currents must be verified during the development process. Existing techniques for testing intelligent power modules' surge current tolerance and shutdown capabilities typically involve a short circuit, allowing the current to rise slowly. This is inconsistent with actual application conditions and poses a harsh test environment, leading to inaccurate test results.

[0025] One of the core concepts of the embodiment of the present utility model is that the circuit includes a main loop, an upper bridge integrated circuit, a lower bridge integrated circuit, a bootstrap circuit and a first insulated gate bipolar transistor, which can simulate the intelligent power module suddenly encountering emergencies such as short circuit or surge current during application, and realizes the ability of testing the insulated gate bipolar transistor in the intelligent power module encountering surge current during operation and shutting down in the process of bearing the surge current. Before the intelligent power module is packaged, it can be ensured that the intelligent power module has the ability to withstand surge current and shut down safely in a short time during application, avoiding problems of the intelligent power module being solved only during the later verification of the whole machine. The early verification can greatly save verification time and resource costs.

[0026] Reference Figure 1 , shows a structural schematic diagram of a test circuit of an intelligent power module according to an embodiment of the present utility model, which specifically includes a main loop 10, an upper bridge integrated circuit 20, a lower bridge integrated circuit 30, a bootstrap circuit 40 and a first insulated gate bipolar transistor 50.

[0027] The main circuit 10 includes a first capacitor 11, a load inductor 12, a second insulated gate bipolar transistor 13 and a third insulated gate bipolar transistor 14; the load inductor 12 is located between the emitter of the second insulated gate bipolar transistor 13 and the collector of the third insulated gate bipolar transistor 14; one end of the first capacitor 11 is connected to the collector of the second insulated gate bipolar transistor and to the DC voltage input terminal 15, and the other end is connected to the emitter of the third insulated gate bipolar transistor 14; the emitter of the third insulated gate bipolar transistor 14 is grounded.

[0028] The first output terminal LO of the lower bridge integrated circuit 30 (corresponding to the attached Figure 1 Pin 6) is connected to the gate of the third insulated gate bipolar transistor 14, and is used to receive the first pulse width modulated square wave and control the working state of the third insulated gate bipolar transistor 14.

[0029] Pulse Width Modulation (PWM) is a technique for controlling the power or amplitude of an analog signal by adjusting the width of its pulses. In PWM, the signal's frequency is typically kept constant, while the pulse width (i.e., the duration of the high level) is adjusted as needed. The most common PWM signal form is the square wave. A square wave is a periodic signal characterized by switching between high and low levels within a cycle, with the high and low levels having equal or unequal durations. In a PWM square wave, the duration of the high level (i.e., the pulse width) determines the effective value of the signal.

[0030] The LIN terminal of the lower bridge integrated circuit 30 (corresponding to the attached Figure 1 Pin 5 in is used to receive a first pulse width modulated square wave, and when the received first pulse width modulated square wave is a high level signal, controls the third insulated gate bipolar transistor 14 to be turned on, and when the received first pulse width modulated square wave is a low level signal, controls the third insulated gate bipolar transistor 14 to be turned on.

[0031] The first output terminal HO of the upper bridge integrated circuit 20 (corresponding to the Figure 1 Pin 4) is connected to the gate of the second insulated gate bipolar transistor 13, and is used to receive the second pulse width modulated square wave to control the working state of the second insulated gate bipolar transistor 13.

[0032] The HIN terminal of the upper bridge integrated circuit 20 (corresponding to the Figure 1 Pin 3 in is used to receive a second pulse width modulated square wave, and when the received second pulse width modulated square wave is a high level signal, controls the second insulated gate bipolar transistor 13 to be turned on, and when the received second pulse width modulated square wave is a low level signal, controls the second insulated gate bipolar transistor 13 to be turned on.

[0033] The bootstrap circuit 40 is connected to the upper bridge integrated circuit 20 and the emitter of the second insulated gate bipolar transistor 13, and is configured to generate a voltage difference between the gate and the emitter of the second insulated gate bipolar transistor 13 to turn on the second insulated gate bipolar transistor 13 when the third insulated gate bipolar transistor 14 is turned on and the upper bridge integrated circuit receives a high level.

[0034] The collector of the first insulated gate bipolar transistor 50 is arranged between the emitter of the second insulated gate bipolar transistor 13 and the load inductor 12, and the emitter is arranged between the collector of the third insulated gate bipolar transistor 14 and the load inductor 12, and is used to receive the third pulse width modulated square wave. When the received third pulse width modulated square wave is at a high level, the first insulated gate bipolar transistor 50 is turned on to short-circuit the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 in the on state, so as to test the short-circuit withstand time, short-circuit current and short-circuit turn-off instantaneous peak voltage of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14.

[0035] The test circuit main loop of the intelligent power module of the embodiment of the utility model, the upper bridge integrated circuit, the lower bridge integrated circuit, the bootstrap circuit and the first insulated gate bipolar transistor, the main loop includes a first capacitor, a load inductor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor, the load inductor is located between the emitter of the second insulated gate bipolar transistor and the collector of the third insulated gate bipolar transistor, one end of the first capacitor is connected to the collector of the second insulated gate bipolar transistor and to the DC voltage input end, the other end is connected to the emitter of the third insulated gate bipolar transistor, and the emitter of the third insulated gate bipolar transistor is grounded; the first output end of the lower bridge integrated circuit is connected to the gate of the third insulated gate bipolar transistor for receiving a first pulse width modulation square wave and controlling the working state of the third insulated gate bipolar transistor; the first output end of the upper bridge integrated circuit is connected to the gate of the second insulated gate bipolar transistor for receiving a second pulse width modulation square wave The bootstrap circuit is connected to the upper bridge integrated circuit and the emitter of the second insulated gate bipolar transistor, and is used to generate a voltage difference between the gate and the emitter of the second insulated gate bipolar transistor to turn on the second insulated gate bipolar transistor when the third insulated gate bipolar transistor is turned on and the upper bridge integrated circuit receives a high level. The collector of the first insulated gate bipolar transistor is arranged between the emitter of the second insulated gate bipolar transistor and the load inductor, and the emitter is arranged between the collector of the third insulated gate bipolar transistor and the load inductor, and is used to receive the third pulse width modulated square wave and be turned on when the received third pulse width modulated square wave is a high level, so as to short-circuit the second insulated gate bipolar transistor and the third insulated gate bipolar transistor in the turned-on state, so as to test the short-circuit withstand time, short-circuit current and short-circuit turn-off instantaneous peak voltage of the second insulated gate bipolar transistor and the third insulated gate bipolar transistor.

[0036] The embodiment of the present utility model controls the timing to turn on and off the first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the third insulated gate bipolar transistor in sequence, and can simulate the intelligent power module suddenly encountering an emergency situation such as a short circuit or surge current during application. It realizes the ability of the insulated gate bipolar transistor in the intelligent power module to encounter a surge current during operation and to shut down in the process of withstanding the surge current. Before the intelligent power module is packaged, it can be ensured that the intelligent power module has the ability to withstand the surge current and shut down safely in a short time during application, avoiding the problem of the intelligent power module being solved only during the later verification of the whole machine. The early verification can greatly save verification time and resource costs.

[0037] In the embodiment of the present utility model, the bootstrap circuit 40 includes a resistor 41, a diode 42 and a second capacitor 43 connected in sequence; one end of the second capacitor 43 is set between the emitter of the second insulated gate bipolar transistor 13 and the load inductor 12; one end of the resistor 41 is connected to the power input terminal VCC of the upper bridge integrated circuit 20 (corresponding to the attached Figure 1 The bootstrap circuit 40 is used to charge the second capacitor 43 when the third insulated gate bipolar transistor 14 is turned on. When the third insulated gate bipolar transistor 14 is turned on, the second capacitor 43 forms a loop through the third insulated gate bipolar transistor 14 to charge.

[0038] For example, a power supply unit provides a 15V output to the upper bridge integrated circuit 20 and the lower bridge integrated circuit 30. A high voltage is input to the DC voltage input terminal connected to one end of the first capacitor. The timing of the pulse-width modulated square wave signal is then controlled to first provide the first pulse-width modulated square wave to the lower bridge integrated circuit 30. When the LIN terminal of the lower bridge integrated circuit 30 is high, the MOSFET between VCC and LO in the lower bridge integrated circuit 30 turns on, the LO pin outputs 15V, the voltage difference between LO and COM (common ground) is 15V, and the second insulated gate bipolar transistor 13 turns on. When the second insulated gate bipolar transistor 13 is turned on, the second capacitor 43 in the bootstrap circuit 40 forms a loop through the second insulated gate bipolar transistor 13, charging the second capacitor 43.

[0039] In the embodiment of the present invention, the first input terminal VCC (corresponding to the attached Figure 1 Pin 1 in the input terminal is used to receive the power supply voltage; the second input terminal LIN (corresponding to the Figure 1 pin 3) is used to receive a first pulse width modulated square wave; the lower bridge integrated circuit 30 is used to control the third insulated gate bipolar transistor 14 to turn on when the first pulse width modulated square wave received at the second input terminal is high.

[0040] In the embodiment of the present invention, the second output terminal VB of the upper bridge integrated circuit 20 (corresponding to the attached Figure 1 Pin 2 in the figure is provided between the diode 42 and the second capacitor 43, and the third output terminal VS (corresponding to the attached Figure 1 Pin 6 in the upper bridge integrated circuit 20 is arranged between the second capacitor 43 and the emitter of the second insulated gate bipolar transistor 13; the upper bridge integrated circuit 20 is used to generate a voltage difference between the first output terminal HO and the third output terminal VS of the upper bridge integrated circuit 20 when the received second pulse width modulated square wave is at a high level and the second capacitor 43 is charged to a preset value, so as to control the second insulated gate bipolar transistor 13 to be turned on.

[0041] For example, when the second insulated gate bipolar transistor 13 is turned on, the second capacitor 43 in the bootstrap circuit 40 forms a loop through the second insulated gate bipolar transistor 13, charging the second capacitor 43. When the second capacitor 43 is charged to 15V, the voltage difference between the second output terminal VB and the third output terminal VS of the upper bridge integrated circuit 20 is 15V. A second pulse-width modulated square wave is then provided to the upper bridge integrated circuit 20. When the HIN terminal of the bridge integrated circuit 20 is at a high level, the MOSFET between VB and HO of the bridge integrated circuit 20 is turned on, the voltage difference between the first output terminal HO and the third output terminal VS is 15V, and the second insulated gate bipolar transistor 13 is turned on. When the second insulated gate bipolar transistor 13 is turned on, the VS voltage is the high voltage of the DC voltage input terminal, and the VB voltage is the high voltage +15V of the DC voltage input terminal. Due to the load inductance 12, the current in the main loop 10 will slowly increase after the second and third insulated gate bipolar transistors 13 and 14 are turned on.

[0042] In the embodiment of the present invention, the upper bridge integrated circuit 20 is configured to control the second insulated gate bipolar transistor 13 to be turned off when the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 are short-circuited and the received second pulse-width modulated square wave is at a low level. The lower bridge integrated circuit 30 is configured to control the third insulated gate bipolar transistor 14 to be turned off when the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 are short-circuited and the received first pulse-width modulated square wave is at a low level.

[0043] Illustratively, after the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 are turned on, the current in the main loop 10 slowly rises. When the current in the main loop 10 rises to a certain value, for example, after rising to the rated operating voltage value of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14, the third pulse width modulation square wave controls the gate voltage of the first insulated gate bipolar transistor 50 to a high level, and the first insulated gate bipolar transistor 50 is turned on. Since the first insulated gate bipolar transistor 50 is turned on, the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 are in a short-circuited state, and the current in the main loop 10 quickly rises to a surge current approximately 3 to 4 times the rated current of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14. By turning on the first insulated gate bipolar transistor 50, the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 are short-circuited, and the current of the main loop 10 quickly rises to a surge current that is approximately 3 to 4 times the rated current of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14. This avoids the problem of premature short circuit, slow current rise, and inaccurate test results caused by the inconsistent working conditions of actual applications and the poor test environment.

[0044] When the second IGBT 13 and the third IGBT 14 are short-circuited, the second pulse-width modulated square wave received by the upper-bridge integrated circuit 20 is controlled to be at a low level, and the second pulse-width modulated square wave received by the lower-bridge integrated circuit 30 is controlled to be at a low level, thereby turning off the second IGBT 13 and the third IGBT 14. After the second IGBT 13 and the third IGBT 14 are simultaneously turned off, their own current drops sharply, generating a large di / dt. Due to the di / dt, a large self-inductance voltage is generated across the second IGBT 13 and the third IGBT 14. di / dt represents the derivative of current (i) with respect to time (t), that is, the rate of change of current with time.

[0045] By adjusting the turn-on time of the first insulated gate bipolar transistor 50 and the turn-off time of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14, the short-circuit pulse width of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 is controlled, and a single pulse width modulated square wave is triggered until the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 explode. The short-circuit withstand time, short-circuit current, and short-circuit turn-off instantaneous peak voltage of the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 are obtained. The second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 suddenly short-circuit during the turn-on process, withstand high voltage and surge current in a short period of time, and turn off until the current drops to zero, completing the detection. For example, the second insulated gate bipolar transistor 13 and the third insulated gate bipolar transistor 14 can be the same model.

[0046] In the embodiment of the present utility model, the second output terminal FO of the lower bridge integrated circuit 30 (corresponding to the attached Figure 1 Pin 2 in the lower bridge integrated circuit 30 is used to indicate the detected fault state, and the third output terminal CSC of the lower bridge integrated circuit 30 (corresponding to the Figure 1 Pin 8 in the MOSFET is used to detect voltage.

[0047] The VB and VS terminals of the upper bridge integrated circuit 20 are high voltage. Voltage fluctuations on the main circuit 10 during shutdown can affect the upper bridge integrated circuit 20 through the VS terminal. The VCC and LO terminals of the lower bridge integrated circuit 30 are low voltage and feature overcurrent detection and protection. If the second or third insulated gate bipolar transistor 13, 14 in the main circuit 10 fails, causing a sudden current change, the overcurrent protection function will be triggered when the CSC pin detection voltage of the lower bridge integrated circuit 30 is ≥ 0.5V. This circuit can evaluate the short-circuit withstand capability and shutdown capability of the second and third insulated gate bipolar transistors 13, 14 under surge current based on the withstand time, short-circuit current, and peak voltage obtained during short-circuit testing. This circuit can simulate and verify the intelligent power module's unexpected short-circuit or surge current conditions during application. It can also test the high-voltage withstand capability of the upper bridge integrated circuit 20 and the overcurrent detection and protection function of the lower bridge integrated circuit 30, eliminating any issues before packaging into an intelligent power module, improving module reliability and reducing manufacturing costs.

[0048] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0049] The above is a detailed introduction to the test circuit of an intelligent power module provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A test circuit for an intelligent power module, characterized in that: The circuit includes a main loop, an upper bridge integrated circuit, a lower bridge integrated circuit, a bootstrap circuit and a first insulated gate bipolar transistor; The main circuit includes a first capacitor, a load inductor, a second insulated gate bipolar transistor, and a third insulated gate bipolar transistor; the load inductor is located between the emitter of the second insulated gate bipolar transistor and the collector of the third insulated gate bipolar transistor; one end of the first capacitor is connected to the collector of the second insulated gate bipolar transistor and to the DC voltage input terminal, and the other end is connected to the emitter of the third insulated gate bipolar transistor; the emitter of the third insulated gate bipolar transistor is grounded; The first output terminal of the lower bridge integrated circuit is connected to the gate of the third insulated gate bipolar transistor, and is used to receive a first pulse width modulated square wave to control the working state of the third insulated gate bipolar transistor; The first output terminal of the upper bridge integrated circuit is connected to the gate of the second insulated gate bipolar transistor, and is used to receive a second pulse width modulated square wave to control the working state of the second insulated gate bipolar transistor; The bootstrap circuit is connected to the upper bridge integrated circuit and the emitter of the second insulated gate bipolar transistor, and is configured to generate a voltage difference between the gate and the emitter of the second insulated gate bipolar transistor to turn on the second insulated gate bipolar transistor when the third insulated gate bipolar transistor is turned on and the upper bridge integrated circuit receives a high level; The collector of the first insulated gate bipolar transistor is arranged between the emitter of the second insulated gate bipolar transistor and the load inductor, and the emitter is arranged between the collector of the third insulated gate bipolar transistor and the load inductor, and is used to receive a third pulse width modulated square wave. When the received third pulse width modulated square wave is at a high level, the first insulated gate bipolar transistor is turned on to short-circuit the second insulated gate bipolar transistor and the third insulated gate bipolar transistor in the on state, so as to test the short-circuit withstand time, short-circuit current and short-circuit shutdown instantaneous peak voltage of the second insulated gate bipolar transistor and the third insulated gate bipolar transistor.

2. The circuit according to claim 1, wherein: The bootstrap circuit includes a resistor, a diode and a second capacitor connected in sequence; one end of the second capacitor is arranged between the emitter of the second insulated gate bipolar transistor and the load inductor; one end of the resistor is connected to the power input terminal of the upper bridge integrated circuit; the bootstrap circuit is used to charge the second capacitor when the third insulated gate bipolar transistor is turned on.

3. The circuit according to claim 2, characterized in that The second output terminal of the upper bridge integrated circuit is arranged between the diode and the second capacitor, and the third output terminal is arranged between the second capacitor and the emitter of the second insulated gate bipolar transistor; the upper bridge integrated circuit is used to generate a voltage difference between the first output terminal and the third output terminal of the upper bridge integrated circuit when the received second pulse width modulated square wave is at a high level and the second capacitor is charged to a preset value, so as to control the second insulated gate bipolar transistor to be turned on.

4. The circuit according to claim 1, wherein: The upper bridge integrated circuit is used to control the second insulated gate bipolar transistor to be disconnected when the second insulated gate bipolar transistor and the third insulated gate bipolar transistor are short-circuited and the received second pulse width modulation square wave is at a low level.

5. The circuit according to claim 1, wherein: The first input terminal of the lower bridge integrated circuit is used to receive a power supply voltage; the second input terminal is used to receive a first pulse width modulated square wave; the lower bridge integrated circuit is used to control the third insulated gate bipolar transistor to turn on when the first pulse width modulated square wave received at the second input terminal is at a high level.

6. The circuit according to claim 1, wherein: The lower bridge integrated circuit is used to receive a first pulse width modulation square wave of a low level and control the third insulated gate bipolar transistor to be disconnected when the second insulated gate bipolar transistor and the third insulated gate bipolar transistor are short-circuited.

7. The circuit according to claim 1, wherein: The second output terminal of the low bridge integrated circuit is used to indicate a detected fault state.

8. The circuit according to claim 1, wherein: The third output terminal of the lower bridge integrated circuit is used for detecting voltage.

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