SAR ADC capacitor array control circuit for stabilizing common-mode voltage

Abstract

The utility model relates to the technical field of integrated circuit design, in particular to an SAR ADC capacitor array control circuit capable of stabilizing common-mode voltage. The circuit comprises an input module, a capacitor array module, a comparison module and an output module, the input module comprises an input voltage VIP, an input voltage VIN and a bootstrap switch, the capacitor array module comprises a P-end capacitor array, an N-end capacitor array and a change-over switch, the output module comprises an output voltage OUTN and an output voltage OUTP, the input module is connected with the capacitor array module, and the comparison module is connected with the output module. The capacitor array module is connected with the comparison module which is connected with the output module. According to the utility model, by adjusting the initial potential of the capacitor array and the potential switching during successive comparison, the common-mode voltage is gradually close to VREF / 2, so that the common-mode voltage is stabilized, the stability of the common-mode level is realized by utilizing the capacitor array, and an additional calibration module is not needed.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuit design, in particular to a SARADC capacitor array control circuit for stabilizing common mode voltage. Background Art

[0002] A successive approximation analog-to-digital converter (A / D converter) consists of a sample-and-hold circuit, a digital-to-analog converter (DAC), a comparator, and digital control logic. Because the input signal amplitude continuously varies, the conversion from analog to digital requires the sampling circuit to select a limited number of voltage values ​​for conversion. The more bits the A / D converter has, the more accurate the conversion result. The voltage sampled during each conversion cycle is stored in a hold circuit to ensure that the sampled voltage remains constant during the comparison process, thus ensuring the accuracy of the A / D conversion result. The comparator compares the sampled input voltage with a reference voltage. Combined with the subsequent digital control circuitry, the comparison result is fed back to the A / D converter circuit, which dynamically adjusts the reference voltage to gradually approach the sampled input voltage. Each comparison result is stored in a register in the digital circuit. After multiple comparison cycles, the least significant bit of the register is determined, resulting in the desired digitally encoded signal.

[0003] When using the above-mentioned successive approximation analog-to-digital converter, the voltage sampled in each conversion cycle needs to be stored in a holding circuit, resulting in an excessively large internal common-mode voltage. Furthermore, due to the excessive number of internal switches, a lot of circuit power consumption is generated, affecting the voltage comparison results and even causing inaccurate analog-to-digital conversion results. Therefore, we propose a SAR ADC capacitor array control circuit with a stable common-mode voltage. Utility Model Content

[0004] The purpose of the present invention is to provide a SAR ADC capacitor array control circuit with a stable common-mode voltage, so as to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above objectives, the present invention provides a SAR ADC capacitor array control circuit with a stable common-mode voltage, comprising an input module, a capacitor array module, a comparison module, and an output module. The input module comprises an input voltage VIP, an input voltage VIN, and a bootstrap switch. The capacitor array module comprises a P-terminal capacitor array, an N-terminal capacitor array, and a switch. The output module comprises an output voltage OUTN and an output voltage OUTP. The input module is connected to the capacitor array module, the capacitor array module is connected to the comparison module, and the comparison module is connected to the output module.

[0006] Turn off the bootstrap switch, and the bottom plate of the capacitor array module is set to VREF and GND respectively according to whether it is an odd or even bit. The input voltage VIP and the input voltage VIN are sampled and processed, and then enter the first comparison stage. According to the initial connection to VREF, the side with the lower level is judged to turn the corresponding switch to GND, and the other side remains unchanged at VREF. The VP terminal voltage and the VN terminal voltage are transmitted to the dynamic comparator of the comparison module for comparison. According to the different results obtained, the second and third comparison stages are entered, thereby stabilizing the common-mode voltage at VREF / 2.

[0007] As a further improvement of the present technical solution, the P-end capacitor array of the capacitor array module includes capacitors CP3, CP2, CP1 and CP0, and corresponding switches SP3, SP2, SP1 and SP0;

[0008] The capacitors CP3, CP2, CP1 and CP0 are connected in parallel with each other. The upper plates of the capacitors CP3, CP2, CP1 and CP0 are connected to the positive input of the dynamic comparator COMP and the output of the bootstrap switch with VIP input. The lower plates of the capacitors CP3, CP2, CP1 and CP0 are connected to the switching switches SP3, SP2, SP1 and SP0 controlled by the output control signal of the SAR control logic circuit, and are respectively connected to VREF / GND.

[0009] As a further improvement of the present technical solution, the N-end capacitor array of the capacitor array module includes capacitors CN3, CN2, CN1 and CN0, and corresponding switches SN3, SN2, SN1 and SN0;

[0010] The capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected in parallel with each other. The upper plates of the capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected to the negative input end of the dynamic comparator COMP and the output end of the bootstrap switch whose input is VIN. The lower plates of the capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected to the switching switches SN3, SN2, SN1 and SN0 controlled by the output control signal of the SAR control logic circuit, and are respectively connected to VREF / GND.

[0011] As a further improvement of the present technical solution, the capacitance ratio in the P-end capacitor array is capacitor CP3: capacitor CP2: capacitor CP1: capacitor CP0 = 8:4:2:1, and the capacitance ratio in the N-end capacitor array is capacitor CN3: capacitor CN2: capacitor CN1: capacitor CN0 = 8:4:2:1.

[0012] As a further improvement of the present technical solution, the switching switch of the capacitor array module initially sets the capacitors in the even positions to GND and the capacitors in the odd positions to VREF, that is, capacitors CP3, CP1, CN3, and CN1 are connected to VREF, and capacitors CP2, CP0, CN2, and CN0 are connected to GND.

[0013] As a further improvement of the present technical solution, a bootstrap switch is provided between the input voltage of the input module and the capacitor array module, and the bootstrap switch controls the sampling process of the capacitor array module by using its own on-off function.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] This SAR ADC capacitor array control circuit for stabilizing common-mode voltage turns off the bootstrap switch, sets the odd-numbered bits of the capacitor base to VREF and the even-numbered bits to GND, samples the voltages at the P and N terminals, and then enters the first comparison phase. For the capacitor group initially connected to VREF, if the voltage level is judged to be low, the switch of the corresponding capacitor is switched to GND; for the capacitor group initially connected to GND, if the voltage level is judged to be high, the switch of the corresponding capacitor is switched to VREF. By adjusting the initial potential of the capacitor array and the potential switching during successive comparisons, the common-mode voltage gradually approaches VREF / 2, thereby stabilizing the common-mode level. This method innovatively utilizes the capacitor array itself to achieve common-mode voltage stabilization, eliminating the need for an additional calibration module. By simplifying the control logic and the number of switches, this method eliminates the need for an additional calibration module, reduces circuit power consumption and occupied layout area, and improves the linearity of the SAR ADC. By reducing the number of switches and the complexity of the control logic, a high-precision and high-linearity ADC is achieved through intelligent control of the capacitor array. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the overall module of the utility model 1;

[0017] Figure 2 This is the SAR ADC capacitor array circuit diagram of the utility model 1;

[0018] Figure 3 This is a schematic diagram of the successive comparison structure of the utility model 1. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0020] The successive approximation analog-to-digital converter (A / D converter) consists of a sample-and-hold circuit, a digital-to-analog converter (DAC), a comparator, and digital control logic. Since the input signal amplitude changes continuously, the conversion from analog to digital can only be achieved by selecting a limited number of voltage values ​​through the sampling circuit and converting them into digital signals. The more bits the A / D converter has, the more accurate the conversion result will be. The voltage sampled in each conversion cycle needs to be stored in a holding circuit so that the sampled voltage does not change during the comparison process, thereby ensuring the accuracy of the A / D conversion result. The comparator compares the sampled input voltage with the reference voltage, and in conjunction with the subsequent digital control circuit, feeds the comparison result back to the A / D converter circuit, and then dynamically adjusts the reference voltage so that the reference voltage gradually approaches the sampled input voltage. Each comparison result will be stored in the register of the digital circuit. After multiple comparison cycles, the least significant bit of the register is determined, and the final required digital coding signal is obtained. Please refer to Figure 1-Figure 3 As shown, the utility model provides a SAR ADC capacitor array control circuit with a stable common-mode voltage, comprising an input module, a capacitor array module, a comparison module and an output module, wherein the input module comprises an input voltage VIP, an input voltage VIN and a bootstrap switch, the capacitor array module comprises a P-terminal capacitor array, an N-terminal capacitor array and a switching switch, the output module comprises an output voltage OUTN and an output voltage OUTP, the input module is connected to the capacitor array module, the capacitor array module is connected to the comparison module, and the comparison module is connected to the output module;

[0021] Turn off the bootstrap switch, and the bottom plate of the capacitor array module is set to VREF and GND respectively according to whether it is an odd or even bit. The input voltage VIP and the input voltage VIN are sampled and processed, and then enter the first comparison stage. According to the initial connection to VREF, the side with the lower level is judged to turn the corresponding switch to GND, and the other side remains unchanged at VREF. The VP terminal voltage and the VN terminal voltage are transmitted to the dynamic comparator of the comparison module for comparison. According to the different results obtained, the second and third comparison stages are entered, thereby stabilizing the common-mode voltage at VREF / 2.

[0022] Principle: This SAR ADC capacitor array control circuit for stabilizing common-mode voltage turns off the bootstrap switch, sets the odd-numbered bits of the capacitor base to VREF and the even-numbered bits to GND, samples the voltages at the P and N terminals, and then enters the first comparison phase. For the capacitor group initially connected to VREF, if the voltage level is judged to be low, the corresponding capacitor switch is switched to GND; for the capacitor group initially connected to GND, if the voltage level is judged to be high, the corresponding capacitor switch is switched to VREF. By adjusting the initial potential of the capacitor array and the potential switching during successive comparisons, the common-mode voltage gradually approaches VREF / 2, thereby stabilizing the common-mode level. This method innovatively utilizes the capacitor array itself to stabilize the common-mode level, eliminating the need for an additional calibration module. By simplifying the control logic and the number of switches, this method reduces circuit power consumption and occupied layout area, and improves the linearity of the SAR ADC. It reduces the number of switches and the complexity of the control logic, achieving a high-precision and high-linearity ADC through intelligent control of the capacitor array.

[0023] In order to implement the sampling processing of the input voltage VIP by the P-end capacitor array, the P-end capacitor array of the capacitor array module includes capacitors CP3, CP2, CP1 and CP0, and corresponding switching switches SP3, SP2, SP1 and SP0;

[0024] Capacitor CP3, capacitor CP2, capacitor CP1 and capacitor CP0 are connected in parallel with each other. The upper plates of capacitor CP3, capacitor CP2, capacitor CP1 and capacitor CP0 are connected to the positive input of dynamic comparator COMP and the output of bootstrap switch with VIP input. The lower plates of capacitor CP3, capacitor CP2, capacitor CP1 and capacitor CP0 are connected to switching switches SP3, SP2, SP1 and SP0 controlled by the output control signal of SAR control logic circuit, and are connected to VREF / GND respectively.

[0025] In the initial stage, by turning off the bootstrap switch, capacitors CP3 and CP1 are connected to VREF, capacitors CP2 and CP0 are connected to GND, and the input voltage VIP of the P-end capacitor array is sampled by utilizing the energy storage characteristics of the capacitors.

[0026] In order to implement the sampling processing of the input voltage VIN by the N-terminal capacitor array, the N-terminal capacitor array of the capacitor array module includes capacitors CN3, CN2, CN1 and CN0, and corresponding switching switches SN3, SN2, SN1 and SN0;

[0027] Capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected in parallel. The upper plates of capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected to the negative input terminal of the dynamic comparator COMP and the output terminal of the bootstrap switch whose input is VIN. The lower plates of capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected to the switching switches SN3, SN2, SN1 and SN0 controlled by the output control signal of the SAR control logic circuit, and are respectively connected to VREF / GND.

[0028] In the initial stage, by turning off the bootstrap switch, capacitors CN3 and CN1 are connected to VREF, capacitors CN2 and CN0 are connected to GND, and the input voltage VIP of the N-terminal capacitor array is sampled by utilizing the energy storage characteristics of the capacitors.

[0029] After sampling the P-terminal voltage VIP and the N-terminal voltage VIN, the first comparison phase begins. Initially, VREF is connected. The side that determines the voltage level is low will turn the corresponding switch to GND, and the other side will remain unchanged at VREF. If the voltage at the VP terminal is greater than the voltage at the VN terminal, the bottom plate voltage at the VN terminal is set to GND, and the bottom plate voltage at the VP terminal remains unchanged at VREF, that is, SN3 is set to GND, and SP3 maintains the VREF potential. If the voltage at the VP terminal is less than the voltage at the VN terminal, the bottom plate voltage at the VN terminal remains unchanged at VREF, and the bottom plate voltage at the VP terminal is set to GND, that is, SP3 is set to GND, and SN3 maintains the VREF potential.

[0030] Entering the second comparison stage, since it is initially connected to GND, the switch corresponding to the side with a higher level is turned to VREF, and the other side remains unchanged at GND; if the voltage at the VP terminal is greater than the voltage at the VN terminal, the bottom plate voltage at the VN terminal remains unchanged at GND, and the bottom plate voltage at the VP terminal is set to VREF, that is, SP2 is set to VREF, and SN2 remains at GND potential; if the voltage at the VP terminal is less than the voltage at the VN terminal, the bottom plate voltage at the VN terminal is set to VREF, and the bottom plate voltage at the VP terminal remains unchanged at GND, that is, SN2 is set to VREF, and SP2 remains at GND potential;

[0031] Entering the third comparison stage, since VREF is initially connected, the party that determines the level is low will turn the corresponding switch to GND, and the other end remains unchanged at VREF; if the voltage at the VP terminal is greater than the voltage at the VN terminal, the bottom plate voltage at the VN terminal is set to GND, and the bottom plate voltage at the VP terminal remains unchanged at VREF, that is, SN1 is set to GND and SP1 maintains the VREF potential; if the voltage at the VP terminal is less than the voltage at the VN terminal, the bottom plate voltage at the VN terminal remains unchanged at VREF, the bottom plate voltage at the VP terminal is set to GND, that is, SP1 is set to GND and SN1 maintains the VREF potential;

[0032] Similarly, for the capacitor group initially connected to VREF, when the voltage level is judged to be low, the switch of the corresponding capacitor is turned to GND; for the capacitor group initially connected to GND, when the voltage level is judged to be high, the switch of the corresponding capacitor is turned to VREF, so that the common-mode voltage in the whole process is stable within a range and gradually converges to VREF / 2.

[0033] In order to improve the control and stability of capacitance accuracy, the capacitance ratio in the P-end capacitance array is capacitance CP3: capacitance CP2: capacitance CP1: capacitance CP0 = 8:4:2:1, and the capacitance ratio in the N-end capacitance array is capacitance CN3: capacitance CN2: capacitance CN1: capacitance CN0 = 8:4:2:1. The capacitance ratios in the P-end capacitance array and the N-end capacitance array are distributed in a binary ratio. Through simple binary coding, capacitors of different capacitance values ​​can be easily selected for combination, thereby achieving a more accurate total capacitance value. The binary coding method has clear rules and certainty. The binary capacitance ratio can reduce the impact of capacitance value fluctuations caused by factors such as capacitor manufacturing errors and temperature changes on the overall accuracy, thereby improving the stability of the accuracy.

[0034] In order to more conveniently confirm the initial potential of the capacitor connection, the switch of the capacitor array module is initially set to fix the capacitors in the even positions to GND and the capacitors in the odd positions to VREF, that is, capacitors CP3, CP1, CN3, and CN1 are connected to VREF, and capacitors CP2, CP0, CN2, and CN0 are connected to GND. The determined initial state setting ensures that the corresponding capacitor positions can be quickly identified during use.

[0035] To reduce the impact of switching power consumption on the capacitor array, a bootstrap switch is placed between the input voltage of the input module and the capacitor array module. The bootstrap switch controls the sampling process of the capacitor array module by its own on-off state. The bootstrap switch typically consists of a main switch and an auxiliary switch. The main switch controls the on-off state of the circuit, while the auxiliary switch provides a high-voltage drive signal to the main switch. In the off state, both the main and auxiliary switches are turned off, cutting off the current. During this state, the auxiliary switch discharges through a diode, reducing its voltage to zero. This process ensures that the auxiliary switch can recharge and provide a high-voltage drive signal to the main switch the next time it is turned on, thereby reducing on-resistance and filtering losses.

[0036] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A SAR ADC capacitor array control circuit with stable common-mode voltage, characterized by: The system comprises an input module, a capacitor array module, a comparison module and an output module, wherein the input module comprises an input voltage VIP, an input voltage VIN and a bootstrap switch, the capacitor array module comprises a P-terminal capacitor array, an N-terminal capacitor array and a switch, the output module comprises an output voltage OUTN and an output voltage OUTP, the input module is connected to the capacitor array module, the capacitor array module is connected to the comparison module, and the comparison module is connected to the output module; Turn off the bootstrap switch, and the bottom plate of the capacitor array module is set to VREF and GND respectively according to whether it is an odd or even bit. The input voltage VIP and the input voltage VIN are sampled and processed, and then enter the first comparison stage. According to the initial connection to VREF, the side with the lower level is judged to turn the corresponding switch to GND, and the other side remains unchanged at VREF. The VP terminal voltage and the VN terminal voltage are transmitted to the dynamic comparator of the comparison module for comparison. According to the different results obtained, the second and third comparison stages are entered, thereby stabilizing the common-mode voltage at VREF / 2.

2. The SAR ADC capacitor array control circuit for stabilizing common mode voltage according to claim 1, wherein: The P-end capacitor array of the capacitor array module includes capacitors CP3, CP2, CP1 and CP0, and corresponding switches SP3, SP2, SP1 and SP0; The capacitors CP3, CP2, CP1 and CP0 are connected in parallel with each other. The upper plates of the capacitors CP3, CP2, CP1 and CP0 are connected to the positive input of the dynamic comparator COMP and the output of the bootstrap switch with VIP input. The lower plates of the capacitors CP3, CP2, CP1 and CP0 are connected to the switching switches SP3, SP2, SP1 and SP0 controlled by the output control signal of the SAR control logic circuit, and are respectively connected to VREF / GND.

3. The SAR ADC capacitor array control circuit for stabilizing common mode voltage according to claim 1, wherein: The N-end capacitor array of the capacitor array module includes capacitors CN3, CN2, CN1 and CN0, and corresponding switches SN3, SN2, SN1 and SN0; The capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected in parallel with each other. The upper plates of the capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected to the negative input end of the dynamic comparator COMP and the output end of the bootstrap switch whose input is VIN. The lower plates of the capacitor CN3, capacitor CN2, capacitor CN1 and capacitor CN0 are connected to the switching switches SN3, SN2, SN1 and SN0 controlled by the output control signal of the SAR control logic circuit, and are respectively connected to VREF / GND.

4. The SAR ADC capacitor array control circuit for stabilizing common mode voltage according to claim 1, wherein: The capacitance ratio of the P-end capacitor array is capacitor CP3: capacitor CP2: capacitor CP1: capacitor CP0 = 8:4:2:1, and the capacitance ratio of the N-end capacitor array is capacitor CN3: capacitor CN2: capacitor CN1: capacitor CN0 = 8:4:2:

1.

5. The SAR ADC capacitor array control circuit for stabilizing common mode voltage according to claim 1, wherein: Initially, the switch of the capacitor array module sets the capacitors in the even positions to GND and the capacitors in the odd positions to VREF, that is, capacitors CP3, CP1, CN3, and CN1 are connected to VREF, and capacitors CP2, CP0, CN2, and CN0 are connected to GND.

6. The SAR ADC capacitor array control circuit for stabilizing common mode voltage according to claim 1, wherein: A bootstrap switch is provided between the input voltage of the input module and the capacitor array module, and the bootstrap switch controls the sampling process of the capacitor array module by using its own on-off function.

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