Stacked multi-color microdisplay device

Abstract

The utility model discloses a stacked multicolor micro display device, and relates to the technical field of semiconductors. The micro display device comprises a driving wafer and a plurality of display device layers arranged on the driving wafer, wherein any display device layer comprises sub-pixels; a semiconductor electrode conduction structure is arranged in at least one display device layer, and the semiconductor electrode conduction structure comprises a first conduction structure arranged in the horizontal direction and a second conduction structure arranged in the vertical direction; the bottom of the second conduction structure is connected with the outer edge of the first conduction structure in the display device layer so as to surround the first conduction structure, and the top of the second conduction structure is connected with the sub-pixel in the upper display device layer or connected with the bottom of the first conduction structure in the upper display device layer; and the bottom of the first conduction structure is connected with an electrode contact in the driving wafer or is connected with the top of the second conduction structure in the lower display device layer.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a stacked multi-color micro display device. Background Art

[0002] In the field of microdisplay, in order to achieve colored display, there is a demand for multi-color stacking integration.

[0003] In related technologies, such as Figure 1 As shown, multi-color stacking is completed in the following manner: the first-layer color device 20 is metal-bonded to the side of the driving panel 10 provided with the electrode contacts through the first bonding layer; the first epitaxial layer and the first bonding layer are micro-nano processed to form the first sub-pixel 21 and the first bonding structure 22; a flat insulating purification layer 23 is provided, and the insulating passivation layer 23 is processed to form holes at positions corresponding to the second sub-pixel 31 and the third sub-pixel 41 until the electrode contacts of the driving panel 10 are exposed, and then the holes are filled with metal material to obtain the interconnected metal parts 24; the second-layer color device 30 and the third-layer color device 40 are integrated with the electrode contacts in a stacking manner similar to the first-layer color device 20.

[0004] Therefore, in order to achieve anode conduction, a process of first forming a through-hole and then metal filling is required to prepare interconnected metal parts. This process has the difficulty of graphical overlay alignment and is relatively difficult. Utility Model Content

[0005] The purpose of the utility model is to provide a stacked multi-color micro display device, which can reduce the difficulty of the process of anode conduction.

[0006] In order to achieve the above-mentioned purpose of the utility model, the utility model proposes the following technical solutions:

[0007] In one aspect, a micro display device is provided, comprising a driver wafer and a plurality of display device layers disposed on the driver wafer, wherein any of the display device layers comprises sub-pixels;

[0008] A semiconductor electrode conductive structure is provided in at least one of the display device layers, and the semiconductor electrode conductive structure includes: a first conductive structure provided in a horizontal direction and a second conductive structure provided in a vertical direction;

[0009] The bottom of the second conductive structure is connected to the outer edge of the first conductive structure in the current display device layer to surround the first conductive structure, and the top is connected to the sub-pixel in the upper display device layer, or connected to the bottom of the first conductive structure in the upper display device layer;

[0010] The bottom of the first conductive structure is connected to the electrode contact in the driving wafer, or is connected to the top of the second conductive structure in the lower display device layer.

[0011] In a possible implementation, the horizontal size of the semiconductor electrode conductive structure in the lower display device layer is smaller than or equal to the horizontal size of the semiconductor electrode conductive structure in the upper display device layer.

[0012] In a possible implementation, a horizontal dimension of a semiconductor electrode conductive structure in the first display device layer directly connected to the driver wafer is greater than or equal to a horizontal dimension of an electrode contact in the driver wafer.

[0013] In one possible implementation, an epitaxial structure is provided inside the semiconductor electrode conductive structure, the bottom of the epitaxial structure is connected to the upper surface of the first conductive structure in the current display device layer, and the top is connected to the lower surface of the first conductive structure in the previous display device layer.

[0014] In a possible implementation, the size of the epitaxial structure is smaller than or equal to the size of a sub-pixel in the same display device layer.

[0015] In a possible implementation, the sidewall of the epitaxial structure is connected to the inner sidewall of the semiconductor electrode conductive structure;

[0016] or,

[0017] An insulating medium is provided between the sidewall of the epitaxial structure and the inner sidewall of the semiconductor electrode conductive structure.

[0018] In a possible implementation, the first conductive structure is consistent with the structure of the bottom metal layer of the sub-pixel;

[0019] The bottom metal layer includes: a bonding metal layer and a first ohmic contact layer vertically stacked in a direction away from the driving wafer.

[0020] In a possible implementation, an Omni-Direction Reflector (ODR) insulating layer is further provided between the bonding metal layer and the first ohmic contact layer, and the ODR insulating layer and the bonding metal layer form an ODR structure.

[0021] In a possible implementation, the thickness of the bonding metal layer is between 10 nm and 1.5 um.

[0022] In a possible implementation, the thickness of the first ohmic contact layer is between 5 nm and 300 nm.

[0023] In a possible implementation, the top height of the second conductive structure is flush with the top height of a sub-pixel in the same display device layer.

[0024] In one possible implementation, the outer periphery of the sub-pixel is surrounded by a metal fence structure that is structurally consistent with the second conductive structure, and the bottom of the metal fence structure is connected to the bonding metal layer at the bottom of the sub-pixel and the outer edge of the first ohmic contact layer to surround the sub-pixel.

[0025] In a possible implementation, the top height of the metal fence is the same as the top height of the semiconductor electrode conductive structure in the same layer.

[0026] In a possible implementation, the inner wall of the metal fence structure is provided with a high reflective layer.

[0027] In a possible implementation, the thickness of the second conductive structure is between 10 nm and 1500 nm.

[0028] In a possible implementation, the angle of the metal fence structure is between 45 degrees and 135 degrees.

[0029] In a possible implementation, the sub-pixels in each display device layer are electrically connected via a transparent conductive layer on a surface of a side away from the driving wafer.

[0030] In a possible implementation, in the top display device layer, the insulating layer is entirely filled in the top display device layer.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] Provided is a stacked multi-color micro-display device, comprising multiple display device layers, wherein at least one display device layer is provided with a semiconductor electrode conduction structure, the semiconductor electrode conduction structure comprising: a first conduction structure arranged in the horizontal direction and a second conduction structure arranged in the vertical direction; the bottom of the second conduction structure is connected to the outer edge of the first conduction structure in the display device layer to surround the first conduction structure, and the top is connected to the sub-pixels in the upper display device layer, or to the bottom of the first conduction structure in the upper display device layer; the bottom of the first conduction structure is connected to the electrode contact in the driver wafer, or to the top of the second conduction structure in the lower display device layer, thereby achieving anode conduction through this fence-style semiconductor electrode conduction structure, eliminating the need for a process of first through-hole and then metal filling, thereby reducing the process difficulty of graphical overlay alignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1This is a schematic structural diagram of a stacked integrated micro-display device provided in the related art;

[0034] Figure 2 1 is a schematic structural diagram of a micro display device with a double-layer display device layer provided in an embodiment of the present application;

[0035] Figure 3 1 is a schematic structural diagram of a micro-display device having three display device layers provided in an embodiment of the present application;

[0036] Figure 4 1 is a schematic structural diagram of a micro display device with an ODR structure provided in an embodiment of the present application;

[0037] Figure 5 1 is a schematic structural diagram of a micro-display device with an epitaxial structure provided in an embodiment of the present application;

[0038] Figure 6 1 is a schematic structural diagram of a micro-display device with an epitaxial structure provided in an embodiment of the present application;

[0039] Figure 7 This is a schematic structural diagram of a micro-display device provided in an embodiment of the present application, in which a top display device layer has a metal fence structure;

[0040] Figure 8 1 is a schematic structural diagram of a micro-display device with a high reflective layer provided in an embodiment of the present application;

[0041] Figure 9 This is a schematic structural diagram of a micro-display device with an overall insulating and filling top display device layer provided in an embodiment of the present application;

[0042] Figure 10 This is a schematic structural diagram of a micro-display device with an overall insulating and filling top display device layer provided in an embodiment of the present application;

[0043] Figure 11 1 is a schematic structural diagram of a dimensionally marked micro-display device provided in an embodiment of the present application;

[0044] Figure 12 is a flow chart of a method for preparing a micro display device provided in an embodiment of the present application;

[0045] Figure 13 is a schematic diagram of a preparation process of a non-top display device layer provided in an embodiment of the present application;

[0046] Figure 14 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0047] Figure 15 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0048] Figure 16 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0049] Figure 17 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0050] Figure 18 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0051] Figure 19 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0052] Figure 20 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0053] Figure 21 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0054] Figure 22 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0055] Figure 23 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0056] Figure 24 Schematic diagram of a process for preparing a semiconductor electrode conductive structure provided in an embodiment of the present application;

[0057] Figure 25 is a schematic diagram of a preparation process of a high reflective layer provided in an embodiment of the present application;

[0058] Figure 26 This is a schematic diagram of a preparation process of a high reflective layer provided in an embodiment of the present application.

[0059] Reference numerals:

[0060] 100-driving wafer, 110-electrode contact, 200-first display device layer, 210-first sub-pixel, 220-first insulating layer, 300-second display device layer, 310-second sub-pixel, 320-second insulating layer, 400-third display device layer, 410-third sub-pixel, 420-third insulating layer, 500-semiconductor electrode conduction structure 500, 510-first conduction structure, 520-second conduction structure, 610-high reflective layer, 620-ODR insulating layer, 630-bonding metal layer, 640-first ohmic contact layer, 650-epitaxial structure, 660-metal fence structure, 670-transparent conductive layer, 680-metal reinforcement structure, 690-second ohmic contact layer, 710-first layer of color compound. DETAILED DESCRIPTION

[0061] To make the purpose, technical solutions, and advantages of the present invention more clear, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0062] In the description of the present invention, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0063] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on specific circumstances.

[0064] In the embodiment of the present application, the preparation method of the micro display device is mainly changed. For the preparation of the conductive interconnection electrode in the micro display device, the process of first through-hole and then metal filling is changed. During the pixel separation, a semiconductor electrode conductive structure 500 that can achieve automatic alignment is prepared at the same time, which reduces the difficulty of graphical overlay alignment and reduces the process difficulty.

[0065] Next, the device structure proposed in this application is described.

[0066] First, the present invention provides a stacked multi-color micro display device, such as Figures 2 to 3 As shown, the micro display device includes:

[0067] A driving wafer 100 and a multi-layer display device layer arranged on the driving wafer 100, wherein any display device layer includes sub-pixels; a semiconductor electrode conduction structure 500 is arranged in at least one display device layer, and the semiconductor electrode conduction structure 500 includes: a first conduction structure 510 arranged in the horizontal direction and a second conduction structure 520 arranged in the vertical direction; the bottom of the second conduction structure 520 is connected to the outer edge of the first conduction structure 510 in the display device layer of this layer to surround the first conduction structure 510, and the top is connected to the sub-pixels in the upper display device layer, or is connected to the bottom of the first conduction structure 510 in the upper display device layer; the bottom of the first conduction structure 510 is connected to the electrode contact 110 in the driving wafer 100, or is connected to the top of the second conduction structure 520 in the lower display device layer.

[0068] In an embodiment of the present application, a micro-display device having multiple display device layers is provided. Each display device layer is provided with at least one sub-pixel, and the sub-pixels in different display device layers can be designed to emit light of different wavelengths, thereby achieving a color display. The sub-pixels in each display device layer need to be electrically connected to the electrode contacts 110 in the driver wafer 100. Therefore, in addition to the electrode contacts 110 in the first display device layer 200 being able to directly contact the electrode contacts 110 in the driver wafer 100, the sub-pixels in the second display device layer 300 and higher display device layers need to be electrically connected. For these sub-pixels, a semiconductor electrode conductive structure 500 formed by a first conductive structure 510 and a second conductive structure 520 can be used in the display device layer below to achieve electrical connection.

[0069] For example: Figure 2As shown, the micro display device has a double-layer display device layer: a first display device layer 200 and a second display device layer 300. For the second sub-pixel 310 in the second display device layer 300, a semiconductor electrode conduction structure 500 can be correspondingly set at the projection position in the first display device layer 200. The bottom of the first conduction structure 510 in the semiconductor electrode conduction structure 500 is connected to the electrode contact 110 in the driving wafer 100, and the top of the second conduction structure 520 is connected to this second sub-pixel 310.

[0070] For example: Figure 3 As shown, the micro display device has three display device layers: a first display device layer 200, a second display device layer 300 and a third display device layer 400. For the second sub-pixel 310 in the second display device layer 300, a semiconductor electrode conductive structure 500 can be correspondingly set at the projected position in the first display device layer 200, the bottom of the first conductive structure 510 in the semiconductor electrode conductive structure 500 is connected to the electrode contact 110 in the driving wafer 100, and the top of the second conductive structure 520 is connected to this second sub-pixel 310; for the third sub-pixel 410 in the third display device layer 400, a semiconductor electrode conductive structure 500 can be correspondingly set at the projected position in the first display device layer 200 and the projected position in the second display device layer 300, and the top of the second conductive structure 520 in the first display device layer 200 is connected to the bottom of the first conductive structure 510 in the second display device layer 300.

[0071] It is understandable that the electrode connection structure in the micro display device can all adopt the above-mentioned semiconductor electrode conduction structure 500, or partially adopt the above-mentioned semiconductor electrode conduction structure 500 and partially adopt other types of electrode connection structures, and this application does not limit this.

[0072] It can be understood that the preparation method of the semiconductor electrode conductive structure 500 can be an unconventional through-hole process, and its preparation can achieve self-alignment, and no longer requires the use of conventional through-hole patterning and alignment methods, thereby reducing process steps, such as: through-hole patterning and etching process steps, through-hole seed layer coating process, electroplating process, and metal flattening process after through-hole metal filling. In addition, it reduces the use of high-cost equipment, such as: electroplating and seed layer coating sputtering equipment, thereby greatly reducing the cost problem of device preparation.

[0073] The driver wafer 100 may be an active design that combines one or more of thin-film transistors (TFTs), low-temperature polysilicon (LTPS), CMOS integrated circuits, and high-mobility transistors (HEMTs). Specifically, the driver wafer 100 includes a driver circuit, which includes at least one electrode contact 110. The electrode contact 110 may have a one-to-one or many-to-one relationship with the sub-pixels, and this application does not impose any restrictions on this.

[0074] Each sub-pixel may include: a bonding metal layer 630 , a first ohmic contact layer 640 , an active layer, and a second ohmic contact layer stacked in a direction away from the driving wafer 100 .

[0075] It is understandable that the first ohmic contact layer 640 and the second ohmic contact layer in the present application can be designed to be a P-type ohmic contact layer and an N-type ohmic contact layer, respectively, or can be designed to be an N-type ohmic contact layer and a P-type ohmic contact layer, respectively.

[0076] Specifically, sub-pixels are made of compound wafer materials. The structures of some compound wafers are as follows. In some practical applications, the film layers of compound wafers will be more complex, or there will be cross-use of materials. The material range is not limited. It typically mainly includes P-type material, N-type material, and MQW quantum wells and other functional layers sandwiched between the two:

[0077]

[0078] Each display device layer may be filled with an insulating layer, and the insulating layer material may include a single film layer such as silicon oxide, silicon nitride, aluminum oxide, boron nitride, or a stack of two or more materials thereof.

[0079] The semiconductor electrode conductive structure 500 includes various combinations of metals such as Al, Cu, Au, Sn, Ni, Pt, and their corresponding adhesion layers or barrier layers, such as Ti, Ni, Cr, TiN, and the like.

[0080] In one possible implementation, the horizontal size of the semiconductor electrode conduction structure 500 in the lower display device layer is less than or equal to the horizontal size of the semiconductor electrode conduction structure 500 in the upper display device layer. Since the various display device layers need to be stacked and integrated, and the semiconductor electrode conduction structure 500 in the upper display device layer needs to be aligned with the semiconductor electrode conduction structure 500 in the lower display device layer, in order to reduce the difficulty of process implementation, the horizontal size of the semiconductor electrode conduction structure 500 in the lower display device layer is designed to be less than or equal to the horizontal size of the semiconductor electrode conduction structure 500 in the upper display device layer. Figure 2As shown, the horizontal size of the semiconductor electrode conductive structure 500 in the first display device layer 200 is smaller than or equal to the horizontal size of the semiconductor electrode conductive structure 500 in the second display device layer 300 .

[0081] Furthermore, the horizontal dimension of the semiconductor electrode conductive structure 500 in the first display device layer 200 directly connected to the driver wafer 100 is greater than or equal to the horizontal dimension of the electrode contact 110 in the driver wafer 100. Since the semiconductor electrode conductive structure 500 in the first display device layer 200 needs to be aligned with the electrode contact 110 in the driver wafer 100, in order to reduce the difficulty of process implementation, the horizontal dimension of the semiconductor electrode conductive structure 500 in the first display device layer 200 is designed to be equal to the horizontal dimension of the electrode contact 110 in the driver wafer 100. Figure 2 、 Figure 3 As shown, the horizontal size of the semiconductor electrode conductive structure 500 in the first display device layer 200 is greater than or equal to the horizontal size of the electrode contact 110 in the driving wafer 100 .

[0082] In a possible implementation, the second conductive structure 520 is in a fence pattern, and the thickness of the second conductive structure 520 is between 10 nm and 1500 nm.

[0083] Furthermore, the top height of the second conductive structure 520 is flush with the top height of the sub-pixels in the same display device layer. To facilitate further integration of display device layers, the semiconductor electrode conductive structure 500 of this layer can be used to provide anode conduction for the sub-pixels in the upper display device layer. Therefore, the top height of the second conductive structure 520 is set to be flush with the top height of the sub-pixels in the same display device layer.

[0084] In one possible implementation, Figure 2 、 Figure 3 As shown, the first conductive structure 500 has the same structure as the bottom metal layer of the sub-pixel; the bottom metal layer includes a bonding metal layer 630 and a first ohmic contact layer 640, which are stacked vertically away from the driver wafer 100. The bonding metal layer 630 has a thickness between 10 nm and 1.5 μm, and the first ohmic contact layer 640 has a thickness between 5 nm and 300 nm.

[0085] In this implementation, the first conductive structure 510 is formed by utilizing the bonding structure in the display device layer, thereby facilitating the preparation of the semiconductor electrode conductive structure 500 .

[0086] Further, such as Figure 4As shown, an ODR insulating layer 620 is also provided between the bonding metal layer 630 and the first ohmic contact layer 640. Thus, in the region below the first ohmic contact layer 640 of the color-based compound, an ODR structure is formed using the bonding metal layer 630 and the ODR insulating layer 620, thereby increasing the reflectivity of the region below the first ohmic contact layer 640 and thereby improving the brightness of the microdisplay device. The bonding metal layer 630 can be made of a highly reflective conductive material, and this application does not impose any restrictions on the specific material type. It is understood that, under this design, the bonding metal layer 630 and the first ohmic contact layer 640 can be electrically connected using the second conductive structure 520.

[0087] In one possible implementation, Figure 5 、 Figure 6 As shown, an epitaxial structure 650 is arranged inside the semiconductor electrode conductive structure 500, and the bottom of the epitaxial structure 650 is connected to the upper surface of the first conductive structure 510 in the current display device layer, and the top is connected to the lower surface of the first conductive structure 510 in the previous display device layer.

[0088] In this implementation, since the semiconductor electrode conductive structure 500 for conductive interconnection is annular, it is prone to collapse during the process if it is thin and has a low elastic modulus. The epitaxial structure 650 is retained within the semiconductor electrode conductive structure 500 to support the semiconductor electrode conductive structure 500, thereby resolving the collapse problem. It is understood that the epitaxial structure 650 can be provided within all semiconductor electrode conductive structures 500, or even partially, and this application is not limited thereto.

[0089] Further, such as Figure 5 As shown, the sidewalls of the epitaxial structure 650 are connected to the inner sidewalls of the semiconductor electrode conductive structure 500, so that the semiconductor electrode conductive structure 500 is attached to the sidewall surface of the epitaxial structure 650 instead of being in a suspended state, thereby solving the problem of collapse.

[0090] Further, such as Figure 6 As shown, an insulating medium is provided between the sidewalls of the epitaxial structure 650 and the inner sidewalls of the semiconductor electrode conductive structure 500. This allows the semiconductor electrode conductive structure 500 to be attached to the surface of the insulating medium while retaining the epitaxial structure 650, rather than being suspended in the air, thereby solving the problem of collapse.

[0091] The size of the epitaxial structure 650 is smaller than or equal to the size of the sub-pixels in the same display device layer. By limiting the size of the epitaxial structure 650, it is possible to avoid this part of the structure taking up too much space, thereby preventing the problem of low pixel density.

[0092] In one possible implementation, Figure 2 、 Figure 3 As shown, the outer periphery of the sub-pixel is surrounded by a metal fence structure 660 that is structurally consistent with the second conductive structure 520, and the bottom of the metal fence structure 660 is connected to the bonding metal layer 630 at the bottom of the sub-pixel and the outer edge of the first ohmic contact layer 640 to surround the sub-pixel.

[0093] In this implementation, a metal fence structure 660 similar in style to the second conductive structure 520 in the semiconductor electrode conductive structure 500 is simultaneously manufactured around the outer periphery of the sub-pixel. This metal fence structure 660 is connected to the bonding metal layer 630 at the bottom of the sub-pixel and the outer edge of the first ohmic contact layer 640. This metal fence structure 660 can block light leakage from the sidewall of the sub-pixel, thereby suppressing or even eliminating light crosstalk between adjacent sub-pixels, thereby improving the display effect of the microdisplay device.

[0094] It is understood that, in the top display device layer, if the top display device layer is filled with an insulating layer as a whole, the sub-pixels in the top display device layer can also be provided with a metal fence structure 660. Figure 7 The micro display device includes two display device layers. The first sub-pixel 210 in the first display device layer 200 is surrounded by a metal fence structure 660 , and the second sub-pixel 310 in the second display device layer 300 is also surrounded by a metal fence structure 660 .

[0095] Furthermore, the top height of the metal fence structure 660 is the same as the top height of the semiconductor electrode conductive structure 500 in the same layer. To facilitate the simultaneous preparation of the semiconductor electrode conductive structure 500 and the metal fence structure 660, the metal fence structure 660 is designed to be flush with the semiconductor electrode conductive structure 500 in the same layer.

[0096] Further, such as Figure 8 As shown, the inner wall of the metal fence structure 660 is provided with a high-reflective layer 610. High-reflective layer 610 has a certain reflective property. The high-reflective mirror structure formed on the inner wall of the metal fence structure 660 can solve the problems of low reflectivity and light absorption of the metal fence structure 660, improve the reflection of light from the compound epitaxial sidewall, thereby increasing light extraction and improving the brightness of the device.

[0097] Furthermore, the angle of the metal fence structure 600 is between 45 degrees and 135 degrees. That is, the angle of the metal fence structure 600 can be designed to be 90°±45°.

[0098] Furthermore, the sub-pixels in each display device layer are electrically connected via the transparent conductive layer 670 on a surface on a side away from the driving wafer 100 .

[0099] For example, Figure 2 、 Figure 3 As shown, after the surface of the second ohmic contact layer of the sub-pixel in each display device layer is exposed, a continuous transparent conductive layer 670 may be provided thereon. Transparent conductive film deposition may be performed by sputtering, evaporation, or other methods to prepare transparent conductive layer 670. Transparent conductive layer 670 may be a combination of one or more of an ITO (Indium Tin Oxide) film, an AZO (Antimony Doped Zinc Oxide) film, an ATO (Antimony Doped Tin Oxide) film, and an FTO (Fluorine Doped Tin Oxide) film, or a metal-doped ITO single layer or stack formed by thinly coating an ITO surface with Al, Au, or Ag and then annealing it, thereby enhancing the current transmission capability of transparent conductive layer 670.

[0100] Furthermore, in the top display device layer, the insulating layer is entirely filled in the top display device layer. That is, during the preparation of the top display device layer, after the pixelation of the sub-pixels in the top display device layer is completed, the insulating layer can be prepared by an overall filling method, and then flattened to the surface of the sub-pixels in the top display device layer; then, openings are opened to expose the surface of the second ohmic contact layer of the sub-pixels in each display device layer; and finally, a transparent conductive layer is formed to electrically connect the layers.

[0101] For example, Figure 9 As shown, the micro display device includes three display device layers, the top display device layer is the third display device layer 400, the insulating medium in the third display device layer 400 is entirely filled in this layer, and the sub-pixels in each display device layer are electrically connected through the transparent conductive layer 670; Figure 10 As shown, the micro display device includes two display device layers. The top display device layer is the second display device layer 300. The insulating medium in the second display device layer 300 is entirely filled in this layer. The sub-pixels in each display device layer are electrically connected through the transparent conductive layer 670.

[0102] Further, such as Figure 2 、 Figure 3 As shown, a metal reinforcement structure 680 is prepared on the transparent conductive layer 670 to expand the current and improve the luminous angle and brightness. The metal reinforcement structure 680 can be realized by patterned evaporation, sputtering, or etching after coating.

[0103] Exemplary, with reference to Figure 11The relevant dimensions of the micro display device can be set as follows: the thickness B1 / B2 / B3 of the bonding metal layer 630 is designed to be in the range of 10nm to 1.5um, and the thickness of the bonding metal layer 630 tends to be thin and without voids or gaps. The optimal design thickness is different for different bonding metal methods; the thickness of the first ohmic contact layer 640 is in the range of 5nm to 300nm; the thickness A1 / A2 / A3 of the sub-pixel related layers in each display device layer is designed to be in the range of 0.2um to 5um, and different chemical The optimal design of compound patterning with different thicknesses is as follows: for compound patterning of ≤5um, A1 / A2 / A3 is optimally 0.2-2um; the design range of the angle α1 / α2 / α3 of the sub-pixel in each display device layer is 90°±45°, and the preferred range is 90°±20°, which has the best performance of light extraction and spacing design; the design range of the through-hole angle β1 / β2 of the semiconductor electrode conductive structure 500 in the first display device layer 200 and the second display device layer 300 is 90°±4 5°, the preferred range is <90°; M0 is the size of the electrode contact 110, M1 is the size of the semiconductor electrode conductive structure 500 of the first layer, M2 is the size of the semiconductor electrode conductive structure 500 of the second layer, and M3 is the size of the bonding metal layer 630 of the third layer, and the relationship between the sizes is M3 ≥ M2 ≥ M1 ≥ M0; the thickness of the semiconductor electrode conductive structure 500 is set to 10nm ~ 1500nm, where D1 is the thickness of the semiconductor electrode conductive structure 500 of the first layer, and D2 is the thickness of the second layer The thickness of the semiconductor electrode conductive structure 500 is designed to be 10 nm to 500 nm; the thickness T1 of the transparent conductive layer 670 is in the range of 10 nm to 500 nm. In addition, the current expansion and transmittance are also considered. The thicker the layer, the better the current expansion, but the lower the transmittance. The thickness n of the metal reinforcement structure 680 is designed to be in the range of 100 nm to 5000 nm. The opening size of the metal reinforcement structure 680 in the sub-pixel is ≥ the size of the ohmic contact layer in the sub-pixel. For example, the opening size of the metal reinforcement structure 680 corresponding to the first sub-pixel 210 is: N1 ≥ N2.

[0104] In summary, an embodiment of the present application provides a stacked multi-color microdisplay device, which includes multiple display device layers, wherein at least one display device layer is provided with a semiconductor electrode conduction structure, and the semiconductor electrode conduction structure includes: a first conduction structure arranged in the horizontal direction and a second conduction structure arranged in the vertical direction; the bottom of the second conduction structure is connected to the outer edge of the first conduction structure in the current display device layer to surround the first conduction structure, and the top is connected to the sub-pixel in the upper display device layer, or connected to the bottom of the first conduction structure in the upper display device layer; the bottom of the first conduction structure is connected to the electrode contact in the driving wafer, or connected to the top of the second conduction structure in the lower display device layer, so that the anode conduction is achieved through this fence-style semiconductor electrode conduction structure, without the need for a process of first through-hole and then metal filling, reducing the process difficulty of graphical overlay alignment.

[0105] Next, the preparation method of the micro display device corresponding to the structure described in the above embodiment is described. Figure 12 As shown, the method for preparing a micro display device may include the following steps:

[0106] Step S1: Prepare the driving wafer.

[0107] Step S2: bonding and integrating multiple display device layers on the driver wafer, and preparing a semiconductor electrode conduction structure in at least one display device layer.

[0108] Among them, any display device layer includes sub-pixels; the semiconductor electrode conduction structure includes: a first conduction structure arranged in the horizontal direction and a second conduction structure arranged in the vertical direction; the bottom of the second conduction structure is connected to the outer edge of the first conduction structure in the current display device layer to surround the first conduction structure, and the top is connected to the sub-pixels in the upper display device layer, or connected to the bottom of the first conduction structure in the upper display device layer; the bottom of the first conduction structure is connected to the electrode contact in the driving wafer, or connected to the top of the second conduction structure in the lower display device layer.

[0109] Specifically, step S2 may include:

[0110] S21: For non-top display device layers in the multi-layer display device layer, the color compound is bonded and integrated onto a driving wafer or a previous display device layer; the color compound is pixelated to form sub-pixels in the current display device layer; a semiconductor electrode conduction structure is prepared in the current display device layer, and the current display device layer is filled with an insulating material to form an insulating layer.

[0111] S22: For the top display device layer in the multi-layer display device layer, the color compound is bonded and integrated onto the previous display device layer; the color compound is pixelated to form sub-pixels in the current display device layer, and the sub-pixels are electrically connected to the electrode contacts in the driving wafer through the semiconductor electrode conduction structure in the non-top display device layer.

[0112] For example, Figure 2 As shown, if there are two display device layers, the non-top display device layer is the first display device layer 200, and the top display device layer is the second display device layer 300. The first display device layer 200 includes a first sub-pixel 210 and is filled with a first insulating layer 220, and the second display device layer 300 includes a second sub-pixel 310 and has a second insulating layer 320 disposed on the pixel sidewall. The first sub-pixel 210 is directly conductively connected to the electrode contact 110 in the driver wafer 100. Therefore, it is necessary to prepare a semiconductor electrode conductive structure 500 in the first display device layer 200 for anode conductively connecting the second sub-pixel 310 in the second display device layer 300.

[0113] For example, Figure 3 As shown, if there are three display device layers, the non-top display device layers are the first display device layer 200 and the second display device layer 300, and the top display device layer is the third display device layer 400. The first display device layer 200 includes a first sub-pixel 210 and is filled with a first insulating layer 220, the second display device layer 300 includes a second sub-pixel 310 and is filled with a second insulating layer 320, and the third display device layer 400 includes a third sub-pixel 410 and has a third insulating layer 420 disposed on the pixel sidewall. The first sub-pixel 210 is directly conductively connected to the electrode contact 110 in the driver wafer 100. Therefore, it is necessary to prepare a semiconductor electrode conductive structure 500 in the first display device layer 200 and the second display device layer 300 for anode conductively connecting the second sub-pixel 310 in the second display device layer 300 and the third sub-pixel 410 in the third display device layer 400.

[0114] For example, taking the preparation process of the first display device layer 200 as an example, the preparation process of the non-top display device layer includes the following steps 1 to 5, and the processes of the first to third steps can be as follows: Figure 13 As shown:

[0115] Step 1: Select a first layer of color compound 710 and prepare a second ohmic contact layer 690 .

[0116] Specifically, a contact material is prepared on the P contact surface or N contact surface of the first layer of color compound 710 to form a first ohmic contact layer 640. The contact material can be a transparent conductive film such as ITO, IZO, IGZO, AZO, or a metal alloy film such as AuBe, AnZn, with a thickness ranging from 1nm to 300nm.

[0117] Step 2: Bonding the first layer of color compound 710 to the wafer for integration.

[0118] Specifically, bonding structures are prepared on the first layer of color compound 710 and the driver wafer 100 , respectively, and the first layer of color compound 710 and the driver wafer 100 are bonded and integrated by wafer-level bonding to form a bonding metal layer 630 .

[0119] The bonding structure can be a conductive material, and the main bonding material can be one or more of a Ni, Sn combination, an Au, Sn combination, a Cu, Sn combination, an Au, In combination, an Au, Au combination, an Al, Al combination, a Cu, Cu combination, an ITO, ITO combination, etc. The bonding material and the wafer can include an adhesion layer (such as Cr, Ti, Ni, etc.) and a blocking depletion layer (such as Ni, Pt, Cu, etc.). The bonding structure on the compound and the driver wafer can be symmetrical or asymmetrical.

[0120] In one embodiment, symmetrical metal bonding is used, that is, the bonding structure on the compound and the driver wafer is the same, and the bonding structure is Cr (10nm, adhesion layer) / Pt (50nm, blocking depletion layer) / Au (100nm) / Sn (150nm) / Au (50nm). After high-temperature hot pressing bonding, the compound and the driver wafer are bonded and integrated.

[0121] Step 3: Pixelation preparation.

[0122] Specifically, the substrate and related structures of the first layer of color compound 710 that has been bonded and integrated are removed to expose the second ohmic contact layer 690. After exposing the second ohmic contact layer 690, the first layer of color compound is patterned to produce pixels through semiconductor photolithography and etching processes. The first ohmic contact layer 640 serves as the etching stop layer. The etched first sub-pixels 210 correspond to the electrode contacts 110 in the driver wafer 100, which can be a one-to-one or one-to-many correspondence. Subsequently, patterning and etching are performed to isolate the first ohmic contact layer 640, the bonding metal layer 630, etc., to achieve sub-pixel independence. The sidewalls of the sub-pixels can then be cleaned and a passivation film layer can be applied to repair the damaged sidewall layers.

[0123] Step 4: Preparation of semiconductor electrode conductive structure 500.

[0124] Specifically, in order to achieve anode conduction, it is necessary to prepare a semiconductor electrode conduction structure 500 in the first display device layer 200 for the sub-pixels in the upper display device layer.

[0125] It is understandable that the semiconductor electrode conductive structure can be prepared by reverse sputtering during the patterning of the bonding metal layer and the first ohmic contact layer in the display device layer, thereby facilitating the preparation of the semiconductor electrode conductive structure.

[0126] Step 5: Flatten after filling with insulating material.

[0127] Specifically, the first display device layer 200 is filled with an insulating dielectric to form a first insulating layer. The insulating dielectric includes silicon oxide, silicon nitride, SiC, SiCN, PSG, BPSG, polyimide, etc. Subsequently, planarization is performed. Planarization can be performed by CMP, etching, or a combination of the two, and the planarization stops at the top surface of the first sub-pixel 210.

[0128] In one embodiment, a SiO2 dielectric layer is used for filling and a CMP surface planarization process is performed to expose the conductive electrode contact area and the color compound epitaxial surface.

[0129] It is understood that if the first display device layer prepared in step 5 is defined as a new driver wafer, steps 1 to 3 are repeated to complete the stacking process until a double-layer pixelation process is completed. If the second display device layer prepared in step 5 is defined as a new driver wafer, steps 1 to 3 are repeated to complete the stacking process until a triple-layer pixelation process is completed.

[0130] Furthermore, with respect to the fourth and fifth steps above, the preparation of the semiconductor electrode conductive structure in the non-top display device layer and the subsequent preparation process may specifically include the following solutions:

[0131] A first possible implementation method is to prepare a semiconductor electrode conduction structure in a non-top display device layer, and fill the current display device layer with an insulating material to form an insulating layer, including: patterning the bonding metal layer and the first ohmic contact layer in the current display device layer by ion beam etching, and simultaneously forming the semiconductor electrode conduction structure; and filling the current display device layer with an insulating medium to form an insulating layer.

[0132] In this implementation, if Figure 14 As shown, for the device prepared in the third step, an etching process is used after pixelation to isolate the first ohmic contact layer 640, the bonding metal layer 630, etc., and a metal electrode structure that is conductively interconnected with the electrode contact 110 in the driving wafer 100 is also prepared as a semiconductor electrode conductive structure 500, and then an insulating material is filled to form an insulating layer.

[0133] The second possible implementation method is to prepare the color compound into pixels to form sub-pixels for the non-top display device layer, and also includes the following steps: forming an epitaxial structure in the non-top display device layer in the area corresponding to the semiconductor electrode conduction structure.

[0134] In this implementation, during pixelation, the epitaxial structure is retained in the region corresponding to the semiconductor electrode conductive structure, and any combination of retention methods can be used. A semiconductor electrode conductive structure in contact with the electrode contact is then prepared, and insulation filling is performed to complete the insulation layer preparation.

[0135] It is understandable that the epitaxial structure may be retained in some areas corresponding to the semiconductor electrode conduction structure, or the epitaxial structure may be retained in all areas corresponding to the semiconductor electrode conduction structure, and this application does not impose any restrictions on this.

[0136] Furthermore, while retaining the epitaxial structure, a semiconductor electrode conduction structure is prepared in the current display device layer, and the current display device layer is filled with insulating material to form an insulating layer, including: patterning the bonding metal layer and the first ohmic contact layer in the non-top display device layer by ion beam etching, and simultaneously forming a semiconductor electrode conduction structure around the outer periphery of the epitaxial structure, and the inner side wall of the semiconductor electrode conduction structure is connected to the side wall of the epitaxial structure; filling the non-top display device layer with insulating medium to form an insulating layer.

[0137] Since the semiconductor electrode conduction structure is a ring-shaped pattern, if the thickness is thin and the elastic modulus is small, it is easy to collapse during the process. The problem of collapse can be solved by retaining the compound epitaxy during pixel patterning and attaching the semiconductor electrode conduction structure to the side wall surface of the compound epitaxial layer instead of leaving it suspended.

[0138] In one embodiment, when the height of the semiconductor electrode conductive structure is consistent with that of the epitaxial structure and the insulating layer, the process from pixelation to insulating layer filling in the display device layer is as follows: Figure 15 、 Figure 16 、 Figure 17 As shown. Among them, Figure 15 Corresponding to retaining the epitaxial structure 650 in the areas corresponding to all semiconductor electrode conductive structures 500; Figure 16 、 Figure 17 The epitaxial structure 650 is retained in a region corresponding to a portion of the semiconductor electrode conductive structure 500 .

[0139] In one embodiment, when the prepared semiconductor electrode conductive structure is lower than the height of the epitaxial structure and the insulating layer, a planarization process is also used after the insulating layer is filled. The process from pixelization in the display device layer to filling and planarization of the insulating layer is as follows: Figure 18 、 Figure 19 、 Figure 20 As shown. Among them, Figure 18 Corresponding to retaining the epitaxial structure 650 in the areas corresponding to all semiconductor electrode conductive structures 500; Figure 19 、 Figure 20 The epitaxial structure 650 is retained in a region corresponding to a portion of the semiconductor electrode conductive structure 500 .

[0140] Furthermore, while retaining the epitaxial structure, a semiconductor electrode conduction structure is prepared in the current display device layer, and the current display device layer is filled with an insulating material to form an insulating layer, including: filling the non-top display device layer with an insulating medium; patterning the bonding metal layer and the first ohmic contact layer in the non-top display device layer through ion beam etching, and simultaneously forming a semiconductor electrode conduction structure around the outer periphery of the epitaxial structure, and retaining an insulating medium between the semiconductor electrode conduction structure and the epitaxial structure; and filling the non-top display device layer with an insulating medium again to form an insulating layer.

[0141] In the process of simultaneously preparing the semiconductor electrode conduction structure and the metal fence structure, metal atoms are easily left behind. Metal atoms can easily penetrate the insulating layer to the sidewalls of the sub-pixel, causing N and P leakage problems. In severe cases, it is easy to cause short circuit problems, resulting in a low yield of device preparation. To solve this problem, after retaining the epitaxial structure and completing pixelation, the insulating material is filled, and then the first ohmic contact layer, bonding metal layer, etc. are isolated at the same time. At the same time, the semiconductor electrode conduction structure and the metal fence structure that are conductive to the electrode contacts are also prepared. Then, the insulating material is filled to form the final insulating layer, and then flattened to expose the semiconductor electrode conduction structure.

[0142] In one embodiment, when the height of the semiconductor electrode conductive structure 500 is consistent with that of the epitaxial structure 650 and the insulating layer, the process from pixelation to insulating layer filling in the display device layer is as follows: Figure 21 shown.

[0143] In one embodiment, when the prepared semiconductor electrode conductive structure 500 is lower than the height of the epitaxial structure 650 and the insulating layer, a planarization process is also used after the insulating layer is filled. The process from pixelization in the display device layer to filling and planarization of the insulating layer is as follows: Figure 22 shown.

[0144] A third possible implementation method is to prepare a semiconductor electrode conduction structure in a non-top display device layer, and fill the current display device layer with an insulating material to form an insulating layer, including: filling the non-top display device layer with an insulating dielectric; patterning the bonding metal layer and the first ohmic contact layer in the non-top display device layer by ion beam etching, and simultaneously forming a semiconductor electrode conduction structure, and retaining an insulating dielectric inside the semiconductor electrode conduction structure; and filling the non-top display device layer with an insulating dielectric again to form an insulating layer.

[0145] In this implementation, without retaining the epitaxial structure, after pixelation is completed, an insulating material can be filled, and then the first ohmic contact layer, bonding metal layer, etc. can be isolated at the same time. At the same time, a semiconductor electrode conductive structure and a metal fence structure that are conductive to the electrode contacts are also prepared. Then, the insulating material is filled to form the final insulating layer, and then flattened to expose the semiconductor electrode conductive structure. Under this preparation scheme, since the semiconductor electrode conductive structure and the metal fence structure are prepared simultaneously, an insulating medium is also retained between the metal fence structure and the sub-pixel to prevent device short circuits.

[0146] In one embodiment, when the height of the semiconductor electrode conductive structure 500 is consistent with that of the epitaxial structure 650 and the insulating layer, the process from pixelation to insulating layer filling in the display device layer is as follows: Figure 23 shown.

[0147] In one embodiment, when the prepared semiconductor electrode conductive structure 500 is lower than the height of the epitaxial structure 650 and the insulating layer, a planarization process is also used after the insulating layer is filled. The process from pixelization in the display device layer to filling and planarization of the insulating layer is as follows: Figure 24 shown.

[0148] In one possible implementation, while preparing the semiconductor electrode conductive structure in the current display device layer, the following step is also included: preparing a metal fence structure surrounding the sub-pixels in the current display device layer. The metal fence structure can be prepared simultaneously with the semiconductor electrode conductive structure. The specific preparation method can be referred to the preparation method of the semiconductor electrode conductive structure described above and will not be repeated here.

[0149] Specifically, such as Figure 3As shown, a metal fence structure 660 is arranged around the first sub-pixel 210 and the second sub-pixel 310. The metal fence structure 660 is similar in style to the second conductive structure 520. The metal fence structure 660 is connected to the outer edge of the bonding metal layer 630 and the first ohmic contact layer 640 at the bottom of the sub-pixel. The preparation of the metal fence structure 660 can be completed simultaneously with the preparation of the semiconductor electrode conductive structure 500. The metal fence structure 660 can block light leakage from the sidewalls of the sub-pixels, thereby suppressing or even eliminating light crosstalk between adjacent sub-pixels, thereby improving the display effect of the micro-display device.

[0150] In one possible implementation, the color compound is bonded and integrated onto a driver wafer or a previous display device layer, including: preparing an ODR insulating layer on the surface of the color compound after the first ohmic contact layer is prepared; preparing a bonding metal layer on the surface of the ODR insulating layer of the color compound and the surface of the driver wafer or the previous display device layer; and bonding and integrating the color compound onto the driver wafer or the previous display device layer through the bonding metal layer.

[0151] In this implementation, an insulating dielectric layer is prepared on the surface of the color compound after the first step of ohmic contact preparation as an ODR insulating layer, and then a bonding metal layer prepared on the surface is used to bond and integrate with the driver wafer or the previous display device layer to form an ODR structure in the area below the first ohmic contact layer of the color compound, thereby reducing the absorption problem of the sub-pixel after light is emitted from this side, improving the reflection of this side, and thus improving the brightness of the device. For example, Figure 4 As shown, under the first ohmic contact layer 640 , an ODR structure is formed by the ODR insulating layer 620 and the bonding metal layer 630 .

[0152] In a possible implementation, before preparing the semiconductor electrode conduction structure in the current display device layer, a high reflective layer is also prepared around the sub-pixel.

[0153] The high reflective layer can be prepared by the following steps: using a photolithographic patterning method to plate a reflective material around the sub-pixels in the current display device layer to form a high reflective layer.

[0154] Specifically, such as Figure 8 As shown, after the pixel preparation is completed, after photolithography and patterning, a layer of reflective material is coated, the material of which can be a conductive material with high reflectivity or other insulating high-reflectivity material; then an etching process method is used to isolate the first ohmic contact layer 640, the bonding metal layer 630, etc., and at the same time, a semiconductor electrode conduction structure 500 that is conductively interconnected with the electrode contact 110 in the driving wafer 100 is also prepared.

[0155] The high reflective layer can also be prepared by the following steps: preparing a sidewall insulating film layer for the sub-pixels in the current display device layer; and plating a reflective material on the sidewall of the sidewall insulating film layer to form a high reflective layer.

[0156] Specifically, after completing the third step of pixelation, an insulating layer is retained on the epitaxial surface of the sub-pixel. An insulating film layer is then formed through plasma deposition, sputtering, atomic layer deposition, or other methods. The insulating layer thickness ranges from 1nm to 1500nm, and the insulating layer material includes a single film layer of silicon oxide, silicon nitride, aluminum oxide, boron nitride, or a stack of two or more materials. Etching methods such as RIE (Reactive Ion Etching) / ICP (Inductive Coupled Plasma) / IBE (Ion Beam Etching) are then used to retain the insulating film layer on the sidewalls. A layer of a reflective material with high reflectivity is then deposited to form a high-reflectivity layer. A semiconductor electrode conductive structure is then formed using etching methods, and then the insulating layer is filled. Furthermore, multiple sets of highly reflective layers and sidewall insulating film layers can be included between the semiconductor electrode conductive structure and the sidewalls of the sub-pixel, thereby further improving the reflection of light emitted from the sidewalls and enhancing the device brightness.

[0157] In one embodiment, when the height of the semiconductor electrode conductive structure 500 is consistent with that of the epitaxial structure 650 and the insulating layer, the process from pixelation to insulating layer filling in the display device layer is as follows: Figure 25 shown.

[0158] In one embodiment, when the prepared semiconductor electrode conductive structure 500 is lower than the height of the epitaxial structure 650 and the insulating layer, a planarization process is also used after the insulating layer is filled. The process from pixelization in the display device layer to filling and planarization of the insulating layer is as follows: Figure 23 shown.

[0159] Furthermore, after completing the preparation of sub-pixels in each display device layer, the following steps can be further performed: preparing a transparent conductive layer, the second ohmic contact layer of the sub-pixels in any display device layer is connected to a common cathode through the transparent conductive layer, and the transparent conductive layer is covered on the second ohmic contact layer of the sub-pixels in each display device layer.

[0160] Specifically, such as Figure 2 、 Figure 3 As shown, after the surface of the second ohmic contact layer of the sub-pixel in each display device layer is exposed, electrical connection is performed, and a transparent conductive film is deposited by sputtering, evaporation, etc. to form a transparent conductive layer 670.

[0161] Furthermore, after the transparent conductive layer is prepared, the following step may be further performed: a metal reinforcement structure is provided on the transparent conductive layer.

[0162] Specifically, such as Figure 2 、 Figure 3 As shown, a metal reinforcement structure 680 is prepared on the transparent conductive layer 670. The metal reinforcement structure 680 can be realized by patterned evaporation or sputtering, or by etching after coating.

[0163] In one embodiment, a metal enhancement structure is realized by patterned coating of Ni, Al, Ti, and Au stacked layers, and this structure can achieve better current expansion. At the same time, the cavity formed by this structure can constrain the light distribution and improve the brightness.

[0164] In summary, the preparation method of the micro display device provided in the embodiment of the present application integrates multiple display device layers on a driving wafer, wherein at least one display device layer is provided with a semiconductor electrode conduction structure, and the semiconductor electrode conduction structure includes: a first conduction structure arranged in the horizontal direction and a second conduction structure arranged in the vertical direction; the bottom of the second conduction structure is connected to the outer edge of the first conduction structure in the current display device layer to surround the first conduction structure, and the top is connected to the sub-pixel in the upper display device layer, or connected to the bottom of the first conduction structure in the upper display device layer; the bottom of the first conduction structure is connected to the electrode contact in the driving wafer, or connected to the top of the second conduction structure in the lower display device layer, thereby realizing anode conduction through this fence-style semiconductor electrode conduction structure, without the need for a process of first through-hole and then metal filling, reducing the process difficulty of graphical overlay alignment.

[0165] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the scope of protection of this application and will not be described in detail here.

[0166] It should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A stacked multi-color micro-display device, characterized in that: The micro display device includes a driving wafer and a multi-layer display device layer arranged on the driving wafer, wherein any of the display device layers includes sub-pixels; A semiconductor electrode conductive structure is provided in at least one of the display device layers, and the semiconductor electrode conductive structure includes: a first conductive structure provided in a horizontal direction and a second conductive structure provided in a vertical direction; The bottom of the second conductive structure is connected to the outer edge of the first conductive structure in the current display device layer to surround the first conductive structure, and the top is connected to the sub-pixel in the upper display device layer, or connected to the bottom of the first conductive structure in the upper display device layer; The bottom of the first conductive structure is connected to the electrode contact in the driving wafer, or is connected to the top of the second conductive structure in the lower display device layer.

2. The micro display device according to claim 1, characterized in that The horizontal size of the semiconductor electrode conductive structure in the lower display device layer is smaller than or equal to the horizontal size of the semiconductor electrode conductive structure in the upper display device layer.

3. The micro display device according to claim 2, characterized in that The horizontal size of the semiconductor electrode conductive structure in the first display device layer directly connected to the driver wafer is greater than or equal to the horizontal size of the electrode contact in the driver wafer.

4. The micro display device according to claim 1, wherein: An epitaxial structure is provided inside the semiconductor electrode conductive structure, the bottom of the epitaxial structure is connected to the upper surface of the first conductive structure in the current display device layer, and the top is connected to the lower surface of the first conductive structure in the previous display device layer.

5. The micro display device according to claim 4, characterized in that The size of the epitaxial structure is smaller than or equal to the size of the sub-pixel in the same display device layer.

6. The micro display device according to claim 4, characterized in that The sidewall of the epitaxial structure is connected to the inner sidewall of the semiconductor electrode conductive structure; or, An insulating medium is provided between the sidewall of the epitaxial structure and the inner sidewall of the semiconductor electrode conductive structure.

7. The micro display device according to claim 1, characterized in that The first conductive structure is consistent with the structure of the bottom metal layer of the sub-pixel; The bottom metal layer includes: a bonding metal layer and a first ohmic contact layer vertically stacked in a direction away from the driving wafer.

8. The micro display device according to claim 7, characterized in that An ODR insulating layer is further provided between the bonding metal layer and the first ohmic contact layer, and the ODR insulating layer and the bonding metal layer form an ODR structure.

9. The micro display device according to claim 7, characterized in that: The thickness of the bonding metal layer is between 10 nm and 1.5 um.

10. The micro display device according to claim 7, characterized in that: The thickness of the first ohmic contact layer is between 5 nm and 300 nm.

11. The micro display device according to claim 1, wherein: The top height of the second conductive structure is flush with the top height of the sub-pixels in the same display device layer.

12. The micro display device according to claim 1, wherein: The outer periphery of the sub-pixel is surrounded by a metal fence structure that is structurally consistent with the second conductive structure, and the bottom of the metal fence structure is connected to the bonding metal layer at the bottom of the sub-pixel and the outer edge of the first ohmic contact layer to surround the sub-pixel.

13. The micro display device according to claim 12, characterized in that: The top height of the metal fence structure is the same as the top height of the semiconductor electrode conductive structure in the same layer.

14. The micro display device according to claim 12, characterized in that: The inner wall of the metal fence structure is provided with a high reflective layer.

15. The micro display device according to claim 1, characterized in that The thickness of the second conductive structure is between 10 nm and 1500 nm.

16. The micro display device according to claim 12, characterized in that: The angle of the metal fence structure is between 45 degrees and 135 degrees.

17. The micro display device according to claim 1, characterized in that The sub-pixels in each display device layer are electrically connected via a transparent conductive layer on a surface on a side away from the driving wafer.

18. The micro display device according to claim 17, characterized in that In the top display device layer, the insulating layer is entirely filled in the top display device layer.

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