Packaging substrate and packaging chip

Abstract

The embodiment of the utility model discloses a packaging substrate and a packaging chip. The packaging substrate comprises a core plate, at least one opening structure formed on the core plate, first electrode layers, second electrode layers and dielectric material layers, wherein the first electrode layers and the second electrode layers cover part of side walls of the opening structures, and the dielectric material layers are formed between the first electrode layers and the second electrode layers. Wherein the opening structure comprises a groove partially penetrating through the core plate and / or a through hole penetrating through the core plate, the first electrode layer and the second electrode layer are electrically isolated from each other and are opposite in position, the first electrode layer and the second electrode layer are used as polar plates of a capacitor, the dielectric material layer is used as a dielectric layer of the capacitor, and the packaging substrate can reduce the packaging size and improve the packaging efficiency. Meanwhile, loop inductance of the power distribution network is reduced, and link parasitism is improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging, and more specifically, to a packaging substrate and a packaging chip. Background Art

[0002] With the development of ultra-large-scale integrated circuit (VLSI) technology, the operating voltage of chips is becoming lower and lower, while the operating speed is becoming faster and faster, and the power consumption is increasing. This places higher demands on the stability of the power supply system. To reduce power supply noise and improve power supply stability, existing technologies usually place small-capacitance decoupling capacitors on the package substrate in a surface-mount manner, close to the chip power pins, and large-capacitance filter capacitors at the power input end of the package substrate or farther away from the chip. However, when capacitors are directly mounted on the package substrate, the size of the package needs to be increased accordingly to accommodate these capacitors. At the same time, the leads used to connect the capacitors to the package substrate form a small inductor in parallel with the capacitor. The resulting loop inductance can adversely affect the performance of the power distribution network. Utility Model Content

[0003] In view of this, embodiments of the present invention provide a packaging substrate and a packaging chip to reduce the package size, while reducing the loop inductance of the power distribution network and improving link parasitics.

[0004] In a first aspect, an embodiment of the present invention provides a packaging substrate, the packaging substrate comprising:

[0005] core board;

[0006] at least one opening structure formed on the core plate, the opening structure comprising a groove partially penetrating the core plate and / or a through hole penetrating the core plate;

[0007] a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer cover a portion of a sidewall of each of the opening structures, the first electrode layer and the second electrode layer are electrically isolated from each other and positioned opposite to each other, and the first electrode layer and the second electrode layer are used to serve as plates of a capacitor;

[0008] A dielectric material layer is formed between each of the first electrode layers and each of the second electrode layers, and the dielectric material layer is used as a dielectric layer of the capacitor.

[0009] In a second aspect, an embodiment of the present invention provides a packaged chip, the packaged chip comprising:

[0010] chip;

[0011] As described in the first aspect, the packaging substrate is used to carry the chip and realize electrical connection between the chip and the circuit board.

[0012] The packaging substrate in an embodiment of the present invention includes a core board, at least one opening structure formed in the core board, a first electrode layer and a second electrode layer covering a portion of the sidewalls of each opening structure, and a dielectric material layer formed between each first electrode layer and each second electrode layer. The opening structure includes a groove that partially penetrates the core board and / or a through hole that penetrates the core board. The first electrode layer and the second electrode layer are electrically isolated from each other and positioned opposite each other. The first electrode layer and the second electrode layer are used to serve as the plates of a capacitor, and the dielectric material layer is used to serve as the dielectric layer of the capacitor. The packaging substrate can reduce the package size while reducing the loop inductance of the power distribution network and improving link parasitics. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0014] Figure 1 A three-dimensional diagram of a packaging system according to an embodiment of the present invention;

[0015] Figure 2 and Figure 3 A cross-sectional view of a packaging system according to an embodiment of the present invention;

[0016] Figure 4 is a cross-sectional view of another packaging system according to an embodiment of the present invention;

[0017] Figure 5 and Figure 6 A cross-sectional view of another packaging system according to an embodiment of the present invention;

[0018] Figure 7 and Figure 8 A cross-sectional view of another packaging system according to an embodiment of the present invention;

[0019] Figure 9 This is a flow chart of a method for forming a capacitor in a packaging substrate according to an embodiment of the present invention;

[0020] Figure 10-20 A schematic diagram of the process of forming a package substrate according to an embodiment of the present invention;

[0021] Figure 21 This is a schematic diagram of a package substrate after molding according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present application is described below based on the following embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. To avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0023] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0024] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0025] For ease of explanation, spatially relative terms such as "in," "out," "under," "below," "lower," "above," and "upper" are used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. It will be understood that spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being "under" or "beneath" another element or feature would then be positioned "above" the other element or feature. Thus, the example term "under" can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] Unless the context clearly requires otherwise, words like “include”, “comprising” and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning “including but not limited to”.

[0027] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] It should be understood that in each embodiment of the present invention, "side wall" refers to the surface other than the top and bottom surfaces, such as "covering the side wall of the opening structure" means covering the front, back, left and right sides of the opening structure.

[0029] Figure 1 This is a three-dimensional diagram of the packaging system of the embodiment of the utility model. Figure 1 As shown, the packaging system of the embodiment of the present invention includes a packaging chip and a circuit board 13.

[0030] Among them, the packaged chip includes a chip 11 and a packaging substrate 12. The chip 11 is an integrated circuit that has not undergone any packaging processing, that is, a bare chip (Die). The chip 11 can be obtained by making a corresponding circuit on a silicon wafer (Wafer) using a semiconductor manufacturing process. It should be understood that the packaging system of the embodiment of the present utility model does not impose specific restrictions on the type of packaged chip. The packaging substrate 12 is located between the chip 11 and the circuit board 13. The packaging substrate 12 is fixed on the circuit board 13 and is used to carry the chip 11 to provide the necessary physical support, physical protection, electrical connection and thermal management (that is, to help the chip 11 dissipate heat) for the chip 11.

[0031] The circuit board 13 ( Figure 1 The circuit board shown is only a portion of the circuit board used to fix the chip 11. It is a carrier for mounting and connecting different electronic components (such as the packaged chips mentioned above and electronic components such as resistors, diodes, transistors, inductors, capacitors, etc.). The circuit board 13 can provide a fixed platform for each electronic component and realize electrical connection between the components through conductive paths (commonly called traces or wiring) printed on the board. It should be understood that the circuit board 13 can be obtained by forming corresponding conductive paths on a substrate board made of an insulating material (such as polyethylene, polystyrene, polypropylene, aluminum oxide, barium titanate or aluminum silicate, etc.) (the conductive paths can be formed by depositing a conductive material film on the substrate board and then patterning the conductive material film).

[0032] Optionally, in this embodiment, the chip 11 and the package substrate 12 can be connected by a flip chip packaging method. The package substrate 12 and the circuit board 13 can be connected by a ball grid array (BGA) packaging method. The flip chip packaging method refers to turning the chip over so that the chip pads are opposite to the pads of the package substrate, and transplanting solder balls (such as Figure 2 The ball grid array packaging method refers to transplanting solder balls (such as solder balls 14) on each pad of the packaging substrate. Figure 2) to form a solder ball array, and then use the solder ball array to connect the package substrate and the circuit board 13 together. It should be understood that in actual application, the chip 11 and the package substrate 12 can also be connected by methods such as wire bonding (Wire Bonding) or tape automated bonding (TAB). The package substrate 12 and the circuit board 13 can also be connected by methods such as pin grid array packaging (Pin Grid Array, PGA) or quad flat package (Quad F l at Package, QFP). This application does not specifically limit the connection methods adopted between the chip 11 and the package substrate 12 and between the package substrate 12 and the circuit board 13.

[0033] It should be understood that after the chip 11 is connected to the package substrate 12, in order to fix and protect the chip, the relevant process usually uses sealing technology to seal the chip 11 in a package shell made of plastic, glass, metal or ceramic, thereby isolating the chip 11 from the external environment. In this embodiment, in order to conveniently illustrate the relationship between the chip 11 and the package substrate 12, Figure 1 and Figure 2 The packaging system shown in omits the packaging shell.

[0034] Compared to the prior art in which capacitors are mounted on the top and bottom surfaces of the package substrate 12 respectively, in this embodiment, the capacitors are directly formed inside the package substrate 12 .

[0035] Figure 2 and Figure 3 This is a cross-sectional view of the packaging system of an embodiment of the present utility model. Figure 2 Yes Figure 1 Cross-sectional view of the packaging system along the dotted line AA'. Figure 3 Yes Figure 1 It should be understood that in order to facilitate the display of the formed capacitor structure, Figure 3 The cross-sectional view in FIG also omits the circuit layer (ie, circuit layer 125) covering the core board 121. Figure 2 and Figure 3 As shown, the package substrate 12 includes a core board 121 , at least one opening structure 122 , a first electrode layer 1221 , a second electrode layer 1222 and a dielectric material layer 1223 .

[0036] The core plate 121 is a physical support layer located in the middle of the package substrate 12, which can support the entire package structure. The core plate 121 can be formed by epoxy resin reinforced with glass fiber or other types of rigid materials.

[0037] Furthermore, each of the opening structures 122 can be formed on the core plate 121. In the present embodiment, each of the opening structures 122 is specifically a through hole that penetrates the core plate 121. The shape of each of the opening structures 122 is specifically a rectangular parallelepiped. However, in some embodiments, each of the opening structures 122 can also be a groove formed on the top or bottom surface of the core plate that partially penetrates the core plate. In addition, in order to maximize the facing area between the first electrode layer 1221 and the second electrode layer 1222 that subsequently cover the side walls of the opening structure 122 (that is, the area directly opposite between the two plates, the facing area is proportional to the capacitance of the capacitor) to obtain a capacitor structure with a higher capacitance, the shape of the opening structure 122 can also be made into other shapes, and this application does not impose specific restrictions on this.

[0038] Furthermore, the first electrode layer 1221 and the second electrode layer 1222 cover part of the sidewalls of each of the opening structures 122. The first electrode layer 1221 and the second electrode layer 1222 can be formed of a conductive material. The conductive material can be a conductive metal (such as copper, aluminum, zinc, tantalum or silver, etc.), or a conductive polymer (such as polyaniline or polythiophene, etc.). Furthermore, the first electrode layer 1221 and the second electrode layer 1222 in each opening structure 122 are electrically isolated from each other and positioned relative to each other. The dielectric material layer 1223 can be formed between the first electrode layer 1221 and the second electrode layer 1222 to isolate the first electrode layer 1221 and the second electrode layer 1222. Optionally, the dielectric material layer 1223 can be formed of an insulating material with a higher dielectric constant (such as polyethylene, polystyrene, polypropylene, aluminum oxide, barium titanate or aluminum silicate, etc.). Therefore, the first electrode layer 1221 and the second electrode layer 1222 are respectively used as two plates of the capacitor structure, and the dielectric material layer 1223 is used as the dielectric layer of the capacitor structure. The first electrode layer 1221, the second electrode layer 1222 and the dielectric material layer 1223 can constitute a complete capacitor structure.

[0039] Optionally, the packaging substrate 12 may further include a first electrical connection structure 123 and a second electrical connection structure 124. The first electrical connection structure 123 is formed on the top and bottom surfaces of the core board 121, respectively, covering each first electrode layer 1221. The second electrical connection structure 124 is formed on the top and bottom surfaces of the core board 121, respectively, covering each second electrode layer 1222. The first electrical connection structure 123 and the second electrical connection structure 124 can be used to respectively realize electrical connection between the first electrode layer 1221 and the second electrode layer 1222 and the circuit layer 125. It should be understood that the first electrical connection structure 123 and the second electrical connection structure 124 are electrically isolated from each other. Optionally, the first electrical connection structure 123 and the second electrical connection structure 124 can be formed of a conductive material.

[0040] Optionally, the packaging substrate 12 may further include at least one stacked circuit layer 125, at least one adhesive layer 126, and a plurality of conductive vias 127. The stacked circuit layers 125 may be formed on the top and bottom surfaces of the core board 121, respectively. The circuit layer 125 may be formed directly on the core board 121 and the corresponding adhesive layer 126 through a deposition and etching process, or may be formed by laminating a conductive material film (such as copper foil) printed with a circuit pattern formed through a series of process engineering on the core board 121 and the corresponding adhesive layer 126. The circuit layer 125 may be used to achieve electrical connection between the constituted capacitor structure, the chip 11, and the circuit board 13. The adhesive layer 126 is formed between each circuit layer 125. The adhesive layer 126 may be used to bond the circuit layers 125 together, and play a role in supporting the packaging structure and electrically isolating the circuit layers 125. Alternatively, the adhesive layer 126 may be a prepreg (a prepreg may be obtained by impregnating a resin (e.g., epoxy resin) into a reinforcing material (e.g., fiberglass cloth)). The plurality of conductive vias 127 are formed between the circuit layers 125. The plurality of conductive vias 127 may be used to conduct electricity between the circuit layers 125. Optionally, the plurality of conductive vias 127 may be formed of a conductive material (e.g., copper).

[0041] Optionally, in this embodiment, the opening structure may include a first opening structure and a second opening structure that are spaced apart. A dielectric material layer 128 may also be formed between the first opening structure and the second opening structure. Thus, in this embodiment, multiple capacitor structures can be combined to form an array capacitor structure. It should be understood that the first opening structure and the second opening structure here do not refer to two specific opening structures, but to any two opening structures having the feature of being spaced apart. That is, as long as the two opening structures are spaced apart, the two opening structures can be regarded as the first opening structure and the second opening structure, respectively, and in this embodiment, a dielectric material layer 128 can be formed between the two opening structures.

[0042] It should be understood that in some embodiments, according to actual needs, the opening structure may also be a groove formed on the top surface or the bottom surface of the core plate and partially penetrating the core plate.

[0043] Figure 4 FIG. 1 is a cross-sectional view of another packaging system according to an embodiment of the present invention. Figure 4As shown, at least one opening structure 222 can be formed on the top and bottom surfaces of the core plate 221, respectively, and each opening structure 222 is specifically a groove that partially penetrates the core plate 221. The first electrode layer 2221 and the second electrode layer 2222 cover part of the side wall of each of the opening structures 222. The first electrode layer 2221 and the second electrode layer 2222 in each opening structure 222 are electrically isolated from each other and positioned relative to each other. The dielectric material layer 2223 is formed between the first electrode layer 2221 and the second electrode layer 2222. Thus, the first electrode layer 2221 and the second electrode layer 2222 are respectively used as two plates of the capacitor structure, and the dielectric material layer 2223 is used as the dielectric layer of the capacitor structure. The first electrode layer 2221, the second electrode layer 2222 and the dielectric material layer 2223 can also constitute a capacitor structure.

[0044] Furthermore, compared to Figure 2 and Figure 3 The electrical connection structure in Figure 4 The first electrical connection structure 223 and the second electrical connection structure 224 are formed on a side of the core plate 221 having an opening structure to respectively cover each first electrode layer 2221 and each second electrode layer 2222 (it should be understood that if both the top and bottom surfaces of the core plate 221 have opening structures, then the formation positions of the first electrical connection structure 223 and the second electrical connection structure 224 can be determined based on the electrode layers to be covered). It should be understood that the first electrical connection structure 223 and the second electrical connection structure 224 are electrically isolated from each other.

[0045] It should be understood that Figure 4 The packaging system in the invention includes the opening structure and the electrical connection structure corresponding to the opening structure. Figure 2 and Figure 3 Except for the different packaging system, the other structures are the same as Figure 2 and Figure 3 The packaging system is the same as in Figure 4 The other structures of the encapsulation system are not described in detail.

[0046] Optionally, in order to expand the contact area between the electrical connection structure and the electrode layer, thereby reducing the contact resistance and improving the conductive efficiency, the embodiment may further adjust the arrangement of the electrical connection structure.

[0047] Figure 5 and Figure 6 FIG. 1 is a cross-sectional view of another packaging system according to an embodiment of the present invention. Figure 5 and Figure 6As shown, for each opening structure 322, a third electrical connection structure 323 and a fourth electrical connection structure 324 can be formed on either side of the opening structure. The third electrical connection structure 323 can penetrate the core plate 321 (when the opening structure is a groove, the third electrical connection structure can be formed on the side of the core plate with the opening structure) and cover a portion of the top and bottom surfaces of the core plate 321, while also being connected to the first electrode layer 3221. The fourth electrical connection structure 324 penetrates the core plate 321 (when the opening structure is a groove, the fourth electrical connection structure can be formed on the side of the core plate with the opening structure) and covers a portion of the top and bottom surfaces of the core plate 321, while also being connected to the second electrode layer 3222. The third electrical connection structure 323 and the fourth electrical connection structure 324 are electrically isolated from each other.

[0048] It should be understood that Figure 5 and Figure 6 The third electrical connection structure 323 and the fourth electrical connection structure 324 shown in the figure are for illustration only. In actual application, the specific shapes of the various parts of the third electrical connection structure and the fourth electrical connection structure (i.e., the parts located on the top and bottom surfaces of the core plate, the parts that penetrate the core plate, and the parts used to connect to the corresponding electrode layers) can be formed according to actual needs. Among them, the parts of the third electrical connection structure and the fourth electrical connection structure that are connected to the corresponding electrode layers are not limited to being formed inside the core plate. They can also be formed on the top and bottom surfaces of the core plate, respectively. This application does not limit this.

[0049] It should be understood that Figure 5 and Figure 6 The packaging system in the Figure 2 and Figure 3 Except for the different packaging system, the other structures are the same as Figure 2 and Figure 3 The packaging system is the same as in Figure 5 and Figure 6 The other structures of the encapsulation system are not described in detail.

[0050] It should be understood that the configuration of the electrical connection structure given in the above embodiments is only for illustration. In actual applications, the configuration of the electrical connection structure can be formed according to actual needs, and this application does not impose any specific restrictions on this.

[0051] Optionally, in order to maximize the facing area between the first electrode layer 1221 and the second electrode layer 1222 that subsequently cover the side walls of the opening structure 122 (that is, the area directly facing each other between the two plates, the facing area is proportional to the capacitance value) and thus obtain a capacitor structure with higher capacitance, the shape of the opening structure 122 can also be made into other shapes.

[0052] Figure 7 and Figure 8 It should be understood that in order to conveniently show the structural relationship between the first electrode layer, the second electrode layer and the dielectric layer, Figure 7 and Figure 8 The packaging system in the embodiment omits the electrical connection structure. Compared with the above embodiment, Figure 7 and Figure 8 The packaging system in the embodiment forms opening structures of different shapes on the core board.

[0053] like Figure 7 As shown, the opening structure 422 formed on the core plate 421 is in the shape of a hollow cylinder (it should be understood that the opening structure here can be a through hole that penetrates the core plate 421, or a groove that partially penetrates the core plate 421. The present application does not impose specific restrictions on this). At this time, the first electrode layer 4221 and the second electrode layer 4222 respectively cover the outer side wall and the inner side wall of each of the opening structures 422. Thus, the first electrode layer 4221 and the second electrode layer 4222 are respectively used as the two plates of the capacitor structure, and the dielectric material layer 4223 is used as the dielectric layer of the capacitor structure. The first electrode layer 4221, the second electrode layer 4222 and the dielectric material layer 4223 can also constitute a capacitor structure.

[0054] like Figure 8 As shown, the shape of the opening structure 522 formed on the core plate 521 is an irregular shape with a broken line shape on the relative side walls (it should be understood that the hollow cylinder here can be a through hole that passes through the core plate 521, or a groove that partially penetrates the core plate 521. The present application does not impose specific restrictions on this). At this time, the first electrode layer 5221 and the second electrode layer 5222 are respectively covered on the two opposite side walls of each of the opening structures 522. Thus, the first electrode layer 5221 and the second electrode layer 5222 are respectively used as the two plates of the capacitor structure, and the dielectric material layer 5223 is used as the dielectric layer of the capacitor structure. The first electrode layer 5221, the second electrode layer 5222 and the dielectric material layer 5223 can also constitute a capacitor structure.

[0055] It should be understood that the shapes of the opening structures given in the above embodiments are only for illustration. In actual applications, the shape of the opening structure can be formed according to actual needs, and this application does not impose any specific restrictions on this.

[0056] It is to be noted that, in actual application, the above-mentioned opening structure setting mode, electrical connection structure setting mode and opening shape setting mode can be combined with each other according to actual needs.

[0057] Figure 9 This is a flow chart of a method for forming a capacitor in a package substrate according to an embodiment of the present invention. Figure 9 As shown, the forming method of the embodiment of the present invention may specifically include the following steps:

[0058] Step S100: providing a core board.

[0059] Step S200: forming at least one opening structure on the core plate, wherein the opening structure includes a groove partially penetrating the core plate and / or a through hole penetrating the core plate.

[0060] Step S300: For each of the opening structures, a first electrode layer and a second electrode layer are formed to cover part of the side wall of the opening structure, wherein the first electrode layer and the second electrode layer are electrically isolated from each other and positioned opposite to each other, and are used as plates of the capacitor.

[0061] Step S400: forming a dielectric material layer between the first electrode layer and the second electrode layer, wherein the dielectric material layer is used as a dielectric layer of the capacitor.

[0062] In the following description, a specific process flow chart is used to further illustrate the above method of forming a capacitor in a packaging substrate.

[0063] Figure 10-13 This is a schematic diagram of the process of forming a package substrate according to an embodiment of the present invention. It should be understood that Figure 10-13 This is a front cross-sectional view of the packaging substrate during the process. Figure 10 As shown, in step S100, a core plate 100 is provided. Optionally, after the package substrate is formed, the core plate 100 is a physical support layer located in the middle of the package substrate, which can support the entire package structure. To ensure that the package structure can support the entire package structure, the core plate 100 can be pressed using epoxy resin reinforced with glass fiber or other types of rigid materials.

[0064] like Figure 11As shown, in step S200, at least one opening structure 200 is formed on the core plate 100. The opening structure may be a groove that partially penetrates the core plate 100, or a through hole that penetrates the core plate 100. The shape of the opening structure may be a cuboid, a hollow cylinder, or any other related shape. In this embodiment, the opening structure 200 is a through hole that penetrates the core plate 100, and the shape is a cuboid. It should be understood that when the opening structure is a groove that partially penetrates the core plate 100, the opening structure may be formed on the top surface of the core plate 100, or on the bottom surface of the core plate 100, and the present application does not impose specific restrictions on this. Optionally, the opening structure 200 may be formed by first forming a corresponding patterned mask on the core plate 100, and then using the patterned mask for selective etching. Optionally, the etching process selected in this embodiment may be dry etching, wet etching, or any other type of existing etching method, and the present application does not impose specific restrictions on this.

[0065] like Figure 12 As shown, in step S300, for each of the opening structures 200, a first electrode layer 210 and a second electrode layer 220 covering part of the side walls of the opening structure 200 are formed. The first electrode layer 210 and the second electrode layer 220 can be formed of a conductive material. The conductive material can be a conductive metal (such as copper, aluminum, zinc, tantalum or silver, etc.), or a conductive polymer (such as polyaniline or polythiophene, etc.). Furthermore, the first electrode layer 210 and the second electrode layer 220 are electrically isolated from each other and positioned relative to each other. Thus, the first electrode layer 210 and the second electrode layer 220 can be used as plates of the formed capacitor structure. Optionally, the first electrode layer 210 and the second electrode layer 220 that are electrically isolated from each other and positioned relative to each other can be obtained by first forming a conductive material layer covering each side wall of the opening structure 200, then removing the conductive material layer on the corresponding side wall, and then flattening the top surface of the core board 100. It should be understood that for opening structures of certain shapes (such as hollow cylinders), the step of removing the conductive material layer on the corresponding sidewalls can also be omitted. Optionally, the conductive material layer covering the sidewalls of the opening structure 200 can be formed by selecting an appropriate deposition process (such as vapor deposition technology, solid phase deposition technology or liquid phase deposition technology, etc.), and this application does not impose specific restrictions on this. Optionally, in this embodiment, the planarization process used can be a chemical planarization process or a mechanical planarization process, and this application does not impose specific restrictions on this.

[0066] like Figure 13As shown, in step S400, a dielectric material layer 230 is formed between the first electrode layer 210 and the second electrode layer 220. The dielectric material layer 230 can isolate the first electrode layer 210 from the second electrode layer 220, and the dielectric material layer 230 can be formed of an insulating material (such as polyethylene, polystyrene, polypropylene, aluminum oxide, barium titanate or aluminum silicate, etc.). Thus, the dielectric material layer 230 can be used as a dielectric layer of the formed capacitor structure. Optionally, the dielectric material layer 230 between the first electrode layer 210 and the second electrode layer 220 can be formed by filling a dielectric material between the first electrode layer 210 and the second electrode layer 220.

[0067] Optionally, in this embodiment, each opening structure can be used to form a capacitor structure. When the opening structure in this embodiment includes a first opening structure and a second opening structure that are spaced apart, this embodiment can also combine the first opening structure and the second opening structure to form an array capacitor structure. It should be understood that the first opening structure and the second opening structure here do not refer to two specific opening structures, but refer to any two opening structures with the feature of being spaced apart, that is, as long as the two opening structures are spaced apart, then the two opening structures can be regarded as the first opening structure and the second opening structure, respectively. In order to achieve the above operations, the method for forming a capacitor in a packaging substrate of an embodiment of the utility model may further include steps S500 and S600.

[0068] Step S500 : After forming a dielectric material layer between the first electrode layer and the second electrode layer, etching the core material between the first opening structure and the second opening structure.

[0069] Step S600 : forming a dielectric material layer between the first opening structure and the second opening structure.

[0070] Figure 14-15 This is a schematic diagram of the process of forming a package substrate according to an embodiment of the present invention. It should be understood that Figure 14-15 This is a front cross-sectional view of the packaging substrate during the process. Figure 13 and Figure 14 As shown, in step S500, after forming the dielectric material layer 230 located between the first electrode layer 210 and the second electrode layer 220, the core board material 300 between the first opening structure (i.e., the opening structure 200 located on the left) and the second opening structure (i.e., the opening structure 200 located on the right) is etched.

[0071] like Figure 15As shown, in step S600, a dielectric material layer 400 is formed between the first opening structure and the second opening structure. Thus, the capacitor structure formed by the first opening structure and the capacitor structure formed by the second opening structure can be combined into a capacitor array. It should be understood that the capacitor array formed in the schematic diagram given in this embodiment is only for illustration. In actual application, the number of capacitor structures in the capacitor array is not limited to this. It should be understood that steps S500 and S600 are optional steps that can be executed. In actual application, steps S500 and S600 can be selected based on actual needs to determine whether they need to be executed.

[0072] Optionally, in this embodiment, in order to enable the formed capacitor structure to achieve electrical connection with the chip and the circuit board, this embodiment may also form a corresponding electrical connection structure for each capacitor structure. To achieve the above operation, the method for forming a capacitor in a packaging substrate according to the embodiment of the present invention may further include steps S700 and S800.

[0073] Step S700: For each of the first electrode layers, a first electrical connection structure covering the first electrode layer is formed, wherein the first electrical connection structure is located on the top surface of the core board or respectively on the top surface and bottom surface of the core board.

[0074] Step S800: For each second electrode layer, a second electrical connection structure covering the second electrode layer is formed, the second electrical connection structure is located on the top surface of the core board or respectively on the top surface and bottom surface of the core board, and the first electrical connection structure and the second electrical connection structure are electrically isolated from each other.

[0075] Figure 16-Figure 19 This is a schematic diagram of the process of forming a package substrate according to an embodiment of the present invention. Figure 16 and Figure 17 They are the front cross-sectional view and top view of the packaging substrate during the process. Figure 16 and Figure 17 As shown, in step S700, for each first electrode layer 210, a first electrical connection structure 500 covering the first electrode layer 210 is formed. The first electrical connection structure 500 is respectively located on the top and bottom surfaces of the core plate 100. It should be understood that when the opening structure is a groove that partially penetrates the core plate 100, the first electrical connection structure 500 can also be formed on the side of the core plate 100 having the opening structure (it should be understood that if both the top and bottom surfaces of the core plate 100 have opening structures, then the formation position of the first electrical connection structure can be determined according to the electrode layer it is to cover).

[0076] Figure 18 and Figure 19 They are the front cross-sectional view and top view of the packaging substrate during the process. Figure 18 and Figure 19 As shown, in step S800, for each second electrode layer 220, a second electrical connection structure 600 covering the second electrode layer 220 is formed. The second electrical connection structure 600 is respectively located on the top and bottom surfaces of the core plate 100. It should be understood that when the opening structure is a groove that partially penetrates the core plate 100, the second electrical connection structure 600 can also be formed on the side of the core plate 100 having the opening structure (it should be understood that if both the top and bottom surfaces of the core plate 100 have an opening structure, then the formation position of the second electrical connection structure can be determined according to the electrode layer it is to cover). It should be understood that the first electrical connection structure 500 and the second electrical connection structure 600 are electrically isolated from each other.

[0077] Optionally, the first electrical connection structure 500 and the second electrical connection structure 600 can be formed by conductive materials. The first electrical connection structure 500 and the second electrical connection structure 600 can be formed by first forming a corresponding patterned mask on the core board 100, then using the patterned mask to deposit the conductive material, and then removing the patterned mask and the deposited excess conductive material.

[0078] Alternatively, as an alternative, this embodiment may also employ other methods to form corresponding electrical connection structures for each capacitor structure. To achieve the above operations, the method for forming a capacitor in a package substrate according to an embodiment of the present invention may further include step S900. It should be understood that in actual applications, step S700 and step S800 may be replaced with step S900 according to actual circuit design requirements.

[0079] Step S900 : For each of the opening structures, forming a third electrical connection structure and a fourth electrical connection structure on both sides of the opening structure respectively.

[0080] Figure 20 This is a schematic diagram of the process of forming a package substrate according to an embodiment of the present invention. Figure 20 The figure shows a top view of the package substrate during the process. In step S900, for each opening structure 200', a third electrical connection structure 500' and a fourth electrical connection structure 600' are formed on both sides of the opening structure 200'. The third electrical connection structure 500' and the fourth electrical connection structure 600' both penetrate the core board 100' and cover part of the top surface and part of the bottom surface of the core board 100'. The third electrical connection structure 500' is also connected to the first electrode layer 210', and the fourth electrical connection structure 600' is also connected to the second electrode layer 220'. The third electrical connection structure 500' and the fourth electrical connection structure 600' are electrically isolated from each other.

[0081] Optionally, the third electrical connection structure 500' and the fourth electrical connection structure 600' may be formed of a conductive material. The third electrical connection structure 500' and the fourth electrical connection structure 600' may be formed by first forming a corresponding patterned mask on the core board 100', etching the corresponding core board material using the patterned mask, then filling the etched through holes with a conductive material, and then flattening the top and bottom surfaces of the core board 100' to remove the patterned mask and excess conductive material.

[0082] It should be understood that Figure 20 The third electrical connection structure 500' and the fourth electrical connection structure 600' shown in the figure are for illustration only. In actual application, the specific shapes of the various parts of the third electrical connection structure 500' and the fourth electrical connection structure 600' (i.e., the parts located on the top and bottom surfaces of the core plate, the parts that penetrate the core plate, and the parts used to connect to the corresponding electrode layers) can be formed according to actual needs. Among them, the parts of the third electrical connection structure and the fourth electrical connection structure that connect to the corresponding electrode layers are not limited to being formed inside the core plate. They can also be formed on the top and bottom surfaces of the core plate, respectively, and this application does not limit this.

[0083] Alternatively, the present embodiment can also form corresponding circuit layers on the top and bottom surfaces of the core plate, and the circuit layers can be used to realize electrical connection between the capacitor structure, the chip and the circuit board. Specifically, the present embodiment can form at least one circuit layer on the top and bottom surfaces of the core plate respectively. Wherein, each of the circuit layers is bonded by an adhesive layer (such as a prepreg). Further, in the process of forming each circuit layer, the present embodiment can also form conductive vias for connecting each circuit layer, and the conductive vias can realize electrical connection between each circuit layer.

[0084] Figure 21 This is a schematic diagram of the package substrate after molding according to an embodiment of the present invention. It should be understood that Figure 21 Specifically, it is a front cross-sectional view of the package substrate after molding. Figure 21 As shown, in this embodiment, at least one circuit layer 700 can be formed on the top and bottom surfaces of the core board 100. The circuit layers 700 can be bonded together by an adhesive layer 800. The circuit layers 700 can be electrically connected through conductive vias 900.

[0085] Alternatively, each circuit layer 700 may be formed directly on the core substrate 100 and the corresponding adhesive layer 800 through a deposition and etching process, or may be formed by laminating a conductive material film (e.g., copper foil) printed with a circuit pattern formed through a series of process steps onto the core substrate 100 and the corresponding adhesive layer 800. Each conductive via 900 may be formed by adopting a corresponding conductive via deposition process, which is not limited in this application.

[0086] The packaging substrate in an embodiment of the present invention includes a core board, at least one opening structure formed in the core board, a first electrode layer and a second electrode layer covering a portion of the sidewalls of each opening structure, and a dielectric material layer formed between each first electrode layer and each second electrode layer. The opening structure includes a groove that partially penetrates the core board and / or a through hole that penetrates the core board. The first electrode layer and the second electrode layer are electrically isolated from each other and positioned opposite each other. The first electrode layer and the second electrode layer are used to serve as the plates of a capacitor, and the dielectric material layer is used to serve as the dielectric layer of the capacitor. The packaging substrate can reduce the package size while reducing the loop inductance of the power distribution network and improving link parasitics.

[0087] The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application are intended to be within the scope of protection of the present application.

Claims

1. A packaging substrate, characterized in that: The packaging substrate includes: core board; at least one opening structure formed on the core plate, the opening structure comprising a groove partially penetrating the core plate and / or a through hole penetrating the core plate; a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer cover a portion of a sidewall of each of the opening structures, the first electrode layer and the second electrode layer are electrically isolated from each other and positioned opposite to each other, and the first electrode layer and the second electrode layer are used to serve as plates of a capacitor; A dielectric material layer is formed between each of the first electrode layers and each of the second electrode layers, and the dielectric material layer is used as a dielectric layer of the capacitor.

2. The packaging substrate according to claim 1, wherein: The opening structure includes a first opening structure and a second opening structure that are spaced apart from each other, and the dielectric material layer is further formed between the first opening structure and the second opening structure.

3. The packaging substrate according to claim 1, wherein: The packaging substrate further includes: A first electrical connection structure is formed on a side of the core plate having the opening structure or on the top and bottom surfaces of the core plate, covering each of the first electrode layers; The second electrical connection structure is formed on the side of the core board having the opening structure or on the top and bottom surfaces of the core board respectively, covering each second electrode layer. The first electrical connection structure and the second electrical connection structure are electrically isolated from each other.

4. The packaging substrate according to claim 1, wherein: The packaging substrate further includes: a third electrical connection structure formed on one side of the opening structure, the third electrical connection structure penetrating the core plate and covering a portion of the top surface and a portion of the bottom surface of the core plate, and the third electrical connection structure being further connected to the first electrode layer; A fourth electrical connection structure is formed on the other side of the opening structure. The fourth electrical connection structure passes through the core board and covers part of the top surface and part of the bottom surface of the core board. The fourth electrical connection structure is also connected to the second electrode layer. The third electrical connection structure and the fourth electrical connection structure are electrically isolated from each other.

5. The packaging substrate according to claim 1, wherein: The packaging substrate further includes: At least one circuit layer is formed on the top surface and the bottom surface of the core board respectively; An adhesive layer is formed between the circuit layers.

6. The packaging substrate according to claim 1, wherein: It is characterized in that The opening structure is in the shape of a cuboid.

7. The packaging substrate according to claim 1, wherein: It is characterized in that The first electrode layer and the second electrode layer are made of copper.

8. The packaging substrate according to claim 5, wherein: It is characterized in that The adhesive layer is a prepreg.

9. The packaging substrate according to claim 5, wherein: It is characterized in that The circuit layers are electrically connected via conductive through-holes.

10. A packaged chip, characterized in that: The packaged chip comprises: chip; The packaging substrate according to any one of claims 1 to 9, wherein the packaging substrate is used to carry the chip and realize electrical connection between the chip and a circuit board.

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