Package structure

Abstract

The utility model discloses a packaging structure. The packaging structure comprises a rectification unit; a power factor correction unit; the power unit comprises a low-side driving chip, a high-side driving chip, a plurality of low-side transistors driven by the low-side driving chip, and a plurality of high-side transistors driven by the high-side driving chip; a lead frame having a plurality of pins; the plastic package body wraps the lead frame, the rectification unit, the power factor correction unit and the power unit; the plastic package body comprises a first side edge and a second side edge which are opposite to each other, and a third side edge and a fourth side edge which are opposite to each other, the plurality of pins extend to the outside along the third side edge and the fourth side edge of the plastic package body, and the power factor correction unit is located between the rectification unit and the power unit. The three units are integrated in the same packaging structure, so that the packaging structure has the functions of rectification, power factor correction and inversion, the peripheral wiring is simplified, the cost is reduced, and the circuit reliability of the packaging structure is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and more particularly to a packaging structure. Background Art

[0002] An IPM (Intelligent Power Module) is a new type of high-power power electronic device with advantages such as high current density, low saturation voltage, and high voltage resistance. It is currently widely used in various fields such as air conditioners, washing machines, and fans. Existing power modules typically require a rectifier circuit and a power factor correction circuit to form a variable frequency control circuit for application.

[0003] Traditional power modules only have one set of three-phase power units. In actual use, the rectifier circuit and power factor correction circuit need to be additionally arranged outside the power module packaging structure. This not only takes up the area of ​​the circuit board, but also makes the wiring and connection more complicated and inconvenient to use. Due to the use of external connection, it is susceptible to interference, lacks reliability, and increases costs. Utility Model Content

[0004] In view of the above problems, the purpose of the present invention is to provide a packaging structure suitable for variable frequency control, improve the usability of the packaging structure, and solve the above problems.

[0005] The utility model provides a packaging structure, which is used for a frequency conversion control circuit and includes: a rectifier unit; a power factor correction unit; a power unit, wherein the power unit includes a low-side driver chip, a high-side driver chip, a plurality of low-side transistors driven by the low-side driver chip, and a plurality of high-side transistors driven by the high-side driver chip; a lead frame, wherein the lead frame has a plurality of pins; a plastic package, wherein the plastic package covers the lead frame, the rectifier unit, the power factor correction unit and the power unit; the plastic package includes a first side and a second side relative to each other, and a third side and a fourth side relative to each other, wherein the first side and the second side extend in a width direction, and the third side and the fourth side extend in a length direction; the plurality of pins extend to the outside along the third side and the fourth side of the plastic package; and the power factor correction unit is located between the rectifier unit and the power unit.

[0006] Optionally, the rectifier unit is close to a first side of the plastic package body, and the power unit is close to a second side of the plastic package body.

[0007] In the above-mentioned packaging structure, the rectifier unit has a plurality of power diodes.

[0008] Optionally, the high-side driver chip includes a plurality of bootstrap diodes.

[0009] Optionally, the low-side driver chip includes one or more of an over-temperature protection circuit, an over-current protection circuit, an under-voltage protection circuit and a fault output circuit.

[0010] Optionally, the over-temperature protection circuit, the over-current protection circuit and the fault output circuit share the same pin for outputting protection signals.

[0011] Optionally, the power factor correction unit includes a power factor correction chip, a first transistor, a second transistor, a first fast recovery diode and a second fast recovery diode; the first end of the first transistor is connected to the anode of the first fast recovery diode to lead out a first current input end, the second end of the first transistor is connected to the first current output end, and the control end of the first transistor is connected to the first voltage output end of the power factor correction chip; the first end of the second transistor is connected to the anode of the second fast recovery diode to lead out a second current input end, the second end of the second transistor is connected to the second current output end, and the control end of the second transistor is connected to the second voltage output end of the power factor correction chip; the cathodes of the first fast recovery diode and the second fast recovery diode are connected to the DC positive terminal.

[0012] Optionally, the ground terminal of the power factor correction chip, the ground terminal of the high-side driver chip and the ground terminal of the low-side driver chip are shared by a common ground.

[0013] Optionally, the first PFC signal input end of the power factor correction chip serves as the first signal input end of the package structure, and the second PFC signal input end of the power factor correction chip serves as the second signal input end of the package structure.

[0014] Optionally, the power supply terminal of the power factor correction chip is connected to the inverter topology power supply voltage input terminal of the package structure.

[0015] In the above-mentioned packaging structure, the power factor correction unit includes a power factor correction chip, a first transistor and a first fast recovery diode; the first end of the first transistor is connected to the anode of the first fast recovery diode to lead to a first current output end, the second end of the first transistor leads to a first current input end, the control end of the first transistor is connected to the first output end of the power factor correction chip; and the first fast recovery diode is connected to the DC positive terminal.

[0016] Optionally, the first PFC signal input end of the power factor correction chip serves as the first signal input end of the packaging structure.

[0017] In the above-mentioned packaging structure, a first inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the first current input terminal of the packaging structure.

[0018] Optionally, a second inductor is connected outside the plastic package between the DC bus voltage positive output terminal and the second current input terminal of the packaging structure.

[0019] Optionally, a first inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the first current input terminal of the packaging structure; a second inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the second current input terminal of the packaging structure.

[0020] The above-mentioned packaging structure also includes multiple base islands, which include a first base island, a second base island, a third base island, a fourth base island, a fifth base island, a sixth base island, a seventh base island, an eighth base island, and a ninth base island arranged in parallel in sequence along the length direction, wherein the third base island is arranged in parallel with the second base island; the multiple power diodes include a first power diode, a second power diode, a third power diode, and a fourth power diode, the first power diode and the second power diode are located on the first base island, and the third power diode and the fourth power diode are located on the second base island and the third base island respectively; the first transistor is located on the fourth base island, and the second transistor is located on the fifth base island; the multiple high-side transistors include three high-side transistors; the first fast recovery diode, the second fast recovery diode, and the three high-side transistors are located on the sixth base island; the multiple low-side transistors include three low-side transistors; and the three low-side transistors are respectively installed on the seventh base island, the eighth base island, and the ninth base island.

[0021] Optionally, the power unit further includes a plurality of low-side diodes and a plurality of high-side diodes, the plurality of low-side diodes corresponding to the plurality of low-side transistors, and the plurality of high-side diodes corresponding to the plurality of high-side transistors.

[0022] Optionally, the plurality of high-side diodes include three high-side diodes, the three high-side diodes are respectively connected to the three high-side transistors, and the three high-side diodes, the three high-side transistors, the first fast recovery diode and the second fast recovery diode are located on the sixth base island; the plurality of low-side diodes include three low-side diodes, the three low-side diodes are respectively connected to the three low-side transistors, and the three low-side diodes and their corresponding low-side transistors are respectively located on the same base island.

[0023] Optionally, the plurality of base islands further include a tenth base island, and the power factor correction chip, the high-side driver chip, and the low-side driver chip are sequentially mounted on the tenth base island.

[0024] Optionally, the first to ninth base islands are located on a heat dissipation substrate, and the tenth base island is located between the heat dissipation substrate and the third side of the plastic package body.

[0025] Optionally, the transistor in the power factor correction unit and the transistor in the power unit include any one of a MOS device, an RC-IGBT device, an IGBT device, and an IGBT device with a fast recovery diode sealed therein.

[0026] The above-mentioned packaging structure also includes multiple base islands, and the multiple base islands include a first base island, a second base island, a third base island, a fourth base island, a fifth base island, a sixth base island, a seventh base island, and an eighth base island arranged in parallel in sequence along the length direction, wherein the third base island is arranged in parallel with the second base island; the several power diodes include a first power diode, a second power diode, a third power diode and a fourth power diode, the first power diode and the second power diode are located on the first base island, and the third power diode and the fourth power diode are located on the second base island and the third base island respectively; the first transistor is located on the fourth base island; the several high-side transistors include three high-side transistors; the first fast recovery diode and the three high-side transistors are located on the fifth base island; the several low-side transistors include three low-side transistors; the three low-side transistors are respectively installed on the sixth base island, the seventh base island and the eighth base island.

[0027] Optionally, the power unit further includes a plurality of low-side diodes and a plurality of high-side diodes, the plurality of low-side diodes corresponding to the plurality of low-side transistors, and the plurality of high-side diodes corresponding to the plurality of high-side transistors.

[0028] Optionally, the plurality of high-side diodes include three high-side diodes, the three high-side diodes are respectively connected to the three high-side transistors, and the three high-side diodes, the three high-side transistors and the first fast recovery diode are located on the sixth base island; the plurality of low-side diodes include three low-side diodes, the three low-side diodes are respectively connected to the three low-side transistors, and the three low-side diodes and their corresponding low-side transistors are respectively located on the same base island.

[0029] Optionally, the plurality of base islands further include a ninth base island, and the power factor correction chip, the high-side driver chip, and the low-side driver chip are sequentially mounted on the ninth base island.

[0030] Optionally, the first to eighth base islands are located on the heat dissipation substrate, and the ninth base island is located between the heat dissipation substrate and the third side of the plastic package body.

[0031] Optionally, the packaging structure is a plug-in package.

[0032] Optionally, the first base island is connected to the anode of the first power diode and the anode of the second power diode; the second base island is connected to the anode of the third power diode, and the third base island is connected to the anode of the fourth power diode.

[0033] Optionally, the AC input negative terminal, the first current output terminal, the second current output terminal, the first current input terminal, the second current input terminal, the DC positive terminal, the first phase output terminal, the second phase output terminal, the third phase output terminal, the first phase DC power supply negative terminal, the second phase DC power supply negative terminal and the third phase DC power supply negative terminal are located on the fourth side of the plastic package body, and the fourth side of the plastic package body is all high-voltage pins.

[0034] Optionally, the AC input negative terminal, the first current output terminal, the first current input terminal, the DC positive terminal, the first phase output terminal, the second phase output terminal, the third phase output terminal, the first phase DC power supply negative terminal, the second phase DC power supply negative terminal and the third phase DC power supply negative terminal are located on the fourth side of the plastic package body, and the fourth side of the plastic package body is all high-voltage pins.

[0035] Optionally, the DC bus voltage output positive terminal, the DC bus voltage output negative terminal and the pins of the power factor correction chip, the low-side driver chip and the high-side driver chip are all located on the third side of the plastic package body, and the DC bus voltage output positive terminal and the DC bus voltage output negative terminal are high-voltage pins.

[0036] Optionally, the AC input positive terminal is located on the third side or the fourth side of the plastic package body.

[0037] Optionally, when the AC input positive terminal is on the third side, the pins other than the AC input positive terminal, the DC bus voltage output positive terminal and the DC bus voltage output negative terminal are low-voltage pins.

[0038] Optionally, when the AC input positive terminal is on the fourth side, the pins other than the DC bus voltage output positive terminal and the DC bus voltage output negative terminal are low-voltage pins.

[0039] Optionally, the DC positive terminal pin is located between the pin of the power factor correction unit and the output pin of the power unit.

[0040] Optionally, among the pins of the packaging structure, the pin connected to the power factor correction unit is between the pin connected to the rectifier unit and the pin connected to the power unit.

[0041] In the above-mentioned packaging structure, the DC bus voltage output positive terminal (DC+) is welded to the first base island; the first current input terminal (PF1+) is welded to the fourth base island; the second current input terminal (PF2+) is welded to the fifth base island; the DC positive terminal (P) is welded to the sixth base island; the first phase output terminal (U) is welded to the seventh base island; the second phase output terminal (V) is welded to the eighth base island; and the third phase output terminal (W) is welded to the ninth base island.

[0042] In the above-mentioned packaging structure, the DC bus voltage output positive terminal (DC+) is welded to the first base island; the first current input terminal (PF1+) is welded to the fourth base island; the DC positive terminal (P) is welded to the fifth base island; the first phase output terminal (U) is welded to the sixth base island; the second phase output terminal (V) is welded to the seventh base island; and the third phase output terminal (W) is welded to the eighth base island.

[0043] In the above-mentioned packaging structure, the DC bus voltage output positive terminal (DC+) and the first current input terminal (PF1+) and the second current input terminal (PF2+) are respectively located on different sides of the plastic package.

[0044] The packaging structure provided by this utility model integrates the rectifier unit, power factor correction unit, and power unit into a single plastic package, enabling the package structure to provide rectification, power factor correction, and inversion functions. This not only simplifies peripheral wiring and reduces costs, but also improves the usability and reliability of the package structure with a variable frequency control circuit.

[0045] Furthermore, the bootstrap diode is integrated into the high-side driver chip, and the protection circuit is integrated into the low-side driver chip to further reduce the overall volume; a heat dissipation substrate is added, and the transistors, high-side transistors and low-side transistors of the power factor correction unit are arranged on the heat dissipation substrate to further enhance the heat dissipation performance of the packaging structure.

[0046] Specifically, in this packaging structure, the power factor correction unit is located between the rectifier unit and the power unit. Among the pins of this packaging structure, the pin connected to the power factor correction unit is between the pin connected to the rectifier unit and the pin connected to the power unit. This layout facilitates the bonding wire connection between the power factor correction unit and the rectifier unit, and also facilitates the bonding wire connection between the power factor correction unit and the power unit for realizing motor control. Furthermore, the DC bus voltage output positive terminal (DC+) and the first current output terminal (PF1+) and the second current output terminal (PF2+) are respectively located on the upper and lower sides of the plastic package, which facilitates the routing and connection of the external inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0048] Figure 1 A circuit diagram showing the packaging structure of the first embodiment of the present invention;

[0049] Figure 2 A schematic diagram of the packaging structure of the first embodiment of the present invention is shown;

[0050] Figure 3 A circuit diagram showing the packaging structure of the second embodiment of the present invention;

[0051] Figure 4 A schematic diagram showing the packaging structure of the second embodiment of the present invention is shown;

[0052] Figure 5 A schematic diagram showing the packaging structure of the third embodiment of the present invention is shown;

[0053] Figure 6 A schematic diagram of the packaging structure of the fourth embodiment of the present utility model is shown. DETAILED DESCRIPTION

[0054] The present invention will be described in more detail below with reference to the accompanying drawings. For the sake of clarity, parts in the drawings are not drawn to scale. In addition, certain well-known parts may not be shown. Numerous specific details of the present invention are described below, but as those skilled in the art will appreciate, the present invention may be practiced without these specific details.

[0055] The present invention may be embodied in various forms, some examples of which will be described below.

[0056] Figure 1 A circuit diagram showing the packaging structure of the first embodiment of the present invention is shown. Figure 2 A schematic diagram of the packaging structure of the first embodiment of the present utility model is shown, and the packaging structure includes, for example, a frequency conversion control circuit.

[0057] like Figure 1As shown, the circuit of this package structure includes, for example, a rectifier unit 100, a power factor correction unit 200, and a power unit 300. By integrating these three units into the same package structure, the frequency conversion control circuit has rectification, power factor correction, and inversion functions. This not only simplifies peripheral wiring and reduces costs, but also improves the reliability of the frequency conversion control circuit. Specifically, the frequency conversion control circuit adopts a single-phase AC input, for example, and its live wire and neutral wire are respectively connected to pin L and pin N as AC input to enter the rectifier unit 100. The rectifier unit 100 includes, for example, four power diodes D9~D12, the anode of the power diode D9 is connected to the cathode of the power diode D11, and the node between the two is connected to pin N; the anode of the power diode D10 is connected to the cathode of the power diode D12, and the node between the two is connected to pin L; the cathode of the power diode D9 is connected to the cathode of the power diode D10 and to pin DC-, and pin DC- serves as the negative pole of the DC output after rectification; the anode of the power diode D11 is connected to the anode of the power diode D12 and to pin DC+, and pin DC+ serves as the positive pole of the DC output after rectification.

[0058] In the variable frequency control circuit of the first embodiment, the power factor correction unit 200 adopts a dual-path design, and accordingly, the power factor correction chip A1 is a dual-path chip. Specifically, the power factor correction unit 200 includes: a power factor correction chip A1, two transistors Q1 and Q2, and two fast recovery diodes D1 and D2. The IN1 terminal of the power factor correction chip A1 is connected to the pin IN1, the IN2 terminal of the power factor correction chip A1 is connected to the pin IN2, and the VCC terminal of the power factor correction chip A1 is connected to the pin V CCP The OUT1 terminal of the power factor correction chip A1 is connected to the gate of the transistor Q1, the emitter of the transistor Q1 is connected to the pin PF1-, the collector of the transistor Q1 is connected to the pin PF1+ and the anode of the fast recovery diode D1, and the cathode of the fast recovery diode D1 is connected to the pin P; the OUT2 terminal of the power factor correction chip A1 is connected to the gate of the transistor Q2, the emitter of the transistor Q2 is connected to the pin PF2-, the collector of the transistor Q2 is connected to the pin PF2+ and the anode of the fast recovery diode D2, and the cathode of the fast recovery diode D2 is connected to the pin P; the GND terminal of the power factor correction chip A1 is connected to the pin COM.

[0059] The power unit 300 includes, for example, a high-side driver chip A2, a low-side driver chip A3, three high-side transistors Q3 to Q5, three high-side diodes D3 to D5, three low-side transistors Q6 to Q8, and three low-side diodes D6 to D8. Specifically, the UVS terminal of the high-side driver chip A2 is connected to the pin V SU Connected, UBS end and pin VBU Connected, VVS end and pin V SV Connected, VBS end and pin V BV connected, WVS end and pin V SW connected, WBS end and pin V BW Connected, IN UH Terminal and pin IN UH Connected, IN VH Terminal and pin IN VH Connected, IN WH Terminal and pin IN WH connected, VCCH end and pin V CCI The COM terminal is connected to the pin COM; the OUTUH terminal is connected to the gate of the high-side transistor Q3, the collector of the high-side transistor Q3 is connected to the cathode of the high-side diode D3 and is connected to the pin P, and the emitter of the high-side transistor Q3 is connected to the anode of the high-side diode D3 and is connected to the UVS terminal and the pin U; ​​the OUTVH terminal is connected to the gate of the high-side transistor Q4, the collector of the high-side transistor Q4 is connected to the cathode of the high-side diode D4 and is connected to the pin P, the emitter of the high-side transistor Q4 is connected to the anode of the high-side diode D4 and is connected to the VVS terminal and the pin V; the OUTWH terminal is connected to the gate of the high-side transistor Q5, the collector of the high-side transistor Q5 is connected to the cathode of the high-side diode D5 and is connected to the pin P, and the emitter of the high-side transistor Q5 is connected to the anode of the high-side diode D5 and is connected to the WVS terminal and the pin W.

[0060] IN of low-side driver chip A3 UL Terminal and pin IN UL Connected, IN VL Terminal and pin IN VL Connected, IN WL End and IN WL Connected, VCCL end and pin V CCI Connected, VFO end and pin V FO Connected, CSC end and pin C SC connected, COM terminal connected to pin COM, VOT terminal connected to pin V OTThe OUTUL terminal is connected to the gate of the low-side transistor Q6, the collector of the low-side transistor Q6 is connected to the cathode of the low-side diode D6 and is connected to the pin U, and the emitter of the low-side transistor Q6 is connected to the anode of the low-side diode D6 and is connected to the pin NU; the OUTVL terminal is connected to the gate of the low-side transistor Q7, the collector of the low-side transistor Q7 is connected to the cathode of the low-side diode D7 and is connected to the pin V, the emitter of the low-side transistor Q7 is connected to the anode of the low-side diode D7 and is connected to the pin NV, the OUTWL terminal is connected to the gate of the low-side transistor Q8, the collector of the low-side transistor Q8 is connected to the cathode of the low-side diode D8 and is connected to the pin W, and the emitter of the low-side transistor Q8 is connected to the anode of the low-side diode D8 and is connected to the pin NW.

[0061] from Figure 2 As can be seen in FIG, power diodes D9 and D10 are located on the first base island, power diode D11 is located on the second base island, and power diode D12 is located on the third base island. The second and third base islands are located on the right side of the first base island and are arranged side by side along the first side of the plastic package. Figure 1 For simplicity, Figure 2 The description of the electrical connection using bonding wires will not be repeated.

[0062] The anodes of the power diodes D9 and D10 are electrically connected to the first base island, which is connected to the pin DC+ by welding; the anode of the power diode D11 is electrically connected to the second base island, and the anode of the power diode D12 is electrically connected to the third base island.

[0063] The transistor Q1 is located on the fourth base island, the collector of the transistor Q1 is electrically connected to the fourth base island, and the fourth base island is connected to the pin PF1+ by welding; the transistor Q2 is located on the fifth base island, the collector of the transistor Q2 is electrically connected to the fifth base island, and the fifth base island is connected to the pin PF2+ by welding;

[0064] Fast recovery diodes D1 and D2, high-side transistors Q3-Q5, and high-side diodes D3-D5 are all located on the sixth base island. The cathodes of fast recovery diodes D1 and D2, the collectors of high-side transistors Q3-Q5, and the cathodes of high-side diodes D3-D5 are all electrically connected to the sixth base island (by being mounted on the sixth base island). The sixth base island is connected to pin P by welding.

[0065] Low-side transistors Q6-Q8 are located on the seventh, eighth, and ninth base islands, respectively. Correspondingly, low-side diodes D6-D8 and their corresponding low-side transistors are located on the same base island. The seventh base island is connected to pin U via soldering, the eighth base island is connected to pin V via soldering, and the ninth base island is connected to pin W via soldering.

[0066] The power factor correction chip A1, the high-side driver chip A2 and the low-side driver chip A3 are all located on the tenth base island. The first to ninth base islands are arranged in sequence, for example, along the fourth side of the plastic package body. The second base island and the third base island are parallel, so that the rectifier unit 100 is located near the first side 11 of the plastic package body, the power unit 300 is located near the second side 12 of the plastic package body, and the power factor correction unit 200 is located between the rectifier unit 100 and the power unit 300.

[0067] Furthermore, the package structure further includes a heat dissipation substrate 40. The first to ninth islands are all located on the heat dissipation substrate 40. The tenth island is located between the heat dissipation substrate 40 and the third side 13 of the plastic package. The heat dissipation substrate 40 is, for example, a copper-clad ceramic substrate.

[0068] The high-side driver chip A2 integrates a bootstrap circuit design, which simplifies peripheral circuitry, reduces the difficulty of frequency conversion control circuit design, and reduces costs. The low-side driver chip A3 integrates protection circuitry, specifically, including over-temperature protection, over-current protection, under-voltage protection, and fault output.

[0069] In the dual-path power factor correction unit design, the two-path power factor correction circuit consists of two boost converters operating with a 180° phase shift. The input current is the sum of the two inductor currents. Because the inductor ripple currents are in opposite phases, the currents cancel each other out, reducing the inductor ripple current generated by the boost inductor.

[0070] Specifically, a first inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the transistor Q1 current output terminal, and a second inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the transistor Q2 current output terminal. The currents of the first inductor and the second inductor are input from the transistor Q1 current output terminal and the transistor Q2 current output terminal, respectively.

[0071] In this embodiment, the high-side transistor and the low-side transistor are one of a MOS (metal-oxide semiconductor field-effect transistor) device, an RC-IGBT (reverse-conducting transistor) device, an IGBT (insulated gate bipolar transistor) device, and an IGBT device with a fast recovery diode.

[0072] When the transistor is a MOS device, the first end of the transistor is the drain, the second end is the source, and the control end is the gate; when the transistor is an IGBT device, the first end of the transistor is the collector, the second end is the emitter, and the control end is the base.

[0073] Figure 2 The package structure of the variable frequency control circuit includes multiple pins. The pin names and descriptions are shown in the following table.

[0074] Table 1. Pin names and descriptions of the variable frequency control circuit package structure

[0075] Pin Name describe Pin Name describe N AC input negative terminal INVL V-phase low-side signal input terminal PF1- The first current output terminal INWL W-phase low-side signal input terminal PF2- The second current output terminal INUH U-phase high-side signal input terminal PF1+ First current input terminal INVH V-phase high-side signal input terminal PF2+ Second current input terminal INWH W-phase high-side signal input terminal P DC positive terminal VSU U-phase high-side floating power supply ground terminal U U phase output terminal VBU U-phase high-side floating power supply voltage terminal V V phase output terminal VSV V-phase high-side floating power supply ground terminal W W phase output terminal VBV V-phase high-side floating power supply voltage terminal NU U-phase DC power supply negative terminal VSW W-phase high-side floating power supply ground terminal NV V-phase DC power supply negative terminal VBW W-phase high-side floating power supply voltage terminal NW W phase DC power supply negative terminal VCCP Inverter topology supply voltage input VOT Temperature signal output IN2 Second signal input terminal COM Public land IN1 First signal input terminal CSC Overcurrent protection signal input terminal DC- DC bus voltage output negative terminal VFO Fault signal output DC+ DC bus voltage output positive terminal VCCI PFC topology supply voltage input L AC input positive terminal INUL U-phase low-side signal input terminal

[0076] Specifically, in this packaging structure, the over-temperature protection circuit, the over-current protection circuit, and the fault output circuit share the same pin (fault signal output terminal VFO) to output the fault signal.

[0077] The first end of the transistor Q1 is connected to the anode of the fast recovery diode D1 to lead to the first current output end (PF1+), the second end of the transistor Q1 is connected to the first current input end (PF1-), and the control end of the transistor Q1 is connected to the first output end (OUT1) of the power factor correction chip A1;

[0078] The first end of transistor Q2 is connected to the anode of the second fast recovery diode D2 to lead out the second current output end (PF2+), the second end of transistor Q2 is connected to the second current input end (PF2-), and the control end of transistor Q2 is connected to the second output end (OUT2) of the power factor correction chip A1; the cathodes of the first fast recovery diode D1 and the second fast recovery diode D2 are connected to the DC positive terminal (P).

[0079] The ground terminal (GND) of the power factor correction chip A1, the ground terminal (com) of the high-side driver chip A2, and the ground terminal (com) of the low-side driver chip A3 are grounded in common.

[0080] The first PFC input signal terminal of the power factor correction chip A1 serves as the first input signal terminal of the package structure, and the second PFC input signal terminal of the power factor correction chip A1 serves as the second input signal terminal of the package structure. The power supply terminal (VCC) of the power factor correction chip A1 is connected to the inverter topology supply voltage (VCCP) input terminal of the package structure. A first inductor is connected outside the plastic package between the DC bus voltage output positive terminal (DC+) and the first current output terminal (PF1+) of the package structure. A second inductor is connected outside the plastic package between the DC bus voltage output positive terminal (DC+) and the second current output terminal (PF2+) of the package structure.

[0081] Although the AC input positive terminal (L) is located on the third side of the plastic package body in the packaging structure of the first embodiment, the AC input positive terminal (L) can also be set on the fourth side of the plastic package body according to actual conditions and needs.

[0082] like Figure 2 As shown, when the AC input positive terminal (L) is on the third side, the pins on the third side except the AC input positive terminal (L), the DC bus voltage output positive terminal (DC+), and the DC bus voltage output negative terminal (DC-) are all low-voltage pins.

[0083] On the fourth side of the plastic package, the DC positive terminal pin (P) is located between the pin of the power factor correction module 200 and the output pin of the power module 300 .

[0084] Figure 3 and Figure 4 The schematic diagram and package diagram of the frequency conversion control circuit of the second embodiment of the present invention are respectively shown; the second embodiment is similar to the first embodiment, and the same parts are not repeated here. The difference between the second embodiment and the first embodiment is that, in the second embodiment, the power factor correction unit adopts a single-path design, that is, the second embodiment does not have a transistor Q2 and a fast recovery diode D2; accordingly, see Figure 4 As shown, the number of base islands is also reduced accordingly. Specifically, the power diodes D9 and D10 are located on the first base island, the power diode D11 is located on the second base island, and the power diode D12 is located on the third base island. The second base island and the third base island are located on the right side of the first base island and are arranged side by side along the first side direction of the plastic package.

[0085] The anodes of the power diodes D9 and D10 are electrically connected to the first base island, which is connected to the pin DC+ by welding; the anode of the power diode D11 is electrically connected to the second base island, and the anode of the power diode D12 is electrically connected to the third base island.

[0086] The transistor Q1 is located on the fourth base island, the collector of the transistor Q1 is electrically connected to the fourth base island, and the fourth base island is connected to the pin PF1+ by welding.

[0087] The fast recovery diode D1, high-side transistors Q3-Q5, and high-side diodes D3-D5 are all located on the fifth base island. The cathode of the fast recovery diode D1, the collectors of the high-side transistors Q3-Q5, and the cathodes of the high-side diodes D3-D5 are all electrically connected to the fifth base island (by being mounted on the fifth base island). The fifth base island is connected to pin P by welding.

[0088] Low-side transistors Q6-Q8 are located on the sixth, seventh, and eighth base islands, respectively. Correspondingly, low-side diodes D6-D8 and their corresponding low-side transistors are located on the same base island. The sixth base island is connected to pin U via soldering, the seventh base island is connected to pin V via soldering, and the eighth base island is connected to pin W via soldering.

[0089] The power factor correction chip A1, the high-side driver chip A2 and the low-side driver chip A3 are all located on the ninth base island. The first to eighth base islands are arranged in sequence, for example, along the extension direction of the fourth side of the plastic package body. The second base island and the third base island are parallel, so that the rectifier unit 100 is located near the first side 11 of the plastic package body, the power unit 300 is located near the second side 12 of the plastic package body, and the power factor correction unit 200 is located between the rectifier unit 100 and the power unit 300.

[0090] Furthermore, the package structure includes a heat sink substrate 40. The first through eighth islands are located on this heat sink substrate 40, and the ninth island is located between the heat sink substrate 40 and the third side 13 of the plastic package. Heat sink substrate 40 is, for example, a copper-clad ceramic substrate. The first voltage output terminal (OUT1) and the second voltage output terminal (OUT2) of power factor correction chip A1 are short-circuited.

[0091] Figure 5 The third embodiment of the utility model shows a package diagram of the frequency conversion control circuit; compared with the first embodiment, the third embodiment replaces the high-side transistors Q3~Q5 and high-side diodes D3~D5 in the first embodiment with reverse-conducting transistors (RC-IGBT) Q3_1~Q5 _ 1. Replace the low-side transistors Q6~Q8 and low-side diodes D6~D8 in the first embodiment with reverse-conducting transistors (RC-IGBT) Q6_1~Q8 _ 1.

[0092] Figure 6 The fourth embodiment of the utility model shows a package diagram of the frequency conversion control circuit; compared with the second embodiment, the fourth embodiment replaces the high-side transistors Q3~Q5 and high-side diodes D3~D5 in the second embodiment with reverse-conducting transistors (RC-IGBT) Q3_1~Q5 _ 1. Replace the low-side transistors Q6~Q8 and low-side diodes D6~D8 in the first embodiment with reverse-conducting transistors (RC-IGBT) Q6_1~Q8 _ 1.

[0093] The packaging structure provided by this utility model integrates the rectifier unit, power factor correction unit, and power unit into a single plastic package, enabling the package structure to provide rectification, power factor correction, and inversion functions. This not only simplifies peripheral wiring and reduces costs, but also improves the usability and reliability of the package structure with a variable frequency control circuit.

[0094] Furthermore, the bootstrap diode is integrated into the high-side driver chip, and the protection circuit is integrated into the low-side driver chip to further reduce the overall volume; a heat dissipation substrate is added, and the transistors, high-side transistors and low-side transistors of the power factor correction unit are arranged on the heat dissipation substrate to further enhance the heat dissipation performance of the packaging structure.

[0095] Specifically, in this packaging structure, the power factor correction unit is located between the rectifier unit and the power unit. Among the pins of this packaging structure, the pin connected to the power factor correction unit is between the pin connected to the rectifier unit and the pin connected to the power unit. This layout facilitates the bonding wire connection between the power factor correction unit and the rectifier unit, and also facilitates the bonding wire connection between the power factor correction unit and the power unit for realizing motor control. Furthermore, the DC bus voltage output positive terminal (DC+) and the first current output terminal (PF1+) and the second current output terminal (PF2+) are respectively located on the upper and lower sides of the plastic package, which facilitates the routing and connection of the external inductor.

[0096] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0097] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A packaging structure, characterized in that: include: Rectifier unit; Power factor correction unit; A power unit, the power unit comprising a low-side driver chip, a high-side driver chip, a plurality of low-side transistors driven by the low-side driver chip, and a plurality of high-side transistors driven by the high-side driver chip; a lead frame having a plurality of pins; A plastic package body, the plastic package body covers the lead frame, the rectifier unit, the power factor correction unit and the power unit; the plastic package body includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, the first side and the second side extend in a width direction, and the third side and the fourth side extend in a length direction; the plurality of pins extend to the outside along the third side and the fourth side of the plastic package body; the power factor correction unit is located between the rectifier unit and the power unit.

2. The packaging structure according to claim 1, wherein: The rectifier unit is close to the first side of the plastic package body, and the power unit is close to the second side of the plastic package body.

3. The packaging structure according to claim 1, wherein: The rectifying unit has a plurality of power diodes.

4. The packaging structure according to claim 1, wherein: The high-side driver chip includes a plurality of bootstrap diodes.

5. The packaging structure according to claim 1, wherein: The low-side driver chip includes one or more of an over-temperature protection circuit, an over-current protection circuit, an under-voltage protection circuit and a fault output circuit.

6. The packaging structure according to claim 5, wherein: The over-temperature protection circuit, the over-current protection circuit and the fault output circuit share the same pin for outputting protection signals.

7. The packaging structure according to claim 3, wherein: The power factor correction unit includes a power factor correction chip, a first transistor, a second transistor, a first fast recovery diode and a second fast recovery diode; The first end of the first transistor is connected to the anode of the first fast recovery diode to lead to a first current input end, the second end of the first transistor is connected to a first current output end, and the control end of the first transistor is connected to the first voltage output end of the power factor correction chip; The first end of the second transistor is connected to the anode of the second fast recovery diode to lead out a second current input end, the second end of the second transistor is connected to the second current output end, and the control end of the second transistor is connected to the second voltage output end of the power factor correction chip; The cathodes of the first fast recovery diode and the second fast recovery diode are connected to the DC positive terminal.

8. The packaging structure according to claim 7, wherein: The ground terminal of the power factor correction chip, the ground terminal of the high-side driver chip and the ground terminal of the low-side driver chip are shared by a common ground.

9. The packaging structure according to claim 7, wherein: The first PFC signal input end of the power factor correction chip serves as the first signal input end of the package structure, and the second PFC signal input end of the power factor correction chip serves as the second signal input end of the package structure.

10. The packaging structure according to claim 7, wherein: The power supply terminal of the power factor correction chip is connected to the inverter topology power supply voltage input terminal of the packaging structure.

11. The packaging structure according to claim 3, wherein: The power factor correction unit includes a power factor correction chip, a first transistor and a first fast recovery diode; The first end of the first transistor is connected to the anode of the first fast recovery diode to lead to a first current output end, the second end of the first transistor is connected to the first current input end, and the control end of the first transistor is connected to the first output end of the power factor correction chip; The first fast recovery diode is connected to the DC positive terminal.

12. The packaging structure according to claim 11, wherein: The first PFC signal input end of the power factor correction chip serves as the first signal input end of the packaging structure.

13. The packaging structure according to claim 7 or 11, characterized in that: A first inductor is connected between the DC bus voltage output positive terminal and the first current input terminal of the packaging structure outside the plastic package.

14. The packaging structure according to claim 7 or 11, characterized in that: A second inductor is connected between the DC bus voltage output positive terminal and the second current input terminal of the packaging structure outside the plastic package.

15. The packaging structure according to claim 7, wherein: A first inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the first current input terminal of the packaging structure; a second inductor is connected outside the plastic package between the DC bus voltage output positive terminal and the second current input terminal of the packaging structure.

16. The packaging structure according to claim 7, wherein: The system further comprises a plurality of base islands, the plurality of base islands comprising a first base island, a second base island, a third base island, a fourth base island, a fifth base island, a sixth base island, a seventh base island, an eighth base island, and a ninth base island arranged in parallel in the length direction, wherein the third base island is arranged in parallel with the second base island; The plurality of power diodes include a first power diode, a second power diode, a third power diode, and a fourth power diode, wherein the first power diode and the second power diode are located on the first base island, and the third power diode and the fourth power diode are located on the second base island and the third base island, respectively; The first transistor is located on the fourth base island, and the second transistor is located on the fifth base island; The plurality of high-side transistors include three high-side transistors; the first fast recovery diode, the second fast recovery diode and the three high-side transistors are located on the sixth base island; The plurality of low-side transistors include three low-side transistors; the three low-side transistors are mounted on the seventh base island, the eighth base island, and the ninth base island, respectively.

17. The packaging structure according to claim 16, wherein: The power unit further includes a plurality of low-side diodes and a plurality of high-side diodes, wherein the plurality of low-side diodes correspond to the plurality of low-side transistors, and the plurality of high-side diodes correspond to the plurality of high-side transistors.

18. The packaging structure according to claim 17, wherein: The plurality of high-side diodes include three high-side diodes, the three high-side diodes are respectively connected to the three high-side transistors, and the three high-side diodes, the three high-side transistors, the first fast recovery diode and the second fast recovery diode are located on the sixth base island; The plurality of low-side diodes include three low-side diodes, the three low-side diodes are respectively connected to the three low-side transistors, and the three low-side diodes and the corresponding low-side transistors are respectively located on the same base island.

19. The packaging structure according to claim 16, wherein: The plurality of base islands further include a tenth base island, and the power factor correction chip, the high-side driver chip, and the low-side driver chip are sequentially mounted on the tenth base island.

20. The packaging structure according to claim 19, wherein: The first to ninth base islands are located on a heat dissipation substrate, and the tenth base island is located between the heat dissipation substrate and the third side of the plastic package body.

21. The packaging structure according to claim 1, wherein: The transistors in the power factor correction unit and the transistors in the power unit include any one of a MOS device, an RC-IGBT device, an IGBT device, and an IGBT device with a fast recovery diode sealed therein.

22. The packaging structure according to claim 11, wherein: The system further comprises a plurality of base islands, the plurality of base islands comprising a first base island, a second base island, a third base island, a fourth base island, a fifth base island, a sixth base island, a seventh base island, and an eighth base island arranged in parallel in the length direction, wherein the third base island is arranged in parallel with the second base island; The plurality of power diodes include a first power diode, a second power diode, a third power diode, and a fourth power diode, wherein the first power diode and the second power diode are located on the first base island, and the third power diode and the fourth power diode are located on the second base island and the third base island, respectively; The first transistor is located on the fourth base island; The plurality of high-side transistors include three high-side transistors; the first fast recovery diode and the three high-side transistors are located on the fifth base island; The plurality of low-side transistors include three low-side transistors; the three low-side transistors are mounted on the sixth base island, the seventh base island, and the eighth base island, respectively.

23. The packaging structure according to claim 22, wherein: The power unit further includes a plurality of low-side diodes and a plurality of high-side diodes, wherein the plurality of low-side diodes correspond to the plurality of low-side transistors, and the plurality of high-side diodes correspond to the plurality of high-side transistors.

24. The packaging structure according to claim 23, wherein: The plurality of high-side diodes include three high-side diodes, which are respectively connected to the three high-side transistors, and the three high-side diodes, the three high-side transistors and the first fast recovery diode are located on the sixth base island; the plurality of low-side diodes include three low-side diodes, which are respectively connected to the three low-side transistors, and the three low-side diodes and their corresponding low-side transistors are respectively located on the same base island.

25. The packaging structure according to claim 22, wherein: The plurality of base islands further include a ninth base island, and the power factor correction chip, the high-side driver chip, and the low-side driver chip are sequentially mounted on the ninth base island.

26. The packaging structure according to claim 25, characterized in that The first to eighth base islands are located on a heat dissipation substrate, and the ninth base island is located between the heat dissipation substrate and the third side of the plastic package body.

27. The packaging structure according to claim 1, wherein: The packaging structure is a plug-in packaging.

28. The packaging structure according to claim 16 or 22, characterized in that: The first base island is connected to the anode of the first power diode and the anode of the second power diode; the second base island is connected to the anode of the third power diode, and the third base island is connected to the anode of the fourth power diode.

29. The packaging structure according to claim 7, wherein: The AC input negative terminal, the first current output terminal, the second current output terminal, the first current input terminal, the second current input terminal, the DC positive terminal, the first phase output terminal, the second phase output terminal, the third phase output terminal, the first phase DC power supply negative terminal, the second phase DC power supply negative terminal and the third phase DC power supply negative terminal are located on the fourth side of the plastic package body, and the fourth side of the plastic package body are all high-voltage pins.

30. The packaging structure according to claim 11, wherein: The AC input negative terminal, the first current output terminal, the first current input terminal, the DC positive terminal, the first phase output terminal, the second phase output terminal, the third phase output terminal, the first phase DC power supply negative terminal, the second phase DC power supply negative terminal and the third phase DC power supply negative terminal are located on the fourth side of the plastic package body, and the fourth side of the plastic package body are all high-voltage pins.

31. The packaging structure according to claim 7 or 11, characterized in that: The DC bus voltage output positive terminal, the DC bus voltage output negative terminal and the pins of the power factor correction chip, the low-side driver chip and the high-side driver chip are all located on the third side of the plastic package body, and the DC bus voltage output positive terminal and the DC bus voltage output negative terminal are high-voltage pins.

32. The packaging structure according to claim 7 or 11, characterized in that: The AC input positive terminal is located on the third side or the fourth side of the plastic package body.

33. The packaging structure according to claim 32, wherein: When the AC input positive terminal is on the third side, the pins other than the AC input positive terminal, the DC bus voltage output positive terminal, and the DC bus voltage output negative terminal are low-voltage pins.

34. The packaging structure according to claim 32, wherein: When the AC input positive terminal is on the fourth side, the pins except the DC bus voltage output positive terminal and the DC bus voltage output negative terminal are low-voltage pins.

35. The packaging structure according to claim 7 or 11, characterized in that: The DC positive terminal pin is located between the pin of the power factor correction unit and the output pin of the power unit.

36. The packaging structure according to claim 1, wherein: Among the pins of the packaging structure, the pin connected to the power factor correction unit is between the pin connected to the rectifier unit and the pin connected to the power unit.

37. The packaging structure according to claim 20, wherein: The DC bus voltage output positive terminal is welded to the first base island; The first current input terminal is connected to the fourth base island by welding; The second current input terminal is connected to the fifth base island by welding; The DC positive terminal is welded to the sixth base island; The first phase output end is welded to the seventh base island; The second phase output end is connected to the eighth base island by welding; The third phase output terminal is connected to the ninth base island by welding.

38. The packaging structure according to claim 22, wherein: The DC bus voltage output positive terminal is welded to the first base island; The first current input terminal is connected to the fourth base island by welding; The DC positive terminal is welded to the fifth base island; The first phase output terminal is connected to the sixth base island by welding; The second phase output end is connected to the seventh base island by welding; The third phase output terminal is connected to the eighth base island by welding.

39. The packaging structure according to claim 31, wherein: The DC bus voltage output positive terminal and the first current input terminal and the second current input terminal are respectively located on different sides of the plastic package body.

Images