Beidou handheld analog terminal circuit

Abstract

The utility model discloses a Beidou hand-held analog terminal circuit, comprising a full A64 chip, a 19V power supply circuit connected with an RGB display circuit, a 5V power supply circuit which is used for supplying power to the RGB display circuit and is respectively connected with the full A64 chip, an HDMI circuit, a USB communication circuit and a network port communication circuit, and a 5V power supply circuit which is used for supplying power to the HDMI circuit, the USB communication circuit and the network port communication circuit of the full A64 chip. The 3.3 V power supply circuit is connected with the TF card storage circuit and is used for supplying power to the TF card storage circuit; the HDMI circuit is respectively connected with the full A64 chip and the 5V power supply circuit and is used for transmitting a video signal; the network port communication circuit is respectively connected with the full A64 chip and the 5V power supply circuit and is used for communication between the full A64 chip and an upper computer; and the USB communication circuit is respectively connected with the full A64 chip and the 5V power supply circuit and is used for transmission between the host and other USB equipment. According to the utility model, the required voltage is low during working, the power consumption is reduced, the required components are few, and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to a Beidou handheld terminal circuit, in particular to a Beidou handheld analog terminal circuit. Background Art

[0002] With the widespread adoption of the Beidou satellite navigation system, the demand for training and testing related personnel is growing. Traditional training methods often rely on real Beidou handheld terminals, which has led to the emergence of Beidou handheld simulation terminals. However, existing Beidou handheld simulation terminals have high power consumption, which directly affects the terminal's standby time and usage time. This is especially true for mobile terminals that rely primarily on battery power, limiting the length of time users can use the device without a power source. Utility Model Content

[0003] The utility model aims to provide a Beidou handheld analog terminal circuit to solve the problem of high power consumption of the existing Beidou handheld analog terminal.

[0004] The technical solution of this utility model is as follows:

[0005] The Allwinner A64 chip is connected to the RGB display circuit, network port communication circuit, USB communication circuit, TF card storage circuit, HDMI circuit and 5V power supply circuit to generate analog signals;

[0006] A 19V power supply circuit is connected to the RGB display circuit and is used to provide a 19V operating voltage to the RGB display circuit;

[0007] The 5V power supply circuit is connected to the Allwinner A64 chip, the HDMI circuit, the USB communication circuit, and the network port communication circuit, respectively, and is used to provide a 5V operating voltage to the Allwinner A64 chip, the HDMI circuit, the USB communication circuit, and the network port communication circuit;

[0008] 3.3V power supply circuit, connected to the TF card storage circuit, used to provide 3.3V operating voltage to the TF card storage circuit;

[0009] The HDMI circuit is connected to the Allwinner A64 chip and the 5V power supply circuit respectively, and is used to transmit video signals;

[0010] The network port communication circuit is connected to the Allwinner A64 chip and the 5V power supply circuit respectively, and is used to connect the USB interface and the Ethernet interface; and

[0011] The USB communication circuit is connected to the Allwinner A64 chip and the 5V power supply circuit respectively, and is used for signal transmission with other USB devices.

[0012] Furthermore, the structure of the 19V power supply circuit is that the VIN terminal of the boost chip U6 is connected to two inputs, one is grounded through the capacitor C11, one is connected to the power supply, and the other is connected to the display circuit after passing through the inductor L3 and the diode D3. The SW terminal of the boost chip U6 is connected to the display circuit through the diode D3; the FB terminal of the boost chip U6 has two outputs, one is grounded, and the other is connected to the display circuit through the capacitor C9, and a voltage divider circuit composed of a resistor R9 and a resistor R12 is connected in parallel at both ends of the capacitor C9; the EN terminal of the boost chip U6 is connected to the VIN terminal of the boost chip U6.

[0013] Furthermore, the structure of the 5V power supply circuit is that the SW end of the boost chip U2 is connected to two inputs after passing through the inductor L2, one of which is connected to the power supply VBAT-D through the field effect transistor P1, and the other is connected to the power supply VCC VBAT; the CBST end of the boost chip U2 is connected to the SW end of the boost chip U2 through the capacitor C6, and the VIN end of the boost chip U2 is connected to the power supply VCC VBAT; one end of the resistor R4 is connected to the power supply, and the other end is connected to the G pole of the field effect transistor P1; the resistor R4 is connected to the CSI-RST-F end of the Allwinner A64 chip through the diode D1, the diode D1 is connected to the D pole of the field effect transistor M1, the S pole of the field effect transistor M1 is grounded, the G pole of the field effect transistor M1 is connected to the CSI SCK end of the Allwinner A64 chip, one end of the resistor R6 is connected to the G pole of the field effect transistor M1, and the other end is grounded; the EN end of the boost chip U2 is connected to two inputs, one of which is connected to the power supply VCC VBAT, two paths are grounded through capacitor C7, and capacitor C61 is connected in parallel at both ends of capacitor C7; the VOUT terminal of the boost chip U2 is connected to two outputs, one is grounded through the voltage divider circuit composed of resistors R3 and R5, and the other is connected to the 5V voltage output terminal; capacitor C4 is connected in parallel at both ends of the voltage divider circuit composed of resistors R3 and R5, and capacitor C5 is connected in parallel at both ends of capacitor C4; the GND terminal of the boost chip U2 is connected to two inputs, one is grounded, and the other is connected to the 5V voltage output terminal through LED diode D10 and resistor R55; the FB terminal of the boost chip U2 is connected to the voltage divider node of the voltage divider circuit composed of resistors R3 and R5.

[0014] Furthermore, the structure of the 3.3V power supply circuit is as follows: the SW terminal of the boost chip U1 is connected to the power supply VCCVBAT via the inductor L2, and the CBST terminal of the boost chip U1 is connected to the SW terminal of the boost chip U1 via the capacitor C3; the VIN terminal and the EN terminal of the boost chip U1 are both connected to the power supply VCC VBAT; the VOUT terminal of the boost chip U12 is connected to two outputs, one is grounded through a voltage divider circuit composed of resistors R1 and R2, and the other is connected to the TF card storage circuit; a capacitor C1 is connected in parallel at both ends of the voltage divider circuit composed of resistors R1 and R2, and a capacitor C2 is connected in parallel at both ends of the capacitor C1; the GND terminal of the boost chip U1 is connected to two inputs, one is grounded, and the other is connected to the TF card storage circuit through an LED diode D5 and a resistor R54; the FB terminal of the boost chip U1 is connected to the voltage divider node of the voltage divider circuit composed of resistors R1 and R2.

[0015] Furthermore, the structure of the HDMI circuit is that the HDMI interface U5 is connected to three electrostatic protection devices respectively, the +5V end of the HDMI interface U5 is connected to the power supply VCC HDMI, the power supply VCC HDMI is connected to the 5V power supply through the diode D2, the power supply VCC HDMI is connected to the cathode of the diode D2, and the 5V power supply is connected to the anode of the diode D2.

[0016] Furthermore, the structure of the network port communication circuit is that the USB to Ethernet control chip U12 is connected to the filter transformer J11 and the crystal oscillator X2 respectively, and the RREF terminal, RSET_BG terminal, and EXTWAKEUP_N terminal of the USB to Ethernet control chip U12 are all grounded through a resistor; the RESET_N terminal of the USB to Ethernet control chip U12 is connected to two inputs, one is connected to the first 3.3V power supply through the resistor R44, and the other is grounded through the capacitor C30; the VCC3R3 terminal of the USB to Ethernet control chip U12 is connected to two inputs, one is connected to the second 3.3V power supply through the resistor R50, one end of the capacitor C44 is respectively connected to the resistor R50 and the second 3.3V power supply, and the other end is grounded, a capacitor C45 is connected in parallel at both ends of the capacitor C44, and the two are connected to the third 3.3V power supply, and one end of the capacitor C52 is respectively connected to the resistor R50 and the third 3.3V power supply. The two ends of the capacitor C48 are connected in parallel with each other, and the other end is grounded. Capacitor C51 is connected in parallel at both ends of the capacitor C52; the V18F end of the USB to Ethernet control chip U12 is connected to the second 1.8V power supply through the first 1.8V power supply and the resistor R51, and the other end is grounded. Capacitor C46 is connected in parallel at both ends of the capacitor C47, one end of the capacitor C48 is connected to the second 1.8V power supply and the resistor R51, and the other end is grounded, and capacitor C49 is connected in parallel at both ends of the capacitor C48; the VCC3IO ends of the USB to Ethernet control chip U12 are all connected to the fourth 3.3V power supply; the first 1.8V power supply is respectively connected to capacitor C34, capacitor C35, capacitor C36 and capacitor C37 and then grounded to form a parallel circuit, and the second 1.8V power supply is respectively connected to capacitor C38, capacitor C39 and capacitor C40 and then grounded to form a parallel circuit.

[0017] Furthermore, the structure of the USB communication circuit is that the USB chip U11 is connected to the host and the crystal oscillator X1 respectively, the RREF terminal of the USB chip U11 is grounded via a resistor R20, the REST# terminal of the USB chip U11 is connected to two inputs, one is connected to a 5V power supply through a resistor R27, and the other is grounded through a capacitor C15, and resistor R30 is connected to both ends of the capacitor R30; the V33 terminal of the USB chip U11 is connected to the voltage stabilizing circuit via a resistor R21, the PGANG terminal of the USB chip U11 is connected to the voltage stabilizing circuit via a resistor R26, and the DVDD terminal of the USB chip U11 is connected to the voltage stabilizing circuit; the OVCUR1# terminal of the USB chip U11 is connected to two inputs, one is connected to a 5V power supply through a resistor R24, and the other is grounded through a resistor R25.

[0018] Furthermore, the structure of the voltage stabilizing circuit is that one end of the capacitor C20 is connected to the resistor R21, and the other end is grounded, a capacitor C21 is connected in parallel at both ends of the capacitor C21, a capacitor C22 is connected in parallel at both ends of the capacitor C21, a capacitor C23 is connected in parallel at both ends of the capacitor C22, and a capacitor C24 is connected in parallel at both ends of the capacitor C23.

[0019] Furthermore, the VBUS terminal of each host has two inputs, one is connected to the 5V power supply, and the other is grounded through a capacitor; the D- port of each host is connected to the DM port of the USB chip, and the D+ port of each host is connected to the DP port of the USB chip.

[0020] Furthermore, the XIN terminal of the crystal oscillator X1 is connected to two inputs, one is connected to the X1 terminal of the USB chip, and the other is grounded through capacitor C18; the XOUT terminal of the crystal oscillator X1 is connected to two outputs, one is connected to the X2 terminal of the USB chip, and the other is grounded through capacitor C26; the GND terminals of the crystal oscillator X1 are all grounded.

[0021] The HDMI circuit, USB communication circuit, network port communication circuit and Allwinner A64 chip in the utility model have low power consumption and only require 5V power supply, so the power consumption is low. The 19V power supply circuit uses the MT3608 chip and selects the appropriate sampling resistors R9 and R10. A 19V voltage output can be obtained using a 3.8V power input, thereby reducing power consumption.

[0022] This utility model utilizes the TPS61230A chip to design 5V and 3.3V power supply circuits, using fewer external components and reducing the cost of the utility model. Connecting the EN terminal to the VIN terminal maintains the circuit voltage output even after being disabled. Three TPD4E05U06 electrostatic protection devices are used in the HDMI circuit, but they do not protect the circuit stability. The network port communication circuit uses parallel capacitors to stabilize the circuit voltage, and the USB communication circuit uses the GL850G chip, which has low power consumption. The USB communication circuit uses fewer external components, reducing the cost of the utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit structure diagram of the utility model.

[0024] Figure 2 This is the circuit diagram of the 19V power supply circuit.

[0025] Figure 3 This is the circuit diagram of a 5V power supply circuit and a 3.3V power supply circuit.

[0026] Figure 4 This is a circuit diagram of the HDMI circuit.

[0027] Figure 5This is the circuit diagram of the USB to Ethernet control chip.

[0028] Figure 6 This is the circuit diagram of filter transformer J11.

[0029] Figure 7 This is a circuit diagram of the USB communication circuit. DETAILED DESCRIPTION

[0030] The utility model is further described below.

[0031] like Figure 1 As shown in the figure, the Beidou handheld simulation terminal circuit includes the Allwinner A64 chip, an RGB display circuit, a 5V power supply circuit, a USB communication circuit, an Ethernet communication circuit and a TF card storage circuit connected to the Allwinner A64 chip, a 19V power supply circuit connected to the RGB display circuit, and a 3.3V power supply circuit connected to the TF card storage circuit.

[0032] The RGB display circuit is the touch screen circuit included in the 47p interface, which matches the Allwinner A64 chip, and the TF card storage circuit is an existing circuit.

[0033] like Figure 2 As shown, the 19V power supply circuit is controlled by the boost chip U6, model MT3608. The structure of the 19V power supply circuit is as follows: the VIN terminal of the boost chip U6 is connected to two inputs, one of which is grounded through capacitor C11, and one is connected to the power supply VCC VBAT. The other is connected to the display circuit after passing through inductor L3 and diode D3. The SW terminal of the boost chip U6 is connected to the RGB display circuit through diode D3; the FB terminal of the boost chip U6 has two outputs, one of which is grounded and the other is connected to the display circuit through capacitor C9. The two ends of capacitor C9 are connected in parallel with a voltage divider circuit composed of resistors R9 and R12; the EN terminal of the boost chip U6 is connected to the VIN terminal of the boost chip U6.

[0034] Resistor R9 and resistor R12 are sampling resistors. In the present invention, the EN terminal of the boost chip U6 is connected to the VIN terminal. The EN terminal of the boost chip U6 is an enable pin. After the EN terminal of the boost chip U6 is enabled, it can boost the voltage. After being disabled, it cannot be completely shut down and the voltage output of the boost chip U6 will be maintained.

[0035] Among them, capacitor C9 and capacitor C11 are both ceramic capacitors with a capacitance of 22μF, the withstand voltage value of capacitor C9 is 10V, the capacitance is 22μF, the withstand voltage value is 50V, the model of diode D3 is IN5819, and the inductance of inductor L3 is 4.7μH.

[0036] The RGB display circuit in the present invention requires a voltage of 19V, and the resistance values ​​of resistors R9 and R10 are selected according to formula (1).

[0037] Formula (1) is:

[0038]

[0039] Among them, V OUT is the output voltage of the 19V power supply circuit, V REF is the internal voltage of the boost chip U6, R9 = 10k (1%), R12 = 310K (1%).

[0040] According to formula (1), the theoretical output voltage is about 19.2V, and the actual circuit output voltage is about 19V, which is consistent with the operating voltage of the RGB display circuit.

[0041] like Figure 3 As shown, the 5V power supply circuit provides 5V voltage to the Allwinner A64 chip, HDMI circuit, USB communication circuit and network port communication circuit, including a boost chip U2, model TPS61230A, capacitor C6, inductor L2, capacitor C7, capacitor C61, resistor R3, resistor R5, capacitor C4, capacitor C5, resistor R55 and diode D10 connected to the boost chip U2 respectively, field effect transistor P1 connected to the inductor L2, model AO3400, resistor R4 connected to the field effect transistor P1, field effect transistor M1 connected to the resistor R4, model AO3401, and diode D1 and resistor R6 connected to the field effect transistor M1 respectively.

[0042] The structure of the 5V power supply circuit is as follows: the SW end of the boost chip U2 is connected to two inputs after passing through the inductor L2. One input is connected to the power supply VBAT_D through the field effect transistor P1, the S pole of the field effect transistor P1 is connected to the power supply VBAT_D, and the D pole of the field effect transistor P1 is connected to the inductor L2. The two inputs are connected to the power supply VCC VBAT; the CBST end of the boost chip U2 is connected to the SW end of the boost chip U2 through the capacitor C6, and the VIN end of the boost chip U2 is connected to the power supply VCC VBAT; one end of the resistor R4 is connected to the power supply VBAT_D, and the other end is connected to the G pole of the field effect transistor P1. The EN end of the boost chip U2 is connected to two inputs, one of which is connected to the power supply VCC VBAT, two paths are grounded through capacitor C7, and capacitor C61 is connected in parallel at both ends of capacitor C7; the VOUT terminal of the boost chip U2 is connected to two outputs, one is grounded through the voltage divider circuit composed of resistors R3 and R5, and the other is connected to the 5V voltage output terminal; capacitor C4 is connected in parallel at both ends of the voltage divider circuit composed of resistors R3 and R5, and capacitor C5 is connected in parallel at both ends of capacitor C4; the GND terminal of the boost chip U2 is connected to two inputs, one is grounded, and the other is connected to the 5V voltage output terminal through LED diode D10 and resistor R55; the FB terminal of the boost chip U2 is connected to the voltage divider node of the voltage divider circuit composed of resistors R3 and R5.

[0043] Among them, the power supply VBAT_D and the power supply VCC VBAT are both 3.8V.

[0044] The field effect transistor M1 and the field effect transistor P1 are used to protect the circuit. After the current of other circuits stabilizes, the field effect transistor M1 and the field effect transistor P1 are turned on.

[0045] The 3.3V power supply circuit provides a 3.3V voltage to the TF card storage module. Its structure is similar to that of the 5V power supply circuit. It includes a boost chip U1 (TPS61230A), and capacitor C3, inductor L1, resistor R1, resistor R2, capacitor C1, capacitor C2, resistor R54, and diode D5 connected to boost chip U1.

[0046] The structure of the 3.3V power supply circuit is as follows: the SW terminal of the boost chip U1 is connected to the power supply VCC VBAT via the inductor L2, and the CBST terminal of the boost chip U1 is connected to the SW terminal of the boost chip U1 via the capacitor C3; the VIN terminal and EN terminal of the boost chip U1 are both connected to the power supply VCCVBAT; the VOUT terminal of the boost chip U12 is connected to two outputs, one is grounded through a voltage divider circuit composed of resistors R1 and R2, and the other is connected to the TF card storage circuit; capacitor C1 is connected in parallel at both ends of the voltage divider circuit composed of resistors R1 and R2, and capacitor C2 is connected in parallel at both ends of capacitor C1; the GND terminal of the boost chip U1 is connected to two inputs, one is grounded, and the other is connected to the TF card storage circuit through the LED diode D5 and resistor R54; the FB terminal of the boost chip U1 is connected to the voltage divider node of the voltage divider circuit composed of resistors R1 and R2.

[0047] The parameters of the components in the 3.3V power supply circuit and the 5V power supply circuit are similar. The inductance of inductor L1 and inductor L2 is both 1μH, the capacitance of capacitor C3 and capacitor C6 is both 10nF, and the withstand voltage value is both 10V. The capacitance of capacitors C1, C2, C4, and capacitor C5 is all 22μF, and the withstand voltage value is all 10V. The resistance value of resistor R4 and resistor R6 is both 10K. The model of diode D1 is IN5819. LED diodes D5 and LED diodes D10 serve as indicators for the normal operation of chip TPS61230A.

[0048] The resistance values ​​of resistors R1, R2, R3, and R5 are determined according to formula (2):

[0049]

[0050] Among them, V OUT is the output voltage, V FB It is the internal voltage of the boost chip U1 or the boost chip U2.

[0051] When R1 = 176k (1%), R2 = 100K (1%), the output voltage is 3.3V; when R3 = 316k (1%), R5 = 100K (1%), the output voltage is 5V.

[0052] According to formula (2), the theoretical output voltage of the 5V power supply circuit is about 5.1V, and the actual circuit output voltage is about 5V, which is consistent with the operating voltage of the Allwinner A64 chip, HDMI circuit, USB communication circuit, and network port communication circuit; the theoretical output voltage of the 3.3V power supply circuit is about 3.32V, and the actual circuit output voltage is about 3.3V, which is consistent with the operating voltage of the 3.3V TF card storage module.

[0053] When the TPS61230A's input voltage is 2.5V, it can output a 5V voltage and provide up to 2.4A of output current. Thanks to its low RDS ON switch, the TPS61230A achieves a power conversion efficiency of up to 96%, minimizing thermal stress in the compact package. Under light load conditions, the TPS61230A does not operate and automatically enters PFM mode, maximizing efficiency at the lowest quiescent current. During shutdown, the load can be completely disconnected from the input by pulling the EN pin to a logic low, while input current consumption is reduced to less than 1.0μA.

[0054] The TPS61230A is packaged in a 2.00 mm × 2.00 mm × 0.9 mm VQFN package and requires minimal external components, thereby reducing the cost of the 3.3 V power supply circuit and the 5 V power supply circuit in the utility model.

[0055] like Figure 4 As shown, the HDMI circuit includes an HDMI interface U5, model HDMI_TYPE_C, and three electrostatic protection devices, model TPD4E05U06, connected to the HDMI interface U5, a diode D2, a resistor R14, a resistor R15, a resistor R17 and a resistor R19.

[0056] The structure of the HDMI circuit is that the HTX2P terminal of the Allwinner A64 chip is connected to the IN1 terminal of the electrostatic protection device U3, the OUT1 terminal of the electrostatic protection device U3 is connected to the HTX2P terminal of the HDMI interface U5, the HTX2N terminal of the Allwinner A64 chip is connected to the IN2 terminal of the electrostatic protection device U3, the OUT2 terminal of the electrostatic protection device U3 is connected to the HTX2N terminal of the HDMI interface U5, the HTX1P terminal of the Allwinner A64 chip is connected to the IN3 terminal of the electrostatic protection device U3, the OUT3 terminal of the electrostatic protection device U3 is connected to the HTX1P terminal of the HDMI interface U5, and the HTX1N terminal of the Allwinner A64 chip Connect the IN4 end of the electrostatic protection device U3, and the OUT4 end of the electrostatic protection device U3 is connected to the HTX1N end of the HDMI interface U5; the HTX0P end of the Allwinner A64 chip is connected to the IN1 end of the electrostatic protection device U4, and the OUT1 end of the electrostatic protection device U4 is connected to the HTX0P end of the HDMI interface U5, the HTX0N end of the Allwinner A64 chip is connected to the IN2 end of the electrostatic protection device U4, and the OUT2 end of the electrostatic protection device U4 is connected to the HTX0N end of the HDMI interface U5, the HTXCP end of the Allwinner A64 chip is connected to the IN3 end of the electrostatic protection device U4, and the OUT T3 is connected to the HTXCP end of HDMI interface U5, HTXCN of Allwinner A64 chip is connected to IN4 of electrostatic protection device U4, OUT4 of electrostatic protection device U4 is connected to HTXCN of HDMI interface U5; HCEC of Allwinner A64 chip is connected to IN1 of electrostatic protection device U7, OUT1 of electrostatic protection device U7 is connected to HCEC of HDMI interface U5, HSCL of Allwinner A64 chip is connected to IN2 of electrostatic protection device U7, HSCL of HDMI interface U5 has two inputs, one is connected to OUT2 of electrostatic protection device U7, and the other is connected to OUT3 of electrostatic protection device U7. One path is connected to a 5V power supply through resistor R14, the HSDA terminal of the Allwinner A64 chip is connected to the IN3 terminal of the electrostatic protection device U7, the HSDA terminal of the HDMI interface U5 has two inputs, one is connected to the OUT3 terminal of the electrostatic protection device U7, and the other is connected to a 5V power supply through resistor R19, the HHPD terminal of the Allwinner A64 chip is connected to the IN4 terminal of the electrostatic protection device U7, the HHPD terminal of the HDMI interface U5 is divided into two paths after passing through resistor R15, one is connected to the OUT4 terminal of the electrostatic protection device U7, and the other is grounded after passing through resistor R17; the +5V terminal of the HDMI interface U5 is connected to the power supply VCC HDMI, the power supply VCC HDMI is connected to the cathode of the diode D2, and the 5V power supply is connected to the anode of the diode D2.

[0057] The AGND, SHIELD1, SHIELD2, SHIELD3 and SHIELD4 terminals of the HDMI interface U5, the GND1 and GND2 terminals of the electrostatic protection device U3, the GND1 and GND2 terminals of the electrostatic protection device U4, and the GND1 and GND2 terminals of the electrostatic protection device U7 are all grounded.

[0058] The HDMI circuit uses three TPD4E05U06 electrostatic protection devices to maintain circuit stability. The TPD4E05U06DQAR is an ESD protection device for ultra-high-speed (up to 6Gbps) interfaces. It is an electrostatic discharge (ESD) protection diode based on a unidirectional transient voltage suppressor (TVS) with ultra-low capacitance, making it ideal for protecting any high-speed signal pin.

[0059] like Figure 5 and Figure 6 As shown, the network port communication circuit is used to connect the USB interface and the Ethernet interface, including a USB to Ethernet control chip U12, model AX88772C or AX88772B, and a filter transformer J11 and a crystal oscillator X2 connected to the USB to Ethernet control chip U12.

[0060] The structure of the network port communication circuit is as follows: the V_BUS terminal of the USB to Ethernet control chip U12 is connected to the 5V power supply through the resistor R29, the RREF terminal is grounded through the resistor R34, the RSET_BG terminal is grounded through the resistor R41, and the EXTWAKEUP_N terminal is grounded through the resistor R42; the RESET_N terminal is connected to two inputs, one is connected to the first 3.3V power supply through the resistor R44, and the other is grounded through the capacitor C30; the VCC3R3 terminal is connected to two inputs, one is connected to the second 3 .3V power supply, one end of capacitor C44 is connected to resistor R50 and the second 3.3V power supply respectively, and the other end is grounded, capacitor C45 is connected in parallel at both ends of capacitor C44, and the two paths are connected to the third 3.3V power supply, one end of capacitor C52 is connected to resistor R50 and the third 3.3V power supply respectively, and the other end is grounded, capacitor C51 is connected in parallel at both ends of capacitor C52; V18F end is connected to the second 1.8V power supply through the first 1.8V power supply and resistor R51, and one end of capacitor C47 is connected to the third 3.3V power supply respectively. A 1.8V power supply and resistor R51, the other end of which is grounded, capacitor C46 is connected in parallel to both ends of capacitor C47, one end of capacitor C48 is connected to the second 1.8V power supply and resistor R50, and the other end is grounded, capacitor C49 is connected in parallel to both ends of capacitor C48, VCC3A3, VCC33A_PLL, VCC33A_H and VCC3IO are all connected to the fourth 3.3V power supply, VCC18A and VCC18A_PLL are all connected to the first 1.8 V power supply, VCCK end are connected to the second 1.8V power supply; the first 1.8V power supply is respectively connected to capacitor C34, capacitor C35, capacitor C36 and capacitor C37 and then grounded to form a parallel circuit, the second 1.8V power supply is respectively connected to capacitor C38, capacitor C39 and capacitor C40 and then grounded to form a parallel circuit; the DM end of the USB to Ethernet control chip U12 is connected to the DM4 end of the USB chip, and the DM end of the USB to Ethernet control chip U12 is connected to the DP end of the USB chip.

[0061] The fourth 3.3V power supply is grounded via a capacitor C41 , and a capacitor C42 is connected in parallel across both ends of the capacitor C41 .

[0062] The TD+ end of the filter transformer J11 is divided into two inputs, one is connected to the TXOP end of the USB to Ethernet control chip U12, and the other is grounded through resistor R37 and capacitor C28; the TD- end is divided into two inputs, one is connected to the TXON end of the USB to Ethernet control chip U12, and the other is grounded through resistor R38 and capacitor C28; the RX+ end is divided into two inputs, one is connected to the RXIP end of the USB to Ethernet control chip U12, and the other is grounded through resistor R39 and capacitor C29; the RX- end is divided into two inputs, one is connected to the RXIN end of the USB to Ethernet control chip U12, and the other is grounded through resistor R40 and Capacitor C29 is grounded; both CT2 and CT1 are grounded via the fifth 3.3V power supply and capacitor C16; both LEDG+ and LEDY+ are connected to the sixth 3.3V power supply; LEDG- is divided into two paths after passing through resistor R33, one path is connected to the MFA_2 / RMII_N terminal of the USB-to-Ethernet control chip U12, and the other path is connected to the sixth 3.3V power supply via resistor R32; LEDY- is divided into two paths after passing through resistor R35, one path is connected to the MFA_3 / PHY_N terminal of the USB-to-Ethernet control chip U12, and the other path is connected to the sixth 3.3V power supply via resistor R31; CHS_GND is grounded via capacitor C27.

[0063] The XIN end of the crystal oscillator X2 is divided into two inputs, one is connected to the XTL25N end of the USB to Ethernet control chip U12, and the other is grounded through capacitor C43; the XIN end of the crystal oscillator X2 is divided into two outputs, one is connected to the XTL25P end of the USB to Ethernet control chip U12, and the other is grounded through capacitor C50.

[0064] The AX88772C is a USB-to-Ethernet controller chip that supports Microsoft AOAC (Always On Always Connected). It can add low-cost, small-package, high-performance, highly integrated, plug-and-play 100M Ethernet connectivity to various applications, requiring only a single 25MHz clock for normal operation.

[0065] like Figure 7 As shown, the USB communication circuit is used for signal transmission with other USB devices, including a USB chip U11, model GL850G, and a host J10 connected to the USB chip U11, a host J12, a crystal oscillator X1, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R30, a capacitor C15, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23 and a capacitor C24, a capacitor C13 connected to the host J10, a capacitor C17 connected to the host J12, and a capacitor C18 and a capacitor C26 respectively connected to the crystal oscillator X1.

[0066] The structure of the USB communication circuit is that capacitor C21 is connected in parallel at both ends of capacitor C20, one end of the parallel connection is grounded, and the other end is the V33_HUB end, capacitor C22 is connected in parallel at both ends of capacitor C21, capacitor C23 is connected in parallel at both ends of capacitor C22, and capacitor C24 is connected in parallel at both ends of capacitor C23. Capacitor C20, capacitor C21, capacitor C22, capacitor C23 and capacitor C24 form a voltage stabilizing circuit. The AVDD1, AVDD3, AVDD2 and DVDD terminals of the USB chip U11 are all connected to the V33_HUB terminal, the V33 terminal is connected to the V33_HUB terminal through the resistor R21, and the PGANG terminal is connected to the V33_HUB terminal through the resistor R26; the OVCUR1# terminal is connected to two inputs, one is connected to the 5V power supply through the resistor R24, and the other is grounded through the resistor R25; the REST# terminal is connected to two inputs, one is connected to the 5V power supply through the resistor R27, and the other is grounded through the capacitor C15, and the resistor R30 is connected to both ends of the capacitor R30; the RREF terminal is grounded through the resistor R20, and the PSELF terminal is connected to the 5V power supply through the resistor R28; the output of the DP0 terminal is divided into two paths, one is connected to the DP1 terminal of the Allwinner A64 chip, and the other is grounded through the resistor R22; the output of the DM0 terminal is divided into two paths The DP2 terminal of USB chip U11 is connected to the D+ terminal of host J12, and the DM2 terminal is connected to the D- terminal of host J12. The VBUS terminal of host J10 is divided into two inputs, one is connected to the 5V power supply, and the other is grounded through capacitor C17; the XIN terminal of crystal oscillator X1 has two inputs, one is connected to the X1 terminal of USB chip, and the other is grounded through capacitor C18; the XOUT terminal of crystal oscillator X1 has two outputs, one is connected to the X2 terminal of USB chip, and the other is grounded through capacitor C26; the GND terminals of crystal oscillator X1 are all grounded.

[0067] To ensure circuit stability, the 5V power supply is grounded through a capacitor.

[0068] The USB communication circuit of the utility model can be connected to a total of four hosts or other USB devices.

[0069] The GL850G chip of this utility model has low power consumption, an overload protection function, and provides self-power and bus-power automatic detection modes, eliminating the need for users to re-plug and re-plug the USB device. The USB communication circuit uses fewer components, reducing costs.

[0070] This utility model uses a 19V power supply circuit to power the RGB display circuit, a 5V power supply circuit to power the Allwinner A64 chip, HDMI circuit, USB communication circuit, and network port communication circuit, and a 3.3V power supply circuit to power the TF card storage circuit. The Allwinner A64 chip generates Beidou satellite analog signals, which are then sent to USB chip U11 via ports DM1 and DP1. After processing by USB chip U11, the Beidou satellite analog signals are sent to ports HUB_DM4 and HUB_DP4. The USB-to-Ethernet control chip U12 collects the Beidou satellite analog signals through ports HUB_DM4 and HUB_DP4, processes them, and sends them to filter transformer J11. The Beidou satellite analog signals from filter transformer J11 are then collected by a computer port.

Claims

1. A Beidou handheld analog terminal circuit, characterized in that: include: The Allwinner A64 chip is connected to the RGB display circuit, network port communication circuit, USB communication circuit, TF card storage circuit, HDMI circuit and 5V power supply circuit to generate analog signals; A 19V power supply circuit is connected to the RGB display circuit and is used to provide a 19V operating voltage to the RGB display circuit; The 5V power supply circuit is connected to the Allwinner A64 chip, the HDMI circuit, the USB communication circuit, and the network port communication circuit, respectively, and is used to provide a 5V operating voltage to the Allwinner A64 chip, the HDMI circuit, the USB communication circuit, and the network port communication circuit; 3.3V power supply circuit, connected to the TF card storage circuit, used to provide 3.3V operating voltage to the TF card storage circuit; The HDMI circuit is connected to the Allwinner A64 chip and the 5V power supply circuit respectively, and is used to transmit video signals; The network port communication circuit is connected to the Allwinner A64 chip and the 5V power supply circuit respectively, and is used to connect the USB interface and the Ethernet interface; as well as The USB communication circuit is connected to the Allwinner A64 chip and the 5V power supply circuit respectively, and is used for signal transmission with other USB devices.

2. The Beidou handheld simulation terminal circuit according to claim 1, characterized in that: The structure of the 19V power supply circuit is as follows: the VIN terminal of the boost chip U6 is connected to two inputs, one is grounded through the capacitor C11, one is connected to the power supply, and the other is connected to the display circuit after passing through the inductor L3 and the diode D3. The SW terminal of the boost chip U6 is connected to the display circuit through the diode D3; the FB terminal of the boost chip U6 has two outputs, one is grounded, and the other is connected to the display circuit through the capacitor C9, and a voltage divider circuit composed of resistors R9 and R12 is connected in parallel at both ends of the capacitor C9; the EN terminal of the boost chip U6 is connected to the VIN terminal of the boost chip U6.

3. The Beidou handheld simulation terminal circuit according to claim 1, characterized in that: The structure of the 5V power supply circuit is as follows: the SW end of the boost chip U2 is connected to two inputs after passing through the inductor L2, one of which is connected to the power supply VBAT-D through the field effect transistor P1, and the other is connected to the power supply VCC VBAT; the CBST end of the boost chip U2 is connected to the SW end of the boost chip U2 through the capacitor C6, and the VIN end of the boost chip U2 is connected to the power supply VCC VBAT; one end of the resistor R4 is connected to the power supply, and the other end is connected to the G pole of the field effect transistor P1; the resistor R4 is connected to the CSI-RST-F end of the Allwinner A64 chip through the diode D1, the diode D1 is connected to the D pole of the field effect transistor M1, the S pole of the field effect transistor M1 is grounded, the G pole of the field effect transistor M1 is connected to the CSISCK end of the Allwinner A64 chip, one end of the resistor R6 is connected to the G pole of the field effect transistor M1, and the other end is grounded; the EN end of the boost chip U2 is connected to two inputs, one of which is connected to the power supply VCC VBAT, two paths are grounded through capacitor C7, and capacitor C61 is connected in parallel at both ends of capacitor C7; the VOUT terminal of the boost chip U2 is connected to two outputs, one is grounded through the voltage divider circuit composed of resistors R3 and R5, and the other is connected to the 5V voltage output terminal; capacitor C4 is connected in parallel at both ends of the voltage divider circuit composed of resistors R3 and R5, and capacitor C5 is connected in parallel at both ends of capacitor C4; the GND terminal of the boost chip U2 is connected to two inputs, one is grounded, and the other is connected to the 5V voltage output terminal through LED diode D10 and resistor R55; the FB terminal of the boost chip U2 is connected to the voltage divider node of the voltage divider circuit composed of resistors R3 and R5.

4. The Beidou handheld simulation terminal circuit according to claim 1, characterized in that: The structure of the 3.3V power supply circuit is as follows: the SW terminal of the boost chip U1 is connected to the power supply VCC VBAT via the inductor L2, and the CBST terminal of the boost chip U1 is connected to the SW terminal of the boost chip U1 via the capacitor C3; the VIN terminal and the EN terminal of the boost chip U1 are both connected to the power supply VCC VBAT; the VOUT terminal of the boost chip U12 is connected to two outputs, one of which is grounded through a voltage divider circuit composed of resistors R1 and R2, and the other is connected to a TF card storage circuit; a capacitor C1 is connected in parallel across the voltage divider circuit composed of resistors R1 and R2, and a capacitor C2 is connected in parallel across the capacitor C1; the GND terminal of the boost chip U1 is connected to two inputs, one of which is grounded and the other is connected to the TF card storage circuit through an LED diode D5 and a resistor R54; and the FB terminal of the boost chip U1 is connected to the voltage divider node of the voltage divider circuit composed of resistors R1 and R2.

5. The Beidou handheld simulation terminal circuit according to claim 1, characterized in that: The structure of the HDMI circuit is as follows: the HDMI interface U5 is connected to three electrostatic protection devices respectively, the +5V end of the HDMI interface U5 is connected to the power supply VCC HDMI, the power supply VCC HDMI is connected to the 5V power supply through the diode D2, the power supply VCC HDMI is connected to the cathode of the diode D2, and the 5V power supply is connected to the anode of the diode D2.

6. The Beidou handheld simulation terminal circuit according to claim 1, characterized in that: The structure of the network port communication circuit is as follows: the USB to Ethernet control chip U12 is connected to the filter transformer J11 and the crystal oscillator X2 respectively; the RREF terminal, RSET_BG terminal, and EXTWAKEUP_N terminal of the USB to Ethernet control chip U12 are all grounded via a resistor; the RESET_N terminal of the USB to Ethernet control chip U12 is connected to two inputs, one of which is connected to the first 3.3V power supply via a resistor R44, and the other is grounded via a capacitor C30; the VCC3R3 terminal of the USB to Ethernet control chip U12 is connected to two inputs, one of which is connected to the second 3.3V power supply via a resistor R50, one end of the capacitor C44 is connected to the resistor R50 and the second 3.3V power supply respectively, and the other end is grounded; a capacitor C45 is connected in parallel at both ends of the capacitor C44, and the two paths are connected to the third 3.3V power supply; one end of the capacitor C52 is connected to the resistor R50 and the third 3.3V power supply respectively, The other end is grounded, and capacitor C51 is connected in parallel at both ends of capacitor C52; the V18F end of the USB to Ethernet control chip U12 is connected to the second 1.8V power supply through the first 1.8V power supply and resistor R51, one end of capacitor C47 is respectively connected to the first 1.8V power supply and resistor R51, and the other end is grounded, capacitor C46 is connected in parallel at both ends of capacitor C47, one end of capacitor C48 is respectively connected to the second 1.8V power supply and resistor R50, and the other end is grounded, and capacitor C49 is connected in parallel at both ends of capacitor C48; the VCC3IO ends of the USB to Ethernet control chip U12 are all connected to the fourth 3.3V power supply; the first 1.8V power supply is respectively connected to capacitor C34, capacitor C35, capacitor C36 and capacitor C37 and then grounded to form a parallel circuit, and the second 1.8V power supply is respectively connected to capacitor C38, capacitor C39 and capacitor C40 and then grounded to form a parallel circuit.

7. The Beidou handheld simulation terminal circuit according to claim 1, characterized in that: The structure of the USB communication circuit is as follows: the USB chip U11 is connected to the host and the crystal oscillator X1 respectively; the RREF terminal of the USB chip U11 is grounded via a resistor R20; the REST# terminal of the USB chip U11 is connected to two inputs, one is connected to a 5V power supply via a resistor R27, and the other is grounded via a capacitor C15; resistor R30 is connected to both ends of the capacitor R30; the V33 terminal of the USB chip U11 is connected to a voltage stabilizing circuit via a resistor R21; the PGANG terminal of the USB chip U11 is connected to a voltage stabilizing circuit via a resistor R26; and the DVDD terminal of the USB chip U11 is connected to a voltage stabilizing circuit; the OVCUR1# terminal of the USB chip U11 is connected to two inputs, one is connected to a 5V power supply via a resistor R24, and the other is grounded via a resistor R25.

8. The Beidou handheld simulation terminal circuit according to claim 7, characterized in that: The structure of the voltage stabilizing circuit is that one end of the capacitor C20 is connected to the resistor R21, and the other end is grounded, the two ends of the capacitor C21 are connected in parallel with the capacitor C21, the two ends of the capacitor C21 are connected in parallel with the capacitor C22, the two ends of the capacitor C22 are connected in parallel with the capacitor C23, and the two ends of the capacitor C23 are connected in parallel with the capacitor C24.

9. The Beidou handheld simulation terminal circuit according to claim 7, characterized in that: The VBUS terminal of each host has two inputs, one is connected to the 5V power supply, and the other is grounded through a capacitor; the D- port of each host is connected to the DM port of the USB chip, and the D+ port of each host is connected to the DP port of the USB chip.

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