Master-slave signal extraction device and system based on direct current carrier communication

Abstract

The utility model relates to a master-slave signal extraction device based on direct-current carrier communication and a system thereof, and the signal extraction device provided by the utility model can be respectively connected with a master and at least one slave through a communication bus of a direct-current carrier communication system. The signal extraction device is used for extracting signals generated by a host computer and / or at least one slave computer in a direct-current carrier communication system, and comprises an MCU control circuit, and the MCU control circuit is in communication connection with an upper computer; one end of the host signal acquisition circuit is connected to the MCU control circuit, and the other end of the host signal acquisition circuit is connected to a host through an input bus interface circuit; and one end of the slave signal acquisition circuit is connected to the MCU control circuit, and the other end of the slave signal acquisition circuit is connected to at least one slave through the input bus interface circuit. The master-slave signal extraction device provided by the utility model overcomes the defect that two-bus communication is not easy to position in the prior art, and realizes efficient and accurate two-bus communication analysis and positioning.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit communication, in particular to a master-slave signal extraction device based on direct current carrier communication and a system thereof. Background Art

[0002] In current fire control systems, the wiring between the controller (referred to as the host) and the node device (referred to as the slave) mostly adopts a two-wire system (i.e. DCS direct current carrier communication technology, where device communication and power supply share two wires). Compared with the four-wire system (two wires for device power supply and two wires for data communication), the two-wire communication system can save two wires.

[0003] While two-wire communication plus power supply can save on wires, it's still prone to issues like improper field wiring and overload. Furthermore, the communication protocols between the master and slave devices vary from manufacturer to manufacturer and are proprietary. For these reasons, master-slave communication in DC carrier communication systems often results in issues like slave uncontrollability, failure to report slave status, and malfunctions, all manifesting as communication-triggered issues.

[0004] Currently, manufacturers can only analyze the communication interaction process by capturing the communication waveforms on the two buses using an oscilloscope. However, capturing the communication waveforms requires access to an oscilloscope, and many field environments do not support strong power (AC220V) and cannot connect to an oscilloscope. Therefore, using an oscilloscope for waveform analysis is not suitable for all scenarios. On the other hand, even if an oscilloscope is available on site, it is still very inconvenient to analyze the communication code waveform bit by bit, which is not conducive to locating the problem. In view of this, it is urgent to develop a method and device that can accurately and efficiently analyze and locate the communication status between the master and slave devices.

[0005] In addition, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making the present invention, but due to space limitations, not all details and contents are listed in detail. However, this does not mean that the present invention does not have the characteristics of these prior arts. On the contrary, the present invention already has all the characteristics of the prior art, and the applicant reserves the right to add relevant prior art to the background technology. Utility Model Content

[0006] The utility model provides a master-slave signal extraction device based on DC carrier communication and a system thereof, which are used to solve the defect of difficult positioning of two-bus communication in the prior art and realize efficient and accurate two-bus communication analysis and positioning.

[0007] To achieve the above-mentioned object, the present invention provides a master-slave signal extraction device based on DC carrier communication, wherein the signal extraction device is communicatively coupled to a master and at least one slave, and is used to extract signals generated by the master and / or at least one slave in a DC carrier communication system, wherein the signal extraction device includes:

[0008] MCU control circuit, which is connected to the host computer;

[0009] A host signal acquisition circuit, one end of which is electrically connected to the MCU control circuit, and the other end is connected to the host through an input bus interface circuit;

[0010] The slave signal acquisition circuit has one end connected to the MCU control circuit and the other end connected to at least one slave through the input bus interface circuit.

[0011] Preferably, the signal extraction device provided by the present invention further includes a host signal optocoupler isolation circuit, one end of which is connected to the MCU control circuit, and the other end is connected to the host signal acquisition circuit.

[0012] Preferably, the signal extraction device provided by the present invention further includes a slave signal optocoupler isolation circuit, one end of which is connected to the MCU control circuit, and the other end of which communicates with the slave signal acquisition circuit.

[0013] Preferably, the signal extraction device provided by the present invention also includes an interface circuit, one end of which is connected to an external device, and the other end is connected in parallel to the MCU control circuit, the host signal optocoupler isolation circuit and the slave signal optocoupler isolation circuit.

[0014] Preferably, the signal extraction device provided by the present invention further includes a power isolation circuit, one end of which is connected to the interface circuit, and the other end of which is connected in parallel to the host signal acquisition circuit and the slave signal acquisition circuit.

[0015] Preferably, the signal extraction device provided by the present invention further includes an output bus interface circuit, one end of which is connected to the slave signal acquisition circuit, and the other end of which is connected to at least one slave.

[0016] Preferably, the MCU control circuit includes a control chip, a ninth capacitor, a tenth capacitor and a thirteenth capacitor, wherein the first pin of the control chip is connected to the ninth capacitor and the tenth capacitor respectively, the eighth pin of the control chip is connected to the output end of the slave signal optocoupler isolation circuit, the sixteenth pin of the control chip is connected to the output end of the host signal optocoupler isolation circuit, the other end of the ninth capacitor is connected to the twenty-fourth pin of the control chip, the other end of the tenth capacitor is connected to the twenty-fourth pin of the control chip, the thirteenth capacitor, and the digital ground; the other end of the thirteenth capacitor is connected to the twenty-third pin of the control chip.

[0017] Preferably, the host signal acquisition circuit includes a voltage regulator, a transistor, a seventeenth resistor, a nineteenth resistor, a twenty-second resistor and a fourteenth capacitor, wherein one end of the voltage regulator is connected to the bus input signal, and the other end is connected to the nineteenth resistor, the other end of the nineteenth resistor is respectively connected to the base of the transistor and the twenty-second resistor, the other end of the twenty-second resistor is connected to the analog ground, the collector of the transistor is connected to the seventeenth resistor, and the emitter of the transistor is connected to the fourteenth capacitor.

[0018] Preferably, the slave signal acquisition circuit includes an operational amplifier U2A, an operational amplifier U2B, a first resistor, a third resistor, a fifth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first capacitor and a second capacitor, wherein one end of the seventh resistor is connected to the analog ground, and the other end is respectively connected to the twelfth resistor and the second pin of the operational amplifier U2A, the tenth resistor and the eleventh resistor are connected in parallel to the eighth resistor, one end of the eighth resistor is connected to the analog ground, and the other end is connected to the ninth resistor, the other end of the ninth resistor is connected to the third pin of the operational amplifier U2A, the first pin of the operational amplifier U2A is connected to the twelfth resistor, the sixth pin of the operational amplifier U2B, and the analog ground, the fifth pin of the operational amplifier U2B is connected to the fifth resistor, the third resistor and the first resistor, the other end of the fifth resistor is connected to the analog ground, the other end of the first resistor is connected to the first capacitor and the second capacitor, the second capacitor is connected to the analog ground, and the other end of the third resistor is connected to the seventh pin of the operational amplifier U2B.

[0019] Preferably, the host signal optocoupler isolation circuit includes an optocoupler U4, a fifteenth resistor, a sixteenth resistor, an eleventh capacitor and a twelfth capacitor, wherein the second pin of the optocoupler U4 is connected to the fifteenth resistor, the other end of the fifteenth resistor is connected to the twelfth capacitor, the other end of the twelfth capacitor is connected to the analog ground, the third pin of the optocoupler U4 is connected to the output end of the host signal acquisition circuit, the eighth pin of the optocoupler U4 is respectively connected to the eleventh capacitor and the sixteenth resistor, the other end of the eleventh capacitor is connected to the fifth pin of the optocoupler U4 and to the digital ground, the other end of the sixteenth resistor is connected to the sixth pin of the optocoupler U4, and the remaining pins of the optocoupler U4 are left floating.

[0020] Preferably, the slave signal optocoupler isolation circuit includes an optocoupler U6, a twenty-first resistor, a twenty-third resistor, a fifteenth capacitor and a sixteenth capacitor, wherein the second pin of the optocoupler U6 is connected to the twenty-first resistor, the other end of the twenty-first resistor is connected to the sixteenth capacitor, the other end of the sixteenth capacitor is connected to the analog ground, the third pin of the optocoupler U6 is connected to the output end of the slave signal acquisition circuit, the eighth pin of the optocoupler U6 is respectively connected to the fifteenth capacitor and the twenty-third resistor, the other end of the fifteenth capacitor is connected to the fifth pin of the optocoupler U6 and to the digital ground, the other end of the twenty-third resistor is connected to the sixth pin of the optocoupler U6, and the remaining pins of the optocoupler U6 are left floating.

[0021] On the other hand, the present invention further provides a DC carrier communication system, which includes:

[0022] Host;

[0023] At least one slave;

[0024] The utility model also provides a master-slave signal extraction device, which is communicatively coupled to a host and at least one slave.

[0025] To locate and resolve a series of issues triggered by dual-bus communication problems, this utility model provides a portable device that connects to the bus and can capture both messages sent by the master and messages reported by slaves. These captured messages are reported to the host computer software in real time via a transmission interface. Communication issues can then be analyzed based on the messages exchanged between the master and slave, greatly facilitating the developer's ability to locate and resolve issues.

[0026] The master-slave signal extraction device based on DC carrier communication provided by the utility model simplifies the traditional method of locating the communication status between the master and the slave by connecting to an oscilloscope for waveform analysis. Unlike the traditional oscilloscope that requires on-site access to strong electricity, the signal extraction device provided by the utility model can be configured in any occasion, which is more flexible and has a wider applicability. In addition, the traditional oscilloscope can only capture a limited number of waveform signals within a limited period, while the signal extraction device provided by the utility model can intercept and retain all waveform signals generated between the master and the slave during the entire communication process. Compared with the traditional oscilloscope waveform analysis method, signal extraction through the signal extraction device improves the analysis efficiency of the communication status between the master and the slave. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 Schematic diagram of the circuit structure of the signal extraction device provided by the embodiment of the present utility model;

[0029] Figure 2 This is an architecture diagram of a DC carrier communication system provided by an embodiment of the present utility model;

[0030] Figure 3 This is a circuit schematic diagram of an interface circuit provided by an embodiment of the present utility model;

[0031] Figure 4 This is a circuit diagram of the MCU control circuit provided by an embodiment of the present utility model;

[0032] Figure 5 This is a circuit diagram of a power isolation circuit provided by an embodiment of the present utility model;

[0033] Figure 6 This is a circuit schematic diagram of a host signal optocoupler isolation circuit provided by an embodiment of the present utility model;

[0034] Figure 7 This is a circuit schematic diagram of a slave signal optocoupler isolation circuit provided by an embodiment of the utility model;

[0035] Figure 8 This is a circuit schematic diagram of a host signal acquisition circuit provided by an embodiment of the present utility model;

[0036] Figure 9 This is a circuit schematic diagram of a slave signal acquisition circuit provided by an embodiment of the present utility model;

[0037] Figure 10 This is a circuit schematic diagram of an input bus interface circuit provided by an embodiment of the present utility model;

[0038] Figure 11 This is a circuit schematic diagram of an output bus interface circuit provided by an embodiment of the present utility model;

[0039] Figure 12 A signal extraction method based on the signal extraction device provided by an embodiment of the present utility model;

[0040] Figure 13 1 is a flow chart of a signal extraction method provided by an embodiment of the present utility model;

[0041] Figure 14 It is a flowchart of the signal synchronization process provided by an embodiment of the present utility model.

[0042] Description of reference numerals:

[0043] 1: Interface circuit; 2: MCU control circuit; 3: Power supply isolation circuit; 4: Host signal optocoupler isolation circuit; 5: Slave signal optocoupler isolation circuit; 6: Host signal acquisition circuit; 7: Slave signal acquisition circuit; 8: Input bus interface circuit; 9: Output bus interface circuit. DETAILED DESCRIPTION

[0044] To make the purpose, technical solution, and advantages of this embodiment more clear, the technical solution of this embodiment will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of this embodiment, not all of it. Based on the embodiments in this embodiment, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this embodiment.

[0045] An embodiment of the present application provides a master-slave signal extraction device based on DC carrier communication. The master-slave signal extraction device is deployed (e.g., via wired or wireless means) in a DC carrier communication system and is electrically coupled to a master and a slave for DC carrier communication-based master-slave signal capture. The signal extraction device provided in this embodiment is described below.

[0046] According to a preferred embodiment, the signal extraction device provided in the embodiment of the present application may include:

[0047] A capture module, configured to capture signals from a master and / or slave;

[0048] A judgment module is used to judge the signal source of each frame of signal obtained through signal capture;

[0049] A processing module, configured to determine a signal processing method for each frame of signal based on the signal source and perform corresponding signal processing on each frame of signal;

[0050] The extraction module is used to extract and output the signal that has been processed and complies with the signal output rule, wherein the signal processing for the slave signal is performed after the host signal of the previous frame is extracted and output.

[0051] According to a preferred embodiment, the master-slave signal extraction device provided in the embodiment of the present application (such as Figure 1 , which can also be called a packet grabber) can include a communication unit, a control unit, a host optocoupler isolation unit, a slave optocoupler isolation unit, a host signal acquisition unit, a slave signal acquisition unit, an input unit, an output unit and an isolation unit.

[0052] Specifically, one end of the control unit is electrically / communicatively connected to a host signal acquisition unit and a slave signal acquisition unit. The host signal acquisition unit and the slave signal acquisition unit are electrically / communicatively connected to the host and at least one slave, respectively, via an input unit, allowing the host signal acquisition unit and the slave signal acquisition unit to respectively acquire data signals uploaded by the host and at least one slave, and send the acquired data signals to the control unit for processing. The other end of the control unit is electrically / communicatively connected to a communication unit, and the other end of the communication unit is electrically / communicatively connected to an external device or a third-party terminal to output the host and slave signals processed by the control unit. For example, the output is displayed through a host computer software interface.

[0053] A host optical coupling isolation unit is electrically / communicatively connected between the control unit and the host signal acquisition unit, and a slave optical coupling isolation unit is electrically / communicatively connected between the control unit and the slave signal acquisition unit.

[0054] On the other hand, an external power supply can be connected through the communication unit to supply power to the control unit, the master optical coupling isolation unit, the slave optical coupling isolation unit, the master signal acquisition unit, and the slave signal acquisition unit of the master-slave signal extraction device. The power supply for the analog part of the master-slave signal extraction device is generated by the isolation unit.

[0055] More specifically, if Figure 1 and 2 As shown, the master-slave signal extraction device (or message grabber) provided in the embodiment of the present application can be composed of an interface circuit 1, an MCU control circuit 2, a power isolation circuit 3, a host signal optocoupler isolation circuit 4, a slave signal optocoupler isolation circuit 5, a host signal acquisition circuit 6, a slave signal acquisition circuit 7, an input bus interface circuit 8 and an output bus interface circuit 9.

[0056] like Figure 2 As shown, the host is connected to the input bus interface circuit 8 of the signal extraction device (i.e., the packet capturer) via a communication bus. One or more slaves are connected to the communication bus connected to the host. One or more slaves are connected to the output bus interface 9 of the signal extraction device via another communication bus. On the other hand, the signal extraction device is connected to the host computer via the interface circuit 1.

[0057] According to a preferred embodiment, Figure 3As shown, the interface circuit 1 may include a Type B interface USB1, a USB-to-serial port chip U1, and capacitors C3, C4, C5, C19, and C20. Specifically, the USB 5V voltage is taken from pin 1 of the Type B interface USB1 to power the entire device, and capacitors C19 and C20 serve as energy storage filter capacitors for the USB 5V power supply. The other ends of capacitors C19 and C20 are connected to digital ground. Pins 5 D+ and 6 D- of the USB-to-serial port chip U1 are connected to pins 3 D+ and 2 D- of the Type B interface USB1, respectively. The USB-to-serial port chip U1 converts the USB high-speed signals pins 5 D+ and 6 D- of the USB into serial port TTL signals. Pin 3 UART_TX of the USB-to-serial port chip U1 is connected to the MCU control circuit 3.

[0058] According to a preferred embodiment, pin 4 of USB-to-serial port chip U1 is connected to capacitor C5. The other end of capacitor C5 is connected to digital ground. Pin 16 of USB-to-serial port chip U1 is connected to capacitors C3, C4, and USB5V, respectively. The other ends of capacitors C3 and C4 are connected to digital ground. The remaining pins of USB-to-serial port chip U1 are left floating. Capacitors C3, C4, and C5 primarily provide power filtering and decoupling for USB-to-serial port chip U1.

[0059] According to a preferred embodiment, Figure 4 As shown, MCU control circuit 2 includes control chip U5 and capacitors C9, C10, and C13. Control chip U5 uses an internal oscillator circuit as the system clock source. USB 5V is connected to pin 1 of control chip U5, capacitors C9, and C10. The other end of capacitor C9 is connected to pin 24 of control chip U5. The other end of capacitor C10 is connected to pin 24 of control chip U5, capacitor C13, and digital ground. The other end of capacitor C13 is connected to pin 23 of control chip U5. Capacitors C9 and C10 provide filtering and decoupling for control chip U5. Capacitor C13 forms the power-on reset circuit.

[0060] According to a preferred embodiment, Figure 4 As shown, pin 3 (UART_TX) of USB-to-serial port chip U1 is connected to pin 21 of control chip U5 in MCU control circuit 2 to transmit the collected signal. Pin 8 (SLAVE_INT_RX) of control chip U5 is connected to the output of slave optocoupler signal isolation circuit 5 to collect slave signals. The slave signal flow is: SLAVE_INT_RX->UART_TX->D+D-. Pin 16 (MASTER_INT_RX) of control chip U5 is connected to the output of host optocoupler signal isolation circuit 4 to collect host signals. The host signal flow is: MASTER_INT_RX->UART_TX->D+D-.

[0061] According to a preferred embodiment, Figure 5 As shown, the power isolation circuit 3 includes an isolated power chip U8 and capacitors C17 and C18. USB5V is a DC 5V power supply obtained from the interface circuit 1 and is used to power the digital portion of the device. The 5V power supply for the analog portion of the device is generated by the isolated power chip U8. Capacitors C17 and C18 are filter capacitors for the power chip U8. Pin 1 of the isolated power chip U8 is connected to capacitor C18 and to digital ground. The other end of capacitor C18 is connected to USB5V and to pin 2 of the isolated power chip U8. Pin 3 of the isolated power chip U8 is connected to capacitor C17 and to analog ground. The other end of capacitor C17 is connected to pin 4 of the isolated power chip U8.

[0062] According to a preferred embodiment, Figure 6 As shown, the host signal optocoupler isolation circuit 4 includes an optocoupler U4, resistors R15 and R16, and capacitors C11 and C12. To prevent instability in the MCU control circuit 2 caused by interference from field devices at the bus end, the collected host signals must be isolated by the optocoupler before entering the MCU control circuit 2.

[0063] According to a preferred embodiment, MASTER_EXT_RX is the host signal collected and output by the host signal acquisition circuit 6, which serves as the optocoupler input signal. MASTER_INT_RX is the host signal output by the optocoupler and connected to pin 16 of the control chip U5 in the MCU control circuit 2. R15 is a current-limiting resistor at the optocoupler input. C12 is a filter capacitor for the optocoupler input power supply. One end of capacitor C12 is connected to analog ground, and the other end is connected to a 5V power supply and resistor R15. The other end of resistor R15 is connected to pin 2 of the optocoupler U4. R16 is a pull-up resistor at the optocoupler output. One end of resistor R16 is connected to pin 6 of the optocoupler U4, and the other end is connected to the 5V power supply introduced by the USB interface and to pin 8 of the optocoupler U4. C11 is a power filter capacitor for the optocoupler output. One end of capacitor C11 is connected to pin 8 of the optocoupler U4, and the other end is connected to pin 5 of the optocoupler U4 and to digital ground.

[0064] According to a preferred embodiment, Figure 7 As shown, the slave signal optocoupler isolation circuit 5 includes an optocoupler U6, resistors R21 and R23, and capacitors C15 and C16. The slave signal is identical or similar to the master signal. To avoid instability in the MCU control circuit 2, the collected slave signal also needs to be optically isolated before entering the MCU control circuit 2.

[0065] According to a preferred embodiment, SLAVE_EXT_RX is the slave signal collected and output by the slave signal acquisition circuit 7, which serves as the optocoupler input signal. SLAVE_INT_RX is the slave signal output by the optocoupler and connected to pin 8 of the control chip U5 in the MCU control circuit 2. R21 is a current-limiting resistor at the optocoupler input. C16 is a filter capacitor for the optocoupler input power supply. Capacitor C16 has one end connected to analog ground, and the other end connected to a 5V power supply and resistor R21. The other end of resistor R21 is connected to pin 2 of the optocoupler U6. R23 is a pull-up resistor at the optocoupler output. Resistor R23 has one end connected to pin 6 of the optocoupler U6, and the other end connected to the 5V power supply introduced by the USB interface and to pin 8 of the optocoupler U6. C15 is a power supply filter capacitor at the optocoupler output. Capacitor C15 has one end connected to pin 8 of the optocoupler U6, and the other end connected to pin 5 of the optocoupler U6 and to digital ground.

[0066] According to a preferred embodiment, Figure 8 As shown, the host signal acquisition circuit 6 includes a voltage regulator D1, resistors R17, R19 and R22, a transistor Q1 and a capacitor C14. Figure 8 BUS1 and BUS2 are the incoming bus input signals, which are divided by the voltage regulator diode D1 and resistors R19 and R22, driving transistor Q1 to output the host acquisition signal MASTER_EXT_RX. The output host signal MASTER_EXT_RX is connected to the input of the optocoupler U4 of the host optocoupler isolation circuit 4. Among them, R17 and C14 are the pull-up resistor and filter capacitor at the output of the host signal acquisition circuit 6, respectively. One end of resistor R19 is connected to the voltage regulator diode D1, and the other end is connected to resistor R22 and transistor Q1 respectively. The other end of resistor R22 is connected to analog ground. Transistor Q1 is connected to resistor R17 and capacitor C14. The other end of resistor R17 is connected to a 5V power supply.

[0067] Specifically, the host's signal demodulation principle is as follows: when the host sends a high level (amplitude equal to the host power supply voltage) on bus 2, transistor Q1 is turned on, and MASTER_EXT_RX output is 0; when the host sends a low level (amplitude 0) on bus 2, transistor Q1 is turned off, and MASTER_EXT_RX output is 1. Conversely, the host signal acquisition process of MASTER_EXT_RX is exactly the opposite of the sending end. When implementing the software of MCU control circuit 2, MASTER_EXT_RX can be set to the opposite.

[0068] According to a preferred embodiment, Figure 9As shown, the slave signal acquisition circuit 7 includes operational amplifiers U2A and U2B, resistors R1, R3, R5, R7, R8, R9, R10, R11, and R12, and capacitors C1 and C2. Resistors R8, R10, and R11 are connected in parallel to form an acquisition circuit for acquiring the slave current signal. Resistor R8 has one end connected to resistor R9, and the other end to analog ground. The other end of resistor R9 is connected to pin 3 of operational amplifier U2A. Pin 2 of amplifier U2A is connected to resistor R7. The other end of resistor R7 is connected to analog ground. Pin 1 of operational amplifier U2A is connected to pin 6 and R12 of operational amplifier U2B, respectively. Pin 5 of operational amplifier U2B is connected to R5, R3, and R1. The other end of resistor R5 is connected to analog ground. The other end of R1 is connected to C1 and C2. The other ends of C1 and C2 are connected to analog ground. The other end of R3 is connected to pin 7 of operational amplifier U2B.

[0069] According to a preferred embodiment, operational amplifier U2A and resistors R7 and R12 form a first-stage proportional operational amplifier with an amplification factor of 1 + R12 / R7. Resistor R9 is used to improve the offset voltage of the operational amplifier. Operational amplifier U2B and resistors R1, R3, and R5 form a comparator, and the comparator's comparison reference voltage is R5 * (5 / (R1 + R5)). Capacitors C1 and C2 are used to decouple and filter operational amplifiers U2A and U2B. The output slave signal SLAVE_EXR_RX is connected to the input of optocoupler U6 of slave optocoupler isolation circuit 5.

[0070] Specifically, the slave's signal demodulation principle is as follows: the voltage on BUS- represents the original analog signal from the slave. Because the original signal is too small, it needs to be amplified by operational amplifier U2A to an appropriate value. Then, operational amplifier U2B compares the voltage to the slave's digital signal. When the slave transmits a high level (current flows from BUS-->R8, R10, R11->AGND, current is 0mA), BUS- is 0V, U2A outputs 0V, and SLAVE_EXR_RX demodulates to a high level. When the slave transmits a low level (current flows from BUS-->R8, R10, R11->AGND, current is 30mA), BUS- is a weak voltage. After amplification by operational amplifier U2A, it is input to the inverting output of pin 6 of U2B. At this point, it is greater than the voltage at the non-inverting input of pin 5, and SLAVE_EXR_RX demodulates to a low level.

[0071] According to a preferred embodiment, Figure 10 As shown, the input bus interface circuit 8 includes a connection terminal CON1. ​​BUS1 and BUS2 of the connection terminal CON1 are connected to the BUS+ and BUS- sides of the host.

[0072] According to a preferred embodiment, Figure 11As shown, the output bus interface circuit 9 includes a connection terminal CON2. BUS+ and BUS- of the connection terminal CON2 are connected to a node device (ie, a slave) on the subsequent bus.

[0073] To locate and resolve a series of issues triggered by dual-bus communication problems, the present invention provides a portable device (referred to as a message grabber) that connects to the bus and can capture both messages sent by the host and messages reported by the slave. The captured messages are reported to the computer's host software in real time via the USB interface. Communication problems can then be analyzed based on the messages exchanged between the host and slave, greatly facilitating the developer's ability to locate and resolve issues.

[0074] See also Figure 12 According to the master-slave signal extraction device based on DC carrier communication provided by the present invention, a method for extracting master-slave signals using the signal extraction device may include one of the following steps:

[0075] S100: Execute a signal capture task for a master and / or at least one slave.

[0076] S200: Determine the signal source of each frame of signal acquired through the signal capture task.

[0077] S300: Determine a signal processing method for each frame of signal based on the signal source and perform corresponding signal processing on each frame of signal.

[0078] S400: extracting and outputting the processed signal that complies with the signal output rule.

[0079] The signals captured by the signal extraction device include host signals and slave signals, and the processing of the slave signals is performed after any frame of host signals that conform to the signal output rule is extracted and output.

[0080] See also Figure 13 The master-slave signal extraction method provided in the embodiments of the present application mainly includes three steps: signal capture, signal synchronization, and signal output. Signal synchronization, which can be called a data verification process, includes two stages: master signal synchronization and slave signal synchronization, which are used to verify whether the captured master and slave signals comply with the expected data verification rules and / or signal output rules.

[0081] Specifically, in the embodiment of the present application, S200: the step of determining the signal source of each frame signal obtained through the signal capture task is specifically as follows: the signal extraction device can determine the source of the signal based on the set communication protocol, that is, the master signal and the slave signal generally have corresponding signal performances based on the definition of the communication protocol, so the signal extraction device signal can determine the signal source. It is understandable that the content of determining the type (or source) of various types of signals based on the definition of the communication protocol has been disclosed in a large amount of prior art. To avoid lengthy description, it will not be repeated here.

[0082] like Figure 13 As shown, in the embodiment of the present application, S300: determining the signal processing method for each frame signal based on the signal source and performing corresponding signal processing on each frame signal may specifically include:

[0083] Determine whether the currently captured signal is a host signal, where:

[0084] If the current signal captured by the signal extraction device is a host signal, data processing is performed on the host signal; otherwise, the signal is continued to be captured.

[0085] Further, if Figure 13 As shown, after the signal extraction device captures the host signal, it performs signal synchronization on the host signal to determine whether the captured host signal meets the signal output rule, wherein,

[0086] If the captured host signal meets the signal output rules, that is, meets the expected data verification standards / results, the host signal is extracted and output.

[0087] In other words, if the host signal verification result is correct, the synchronization process between the signal extraction device and the host signal is considered complete, and the process proceeds to the signal output phase. Otherwise, the process returns to the capture phase, i.e., continues to acquire the next host signal. On the other hand, if the host signal does not meet the signal output rules, that is, does not meet the expected data verification standards / results, then the host signal can be discarded.

[0088] In addition, if Figure 13 As shown, after any frame of host signal that meets the signal output rule (or data verification standard / result) is extracted and output, the signal extraction device continues to perform the signal capture task and determines the source of the next frame of signal, wherein,

[0089] If the current signal captured is a slave signal, data processing is performed on the current slave signal; otherwise, the signal is continued to be captured.

[0090] Further, if Figure 13As shown, after the signal extraction device captures the slave signal, it performs signal synchronization on the slave signal to determine whether the captured slave signal meets the signal output rule, wherein,

[0091] If the captured slave signal complies with the signal output rule, that is, meets the expected data verification standard / result, the slave signal is extracted and output.

[0092] In other words, if the slave signal's verification result is correct, the synchronization process between the signal extraction device and the slave signal is considered complete, and the process proceeds to the signal output phase. Otherwise, the process returns to the capture phase, which involves acquiring the next master signal. On the other hand, if the slave signal does not meet the signal output rules—that is, does not meet the expected data verification criteria / results—then it can be discarded.

[0093] Specifically, if Figure 14 As shown, in the embodiment of the present application, S400: the step of extracting and outputting the signal that has been processed and meets the signal output rule may specifically include:

[0094] Receive and determine whether each byte contained in the current signal is correct in sequence;

[0095] Perform full frame check on a data frame consisting of multiple bytes;

[0096] If each byte and the entire data frame contained in the current signal are correct, the current signal is extracted and output; otherwise, the current signal is discarded.

[0097] In other words, the signal extraction device first determines whether the first byte of the received data frame has been verified correctly. If not, it continues to determine the next received byte. If the currently received byte has been verified correctly, it continues to receive the next byte. After receiving a certain number of correct bytes (the length is specified by the communication protocol), it finally receives the end-of-frame byte. The end-of-frame byte is a checksum of the previously received bytes. Afterwards, the data frame composed of these bytes is subjected to an entire frame check. The above single-byte check and entire-frame check complete the data verification (i.e., signal synchronization) process for the captured signal (or data frame).

[0098] It is understandable that, for ease of operation, the data verification rules for the master signal and the slave signal in this application are consistent. In other embodiments, different data verification methods can be used for the master signal and the slave signal, which is usually determined by the design and development personnel.

[0099] As an example, in an embodiment of the present application, the data verification rule for each signal (or data frame) adopts a level verification rule, that is, confirming the byte level of each byte contained in each captured signal (or data frame) and the frame level of the entire signal (or data frame). Specifically, the byte verification rule is defined as: the start bit of each byte is a low level, and the stop bit is a high level. The frame verification rule is defined as: whether the cumulative result of the sub-node levels of several bytes is consistent with the whole frame level result of the data frame. It is understandable that the level verification is only an illustration of a non-limiting example made for the disclosure of this application and should not be regarded as a specific limitation of this application. Those skilled in the art may adopt other verification methods as appropriate.

[0100] Furthermore, in the signal output stage, the signal extraction device transmits the received signal (host signal and / or slave signal) that meets the signal output rules to a third-party terminal device via a wired and / or wireless method for positioning analysis. As an example, in this application, the signal extraction device can upload the signal that meets the signal output rules to the host computer via the transmission interface (i.e., interface circuit 1).

[0101] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations that may be implemented according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0102] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0103] Finally, it should be noted that the present specification and its drawings are illustrative and do not constitute limitations on the claims. Although this embodiment has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. However, these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of this embodiment. This specification contains multiple inventive concepts. Terms such as "preferably," "according to a preferred embodiment," or "optionally" indicate that the corresponding paragraph discloses an independent concept. The applicant reserves the right to file divisional applications based on each inventive concept.

Claims

1. A master-slave signal extraction device based on DC carrier communication, wherein the signal extraction device is communicatively coupled to a master and at least one slave, and is used to extract signals generated by the master and / or at least one slave in a DC carrier communication system, characterized in that: The signal extraction device comprises: An MCU control circuit (2), wherein the MCU control circuit (2) is communicatively connected to a host computer; A host signal acquisition circuit (6), the output end of which is electrically connected to the MCU control circuit (2), and the input end of which is electrically connected to the host through an input bus interface circuit (8); The slave signal acquisition circuit (7) has an output end electrically connected to the MCU control circuit (2), and an input end electrically connected to the at least one slave through an input bus interface circuit (8).

2. The signal extraction device according to claim 1, characterized in that It also includes a host signal optocoupler isolation circuit (4), the output end of the host signal optocoupler isolation circuit (4) is electrically connected to the MCU control circuit (2), and the input end is electrically connected to the host signal acquisition circuit (6).

3. The signal extraction device according to claim 2, characterized in that It also includes a slave signal optocoupler isolation circuit (5), the output end of the slave signal optocoupler isolation circuit (5) is electrically connected to the MCU control circuit (2), and the input end is electrically connected to the slave signal acquisition circuit (7).

4. The signal extraction device according to claim 3, characterized in that The MCU control circuit (2) comprises a control chip, a ninth capacitor, a tenth capacitor and a thirteenth capacitor, wherein the first pin of the control chip is connected to the ninth capacitor and the tenth capacitor respectively, the eighth pin of the control chip is connected to the output end of the slave signal optocoupler isolation circuit (5), the sixteenth pin of the control chip is connected to the output end of the host signal optocoupler isolation circuit (4), the other end of the ninth capacitor is connected to the twenty-fourth pin of the control chip, the other end of the tenth capacitor is connected to the twenty-fourth pin of the control chip, the thirteenth capacitor and a digital ground; and the other end of the thirteenth capacitor is connected to the twenty-third pin of the control chip.

5. The signal extraction device according to claim 1, wherein: The host signal acquisition circuit (6) includes a voltage regulator, a transistor, a seventeenth resistor, a nineteenth resistor, a twenty-second resistor and a fourteenth capacitor, wherein one end of the voltage regulator is connected to the bus input signal, and the other end is connected to the nineteenth resistor, the other end of the nineteenth resistor is respectively connected to the base of the transistor and the twenty-second resistor, the other end of the twenty-second resistor is connected to the analog ground, the collector of the transistor is connected to the seventeenth resistor, and the emitter of the transistor is connected to the fourteenth capacitor.

6. The signal extraction device according to claim 1, characterized in that The slave signal acquisition circuit (7) includes an operational amplifier U2A, an operational amplifier U2B, a first resistor, a third resistor, a fifth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first capacitor and a second capacitor, wherein one end of the seventh resistor is connected to the analog ground, and the other end is respectively connected to the twelfth resistor and the second pin of the operational amplifier U2A; the tenth resistor and the eleventh resistor are connected in parallel to the eighth resistor; one end of the eighth resistor is connected to the analog ground, and the other end is connected to the ninth resistor; the other end of the ninth resistor is connected to the third pin of the operational amplifier U2A; the first pin of the operational amplifier U2A is connected to the twelfth resistor, the sixth pin of the operational amplifier U2B, and the analog ground; the fifth pin of the operational amplifier U2B is connected to the fifth resistor, the third resistor and the first resistor; the other end of the fifth resistor is connected to the analog ground; the other end of the first resistor is connected to the first capacitor and the second capacitor; the second capacitor is connected to the analog ground; the other end of the third resistor is connected to the seventh pin of the operational amplifier U2B.

7. The signal extraction device according to claim 3, characterized in that: The device also includes an interface circuit (1), one end of which is electrically connected to an external device, and the other end of which is connected in parallel to the MCU control circuit (2), the host signal optocoupler isolation circuit (4), and the slave signal optocoupler isolation circuit (5).

8. The signal extraction device according to claim 7, characterized in that: It also includes a power isolation circuit (3), one end of which is electrically connected to the interface circuit (1), and the other end of which is connected in parallel to the host signal acquisition circuit (6) and the slave signal acquisition circuit (7).

9. The signal extraction device according to claim 1, characterized in that: It also includes an output bus interface circuit (9), one end of the output bus interface circuit (9) is electrically connected to the slave signal acquisition circuit (7), and the other end is electrically connected to the at least one slave.

10. A DC carrier communication system, characterized in that: include: Host; At least one slave; And the signal extraction device according to any one of claims 1 to 9, the signal extraction device is communicatively coupled to the host and at least one slave.

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