Optical sensor with silicon-based CMOS and avalanche diode integrated in parallel

Abstract

The utility model relates to a silicon-based CMOS and avalanche diode parallel integrated optical sensor. The optical sensor comprises a substrate; the epitaxial layer is positioned on the substrate; one or more single photon avalanche diodes (SPAD) located in the epitaxial layer, the SPAD comprising: a buried layer; the avalanche region is located on the buried layer; the diode doping region is located on the upper surface of the avalanche region; the SPAD electrode leading-out region is located on the buried layer and located on the single side, the two sides or the periphery of the avalanche region; the SPAD electrode contact region is positioned on the upper surface of the SPAD electrode extraction region; the silicon-based CMOS transistor circuits are located in the epitaxial layer, and the single photon avalanche diode and the CMOS transistor circuits are located on the same plane and are electrically connected. According to the optical sensor, the avalanche diode and the CMOS circuit are in the same plane, so that all functions of the sensor can be completed on one chip.

Description

Technical Field

[0001] The utility model relates to the technical field of optical sensors, in particular to an optical sensor integrating a silicon-based CMOS and an avalanche diode in parallel. Background Art

[0002] As artificial intelligence (AI) becomes increasingly widespread across various fields, photoelectric conversion devices, as key sensors, are gaining increasing attention. SPAD (single-photon avalanche diode) arrays are widely used in fields requiring detection and imaging at extremely low light intensities, such as homeland security, aerial mapping, lidar, time-of-flight sensing, security monitoring, and biomedical imaging.

[0003] The SPAD array sensor mainly includes an avalanche diode, a bias circuit, a quenching circuit, and a readout circuit to form a complete sensor function. The existing SPAD array sensors are mainly divided into two categories: 1. The avalanche diode 10 made of III-V materials and the auxiliary circuit 20 (including: bias circuit, quenching circuit, readout circuit) realized by silicon-based CMOS (complementary metal oxide semiconductor transistor) process are stacked and packaged, such as Figure 1 This type of SPAD array sensor has good functional parameters, but is difficult to process, has high cost, and has a low yield rate.

[0004] 2. Avalanche diodes 30 are directly manufactured based on silicon-based CMOS technology, and avalanche diode arrays are directly manufactured on silicon-based CMOS auxiliary circuits 40. The two are directly connected through lines 50, so that all sensor functions can be completed on one chip. Figure 2 This type of SPAD array sensor is easy to process and low-cost, but SPAD uses silicon material, which has poor infrared sensing performance. This is especially true when used in infrared lidar detection. Due to the limitations of silicon material for infrared wavelengths, the maximum infrared light wavelength can only reach 910nm, which greatly limits its application. Utility Model Content

[0005] To solve at least some of the above problems in the prior art, the present invention provides a light sensor integrating a silicon-based CMOS and an avalanche diode, comprising:

[0006] substrate;

[0007] an epitaxial layer located on the substrate;

[0008] One or more single-photon avalanche diodes (SPADs) located in the epitaxial layer, the single-photon avalanche diodes (SPADs) comprising:

[0009] buried layer;

[0010] an avalanche zone located above the buried layer;

[0011] a diode doped region located on an upper surface of the avalanche region;

[0012] A SPAD electrode lead-out region located above the buried layer and on one side, both sides, or all four sides of the avalanche region;

[0013] A SPAD electrode contact region, which is located on the upper surface of the SPAD electrode lead-out region;

[0014] One or more silicon-based CMOS transistor circuits are located in the epitaxial layer, wherein the single-photon avalanche diode and the CMOS transistor circuits are located in the same plane and are electrically connected.

[0015] Furthermore, the avalanche region includes a first portion and a second portion, the first portion is located above the second portion, and the first portion is a germanium silicon material layer.

[0016] Furthermore, when the diode doping region serves as the SPAD anode, it is formed by P-type ion doping, and the buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD cathode, all of which are formed by N-type ion doping; or

[0017] When the diode doping region serves as the negative electrode of the SPAD, it is formed by N-type ion doping. The buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the positive electrode of the SPAD and are all formed by P-type ion doping.

[0018] Furthermore, the silicon-based CMOS transistor circuit includes:

[0019] A silicon-based PMOS transistor circuit comprising:

[0020] N-well;

[0021] gate;

[0022] A P active region located on the upper surface of the N well; and

[0023] an N active region located on an upper surface of the N well; and

[0024] A silicon-based NMOS transistor circuit comprising:

[0025] P-well;

[0026] gate;

[0027] A P active region, located on the upper surface of the P well;

[0028] The N active region is located on the upper surface of the P well.

[0029] Furthermore, it also includes:

[0030] a gate oxide layer located above the epitaxial layer and below the gate electrode;

[0031] An oxide layer is located on the gate oxide layer and covers the gate.

[0032] Furthermore, it also includes:

[0033] a first dielectric layer, which is located above the oxide layer and above the positive electrode structure;

[0034] The second dielectric layer is located on the first dielectric layer.

[0035] Furthermore, it also includes metal wires, which are electrically connected to the P active area, the N active area, the gate, the diode doping area and the SPAD electrode contact area.

[0036] Furthermore, the buried layer is located in the substrate and the epitaxial layer.

[0037] The utility model has at least the following beneficial effects:

[0038] (1) In the optical sensor of the present invention, the avalanche diode and the CMOS circuit are on the same plane. The avalanche diode is produced by using a silicon-based CMOS process and injecting germanium ions on the silicon material without affecting the CMOS process. The avalanche diode is connected to the silicon-based CMOS auxiliary circuit in the same plane, so that all the functions of the sensor can be completed on one chip. (2) Germanium ions are directly injected into the epitaxial layer to form an avalanche zone. The physical property of germanium material that absorbs infrared light better than silicon is used to increase the quantum absorption probability of mid-infrared waves, so that its infrared wavelength can be extended to 1550nm. The performance and application scenarios are greatly improved compared to the all-silicon-based SPAD, especially the applicable range of infrared wavelengths is greatly expanded. (3) Directly injecting germanium ions to dope the epitaxial layer is simple in process and the effect is better than the SPAD with a silicon material avalanche zone. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding components will be represented by the same or similar reference numerals.

[0040] Figure 1 A schematic diagram of the structure of a sensor with a stacked avalanche diode and a CMOS auxiliary circuit is shown;

[0041] Figure 2 The schematic diagram of the structure of the sensor in which the existing avalanche diode array is directly fabricated on the silicon-based CMOS auxiliary circuit is shown;

[0042] Figures 3 to 17 A cross-sectional schematic diagram showing a process of forming a light sensor integrating a silicon-based CMOS and an avalanche diode in parallel according to an embodiment of the present invention; and

[0043] Figure 18 A cross-sectional schematic diagram of a light sensor in which a silicon-based CMOS and an avalanche diode are integrated in parallel according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0044] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0045] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be understood as limiting.

[0046] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0047] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the guidance of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0048] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and so on do not mean that the two values ​​are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to".

[0049] It should also be noted that in the description of this utility model, the terms "center," "longitudinal," "transverse," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this utility model and simplify the description. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0051] In the present invention, the N-type doping element includes arsenic, phosphorus or antimony; the P-type doping element includes boron, gallium or indium.

[0052] Figures 3 to 17 A cross-sectional schematic diagram shows a process of forming a light sensor integrating a silicon-based CMOS and an avalanche diode in parallel according to an embodiment of the present invention.

[0053] A method for forming a light sensor integrating a silicon-based CMOS and an avalanche diode in parallel includes:

[0054] Step 1, such as Figure 3 As shown, a photoresist is arranged on a substrate 101, and the photoresist is patterned by a photolithography process to obtain a buried region pattern 102. The substrate 101 is a P-type silicon substrate, and can also be an N-type silicon substrate.

[0055] Step 2, such as Figure 4 As shown, N+ ion implantation is performed on the substrate exposed by the buried layer pattern 102 to form a buried layer 103, and then the photoresist is removed. The buried layer 103 is an N+ buried layer and serves as the charge collection region of the SPAD.

[0056] Step 3, such as Figure 5 As shown, an epitaxial layer 104 is grown on a substrate 101 , and during the epitaxial process, elements of the buried layer 103 diffuse into the epitaxial layer 104 .

[0057] In this embodiment, if the substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer (N-epitaxial layer). If the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer (P-epitaxial layer). In one embodiment of the present invention, the epitaxial temperature is 1000-1200°C.

[0058] Step 4, such as Figure 6 As shown, a SPAD electrode lead-out region 1051 and an N-well 1052 are formed in the epitaxial layer 104. A photoresist is deposited on the upper surface of the epitaxial layer 104 and patterned using a photolithography process to form multiple N-well regions. N-type ion implantation and annealing are then performed on the epitaxial layer exposed in the multiple N-well regions to form the SPAD electrode lead-out region 1051 and the N-well 1052. The photoresist is then removed. The SPAD electrode lead-out region is a negative lead-out region.

[0059] In situations where the noise requirement is low, the SPAD electrode lead-out region can also be subjected to a separate high-concentration N+ type implantation.

[0060] Step 5, such as Figure 7As shown, a P-well 106 is formed in the epitaxial layer 104. Photoresist is deposited on the upper surface of the epitaxial layer 104 and patterned by photolithography to form a P-well region. P-type ion implantation and annealing are performed on the epitaxial layer exposed in the P-well region to form the P-well 106, and then the photoresist is removed.

[0061] The order of steps 4 and 5 can be reversed.

[0062] Step 6, such as Figure 8 As shown, a gate oxide layer 107 and a polysilicon layer 108 are sequentially grown on the upper surface of the epitaxial layer 104 .

[0063] Step 7, such as Figure 9 As shown, the polysilicon layer 108 is etched to form a gate 109. Specifically, a photoresist is arranged on the polysilicon layer 110 and patterned, the polysilicon is etched to obtain a gate 111, and the photoresist is removed.

[0064] Step 8, such as Figure 10 As shown, an oxide layer 110 is deposited on the gate oxide layer 107 and the gate electrode 109.

[0065] Step 9, such as Figure 11 As shown, an N active region 111 is formed in the N well 1052 and the P well 106, and a SPAD electrode contact region 112 is formed in the SPAD electrode lead-out region 1051. Specifically, a photoresist is deposited on the oxide layer 110 and the portion of the photoresist located above the SPAD electrode lead-out region 1051, the N well 1052, and the P well 106 is removed by photolithography. The exposed oxide layer 110 and the gate oxide layer 107 are etched to expose the SPAD electrode lead-out region 1051, the N well 1052, and the P well 106. Then, N+ ion implantation and annealing are performed on the exposed SPAD electrode lead-out region 1051, the N well 1052, and the P well 106 to form the N active region 111 and the SPAD electrode contact region 112. The buried layer 103, the SPAD electrode contact region 112, and the SPAD electrode lead-out region constitute the SPAD cathode.

[0066] Step 10, such as Figure 12 As shown, a photoresist is deposited on the oxide layer 110 and patterned using a photolithography process to create an avalanche region pattern, exposing the oxide layer 110 below. The avalanche region pattern is located above the buried layer 103. The oxide layer 110 and gate oxide layer 107 are etched to expose the epitaxial layer 104. Germanium ions are implanted into the epitaxial layer 104 to form the avalanche region 113, and the photoresist is then removed. As shown in the figure, the avalanche region 113 consists of two parts: the first part is a layer of germanium-silicon material containing germanium atoms, and the second part is an epitaxial silicon material that contacts the buried layer 103 and is located below the first part. The avalanche region 113 is located between the SPAD electrode lead-out regions 1051.

[0067] Step 11, such as Figure 13 As shown, a diode doping region 114 is formed in the avalanche region 113 , and a P active region 115 is formed in the N well 1052 and the P well 106 .

[0068] Photoresist is deposited on the oxide layer 110 and the avalanche region 113, and the portion of the photoresist located above the N-well 1052 and the P-well 106 is removed by photolithography. The exposed oxide layer 110 and gate oxide layer 107 are etched to expose the N-well and P-well. The photoresist on the avalanche region 113 is then removed by photolithography to expose the avalanche region 113. P+ ions are then implanted into the exposed avalanche region, the N-well, and the P-well to form the diode doped region 114 and the P active region 115 of the SPAD. The diode doped region serves as the anode of the SPAD.

[0069] The diode doping region 114 serves as the anode of the SPAD and can be generated synchronously from the P active region in the CMOS process.

[0070] Step 12: annealing the avalanche region 113 and the P active region 115. In one embodiment of the present invention, the annealing temperature is 800-930°C and the annealing time is half an hour.

[0071] In another embodiment of the present invention, after ion implantation and annealing to form the N-well and P-well, germanium ions are implanted into the epitaxial layer above the buried layer without annealing. Ion implantation is then performed to form the N-active region, the diode doping region, and the P-active region, followed by a unified annealing at a temperature of 800-930°C.

[0072] Step 13, such as Figure 14 As shown, a first dielectric layer 116 and a second dielectric layer 117 are sequentially deposited to cover the oxide layer 110, the N active region 111, the SPAD electrode contact region 112, the diode doped region 114, and the P active region 115. The first dielectric layer 116 may be, for example, silicon dioxide, and the second dielectric layer 117 may be, for example, silicon nitride.

[0073] Step 14, such as Figure 15 As shown, the N active region 111, the SPAD electrode contact region 112, the diode doped region 114, the P active region 115, and the second dielectric layer 117 above the gate are removed. Specifically, a photoresist is coated on the second dielectric layer 117. After exposure and development, the photoresist located above the N active region 111, the SPAD electrode contact region 112, the diode doped region 114, the P active region 115, and the gate is removed. Then, the exposed second dielectric layer 117 is etched.

[0074] Step 15, such as Figure 16 and 17As shown, a metal line 119 is formed to connect the N active region 111, the SPAD electrode contact region 112, the diode doping region 114, the P active region 115 and the gate to obtain a light sensor.

[0075] Photoresist is coated on the second dielectric layer 117. After exposure and development, the photoresist located above the N active area 111, SPAD electrode contact area 112, P active area 115, and the gate, as well as the portion of photoresist located above the diode doped area 114, is removed. The exposed first dielectric layer 116 is then etched, and the oxide layer on the gate is etched to expose the N active area 111, SPAD electrode contact area 112, diode doped area 114, P active area 116, and the gate, forming a blind hole 118. A metal layer is formed in the blind hole 118 and on the surface of the second dielectric layer 117 by hole filling, sputtering, or evaporation. Then, photoresist is coated and patterned, and the metal layer not covered by the photoresist is etched to form a metal line 119 to achieve metal connection.

[0076] Optionally, in step 16, a passivation layer is deposited on the surface of the light sensor, and then a photoresist is coated and patterned, and finally the passivation layer on the metal wire is removed by etching.

[0077] In another embodiment of the present invention, the buried layer can be made into P+ type, the P well serves as the positive lead-out region of the SPAD, the P active serves as the positive contact region, and the diode doped region serves as the negative electrode, which has the same effect. The specific operation is as follows:

[0078] Step 2: perform P+ implantation on the exposed buried layer area of ​​the substrate to generate a P+ buried layer.

[0079] Step 4: Forming SPAD electrode lead-out regions and P-wells in the epitaxial layer. A photoresist is applied to the upper surface of the epitaxial layer and patterned using a photolithography process to form multiple P-well regions. P-type ion implantation and annealing are then performed on the epitaxial layer exposed in the multiple P-well regions to form the SPAD electrode lead-out regions and P-wells. The photoresist is then removed. The SPAD electrode lead-out regions serve as the positive lead-out regions.

[0080] Step 5: Form an N-well in the epitaxial layer. Place photoresist on the upper surface of the epitaxial layer and pattern the photoresist through photolithography to form an N-well region. Perform N-type ion implantation and annealing on the epitaxial layer exposed in the N-well region to form an N-well, and then remove the photoresist.

[0081] Step 9: Form a P active region in the N-well 1052 and the P-well 106, and a SPAD electrode contact region in the SPAD electrode lead-out region. Specifically, a photoresist is placed on the oxide layer and the portion of the photoresist located above the SPAD electrode lead-out region, the N-well, and the P-well is removed by photolithography. The exposed oxide layer and gate oxide layer are etched to expose the SPAD electrode lead-out region, the N-well, and the P-well. P+ ions are then implanted into the exposed SPAD electrode lead-out region, the N-well, and the P-well, followed by annealing to form a P active region and a SPAD electrode contact region. The buried layer, the SPAD electrode contact region, and the SPAD electrode lead-out region constitute the positive electrode.

[0082] Step 11: forming a diode doping region in the avalanche region and forming an N active region in the N well and the P well.

[0083] Photoresist is applied to the oxide layer and avalanche region, and the portion of photoresist above the N-well and P-well is removed by photolithography. The exposed oxide layer and gate oxide layer are etched to expose the N-well and P-well. The photoresist on the avalanche region is then removed by photolithography to expose the avalanche region. N+ ions are then implanted into the exposed avalanche region, N-well, and P-well to form the diode doping region and N active region of the SPAD. The diode doping region serves as the negative electrode of the SPAD.

[0084] In other embodiments of the present invention, the SPAD positive and negative electrodes and lead-out regions are not generated incompatiblely, and the sensor formed above can also have the same effect. For higher SPAD performance requirements, such as lower noise coefficient, an additional negative or positive lead-out region injection diffusion process can be added to reduce the lead-out region series resistance. Specific implementation:

[0085] After the N-well and P-well processes are completed, photoresist is applied and N+ or P+ implantation or diffusion is performed on the SPAD cathode lead-out area of ​​the N+ buried layer or the SPAD anode lead-out area of ​​the P+ buried layer. In other words, the N-well, P-well and SPAD electrode lead-out area are manufactured separately.

[0086] Figure 18 A cross-sectional schematic diagram of a light sensor in which a silicon-based CMOS and an avalanche diode are integrated in parallel according to an embodiment of the present invention is shown.

[0087] like Figure 18 As shown, the silicon-based CMOS optical sensor includes a substrate 201, an epitaxial layer 202, a single-photon avalanche diode (SPAD), and a silicon-based CMOS transistor circuit. The single-photon avalanche diode (SPAD) and the silicon-based CMOS transistor circuit are located in the same plane and connected by metal wires.

[0088] Epitaxial layer 202 is located on substrate 201. In one embodiment of the present invention, substrate 201 is a P-type silicon substrate, but may also be an N-type silicon substrate. If substrate 201 is a P-type substrate, epitaxial layer 202 is an N-type epitaxial layer (N-epitaxial layer). If it is an N-type substrate, epitaxial layer 202 is a P-type epitaxial layer (P-epitaxial layer).

[0089] The single photon avalanche diode SPAD includes a buried layer 203 , an avalanche region 204 , a diode doping region 205 , a SPAD electrode lead-out region 206 , and a SPAD electrode contact region 207 .

[0090] The buried layer 203 is an N+ buried layer formed by implanting N+ ions into the substrate and then diffusing them. The buried layer 203 serves as a charge (electric field) collection region of the SPAD.

[0091] The buried layer 203 is located between the substrate 201 and the epitaxial layer 202. The avalanche region 204 is located above the buried layer 203. The avalanche region 204 comprises two parts: a first part is a germanium silicon material layer containing germanium atoms, and a second part is an epitaxial silicon material that contacts the buried layer 103, the second part being located below the first part. In one embodiment of the present invention, the first part of the avalanche region 204 is formed by implanting germanium ions into the epitaxial layer. In one embodiment of the present invention, the thickness of the first part of the avalanche region 204 is 1 / 3, 1 / 4, etc., of the overall thickness of the avalanche region 204. The thickness of the avalanche region 204 is 2-6 μm to meet a bias voltage of 10V-100V.

[0092] The diode doping region 205 is located on the upper surface of the avalanche region 204. The diode doping region 205 can be formed by performing P+ ion implantation on the upper surface of the avalanche region 204. The diode doping region serves as the anode of the SPAD.

[0093] The SPAD electrode lead-out region 206 is located on both sides of the avalanche region 204 and above the buried layer 203. The SPAD electrode lead-out region 206 can also be located on one side or all four sides of the avalanche region. The SPAD electrode lead-out region contacts the buried layer, and the avalanche region contacts the buried layer.

[0094] The SPAD electrode lead-out region 206 can be formed by performing N-type ion implantation and diffusion (annealing) on ​​the epitaxial layer 202 .

[0095] The SPAD electrode contact region 207 is located on the upper surface of the SPAD electrode lead region 206. N+ ion implantation is performed on the upper surface of the SPAD electrode lead region 206 to form the SPAD electrode contact region 207. The buried layer 203, the SPAD electrode lead region 206, and the SPAD electrode contact region 207 constitute the negative electrode of the SPAD.

[0096] The silicon-based CMOS transistor circuit is located in the epitaxial layer 202 , and the silicon-based CMOS transistor circuit includes a silicon-based PMOS transistor circuit and a silicon-based NMOS transistor circuit.

[0097] The silicon-based NMOS transistor circuit includes a P-well 208, a P-active region 209, an N-active region 210, and a gate 2151. The P-active region 209 and the N-active region 210 are located on the upper surface of the P-well 208. The P-well 208 is located in the epitaxial layer 202 and is formed by implanting and diffusing P-type ions into a portion of the epitaxial layer. The P-active region 209 and the N-active region 210 are formed by implanting and diffusing P+ and N+ ions into the P-well 208. The gate 2151 is located above the epitaxial side 202, specifically above the P-well 208. The gate 2152 is made of polysilicon.

[0098] The silicon-based PMOS transistor circuit includes an N-well 211, a P-active region 212, an N-active region 213, and a gate 2152. The P-active region 212 and the N-active region 213 are located on the upper surface of the N-well 211. The N-well 211 is located in the epitaxial layer 202 and is formed by N-type ion implantation and diffusion into a portion of the epitaxial layer. P+ and N+ ion implantation and diffusion into the N-well 211 form the P-active region 212 and the N-active region 213. The gate 2152 is located above the epitaxial side 202, specifically above the N-well 211.

[0099] The metal line 214 is electrically connected to the diode doping region 205 , the SPAD electrode contact region 207 , the P active region 209 , the N active region 210 , the P active region 212 , the N active region 213 and the gate.

[0100] The photosensor further includes a gate oxide layer 216 located on the epitaxial side 202 .

[0101] The oxide layer 217 is located on the gate oxide layer 216 and covers the gate.

[0102] The first dielectric layer 218 is located on the oxide layer 217 and the diode doping region 205. The first dielectric layer 218 may be silicon dioxide.

[0103] The second dielectric layer 219 is located on the first dielectric layer 218. The second dielectric layer 219 may be silicon nitride.

[0104] Metal line 214 passes through second dielectric layer 219 , first dielectric layer 218 , oxide layer 217 , and gate oxide layer 216 to electrically connect to SPAD electrode contact region 207 , P active region, N active region, and gate. Metal line 214 passes through second dielectric layer 219 to electrically connect to diode doping region 205 .

[0105] In another embodiment of the present invention, the buried layer 203 is a P+ buried layer, which is formed by implanting P+ ions into the substrate and then diffusing them.

[0106] The diode doping region 205 serves as the negative electrode of the SPAD and is located on the upper surface of the avalanche region. The diode doping region can be formed by performing N+ ion implantation on the upper surface of the avalanche region.

[0107] By changing the type of doping ions, the negative electrode of the SPAD can be turned into a positive electrode.

[0108] The SPAD electrode lead-out region is located on both sides of the avalanche region 204 and above the buried layer 203. The SPAD electrode lead-out region can be formed by performing P-type ion implantation and diffusion (annealing) on ​​the epitaxial layer 202.

[0109] The SPAD electrode contact region is located on the upper surface of the SPAD electrode lead-out region. P+ ion implantation is performed on the upper surface of the SPAD electrode lead-out region to form the SPAD electrode contact region. P+ implantation is performed on the exposed substrate of the buried layer region to form a P+ buried layer.

[0110] The P+ buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the positive electrode of the SPAD.

[0111] also, Figure 18 The silicon-based CMOS transistor circuit and SPAD are only illustrated in terms of unit number, but an actual photosensor includes multiple SPADs arranged in an array and multiple silicon-based CMOS transistor circuits, which are combined to drive the SPAD.

[0112] The utility model has the following beneficial effects:

[0113] This utility model utilizes a silicon-based CMOS process and implants germanium ions into the silicon material, leveraging the properties of germanium to create an avalanche diode. This diode is then connected to auxiliary circuitry implemented in the same plane using the silicon-based CMOS process, achieving full sensor functionality on a single chip. The use of germanium increases the quantum absorption probability of mid-infrared waves, extending the infrared wavelength to 1550nm, broadening the application range of SPAD array sensors while avoiding the need for a dual-chip stacked package. This significantly improves yield and reliability, while significantly reducing costs.

[0114] Without compromising traditional CMOS processes, this new technology implants germanium ions into the epitaxial layer, leveraging the physical property of Ge (which absorbs infrared light better than silicon) to create a SPAD array directly connected to a silicon-based CMOS process. This technology leverages the respective strengths of both materials, improving performance over all-silicon SPADs, particularly significantly expanding the infrared wavelength range. It also avoids the high cost and low yield associated with multi-chip stacking, achieving single-chip packaging.

[0115] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided for illustrative purposes only. Numerous variations, alternatives, and improvements will be contemplated by those skilled in the art based on the teachings of this invention without departing from the scope of this invention. The appended claims are intended to define the scope of this invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A light sensor integrating silicon-based CMOS and avalanche diode, characterized in that: include: substrate; an epitaxial layer located on the substrate; One or more single-photon avalanche diodes (SPADs) located in the epitaxial layer, the single-photon avalanche diodes (SPADs) comprising: buried layer; an avalanche zone located above the buried layer; a diode doped region located on an upper surface of the avalanche region; A SPAD electrode lead-out region located above the buried layer and on one side, both sides, or all four sides of the avalanche region; A SPAD electrode contact region, which is located on the upper surface of the SPAD electrode lead-out region; One or more silicon-based CMOS transistor circuits are located in the epitaxial layer, wherein the single-photon avalanche diode and the CMOS transistor circuits are located in the same plane and are electrically connected.

2. The optical sensor with parallel integration of silicon-based CMOS and avalanche diode according to claim 1, characterized in that: The avalanche region includes a first portion and a second portion, wherein the first portion is located above the second portion and is a germanium silicon material layer.

3. The optical sensor according to claim 1, wherein When the diode doping region serves as the SPAD anode, it is formed by P-type ion doping, and the buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD cathode, all of which are formed by N-type ion doping; or When the diode doping region serves as the negative electrode of the SPAD, it is formed by N-type ion doping. The buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the positive electrode of the SPAD and are all formed by P-type ion doping.

4. The optical sensor with parallel integration of silicon-based CMOS and avalanche diode according to claim 1, characterized in that: The silicon-based CMOS transistor circuit comprises: A silicon-based PMOS transistor circuit comprising: N-well; gate; A P active region located on the upper surface of the N well; and an N active region located on an upper surface of the N well; and A silicon-based NMOS transistor circuit comprising: P-well; gate; A P active region, located on the upper surface of the P well; The N active region is located on the upper surface of the P well.

5. The optical sensor with parallel integration of silicon-based CMOS and avalanche diode according to claim 4, characterized in that: Also includes: a gate oxide layer located above the epitaxial layer and below the gate electrode; An oxide layer is located on the gate oxide layer and covers the gate.

6. The optical sensor with parallel integration of silicon-based CMOS and avalanche diode according to claim 5, characterized in that: Also includes: a first dielectric layer, which is located above the oxide layer and above the positive electrode structure; The second dielectric layer is located on the first dielectric layer.

7. The optical sensor with parallel integration of silicon-based CMOS and avalanche diode according to claim 5, characterized in that: It also includes metal lines, which are electrically connected to the P active area, the N active area, the gate, the diode doping area and the SPAD electrode contact area.

8. The optical sensor with parallel integration of silicon-based CMOS and avalanche diode according to claim 5, characterized in that: The buried layer is located in the substrate and the epitaxial layer.

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