Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device, the array substrate comprises a substrate body, a first metal layer, a first insulating layer and a first transparent electrode layer which are arranged in a stacked mode, and the substrate body is provided with a plurality of sub-pixels distributed in an array mode; the first metal layer comprises metal wires located between adjacent sub-pixels, the extension direction of the metal wires is a first direction, and the direction intersecting with the first direction is a second direction; the first transparent electrode layer comprises a first transparent electrode located in each sub-pixel, a first connecting part and a second connecting part, every two adjacent first transparent electrodes arranged in the second direction are electrically connected through the corresponding first connecting part, and every two adjacent first transparent electrodes arranged in the first direction are electrically connected through the corresponding second connecting part; the second connecting part is electrically connected with the metal wire through a first via hole penetrating through the first insulating layer; a first gap is formed in the position, corresponding to the first via hole, of the metal wire, and the orthographic projection of the first gap on the substrate covers the orthographic projection of part of the first via hole on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Utility Model Content

[0003] The present disclosure provides an array substrate, a display panel, and a display device for improving the pixel aperture ratio. The specific solution is as follows:

[0004] An embodiment of the present disclosure provides an array substrate having a plurality of sub-pixels distributed in an array, the array substrate comprising:

[0005] substrate;

[0006] a first metal layer located on one side of the base substrate, the first metal layer comprising metal lines located between adjacent sub-pixels, the metal lines extending in a first direction, and a direction intersecting the first direction being a second direction;

[0007] a first insulating layer, located on a side of the first metal layer facing away from the substrate;

[0008] A first transparent electrode layer is located on a side of the first insulating layer away from the base substrate, the first transparent electrode layer includes a first transparent electrode located in each sub-pixel and includes a first connecting portion and a second connecting portion, two adjacent first transparent electrodes arranged along the second direction are electrically connected via the first connecting portion, and two adjacent first transparent electrodes arranged along the first direction are electrically connected via the second connecting portion, and the second connecting portion is electrically connected to the metal wire via a first via hole penetrating the first insulating layer; wherein the metal wire has a first notch at a position corresponding to the first via hole, and the orthographic projection of the first notch on the base substrate partially covers the orthographic projection of the first via hole on the base substrate.

[0009] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the metal line includes a first part corresponding to the first via position and a second part corresponding to a position other than the first via position, the width of the first part along the second direction is greater than the width of the second part along the second direction, and the first part has the first notch.

[0010] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the area of ​​the first notch is less than 1 / 4 of the total area of ​​the first portion and the first notch.

[0011] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the orthographic projection of the inner wall of the first notch on the base substrate is in the shape of a broken line.

[0012] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the orthographic projection of the inner wall of the first notch on the base substrate is an arc.

[0013] In a possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the first via hole is equally divided into four first sub-via holes along the first direction and the second direction, and the orthographic projection of the first notch on the base substrate at least covers the orthographic projection of a partial area of ​​one of the first sub-via holes on the base substrate.

[0014] In a possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the first part further has a second notch, and the orthographic projection of the second notch on the base substrate at least covers the orthographic projection of another partial area of ​​the first sub-via on the base substrate.

[0015] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the first notch and the second notch are arranged opposite to each other.

[0016] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the first portion has a center point, and the first notch and the second notch are centrally symmetric about the center point.

[0017] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the first notch and the second notch are adjacently arranged.

[0018] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the metal line has a center line extending along the first direction, and the first notch and the second notch are symmetrically arranged about the center line.

[0019] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the area of ​​the second notch is the same as the area of ​​the first notch.

[0020] In a possible implementation, the array substrate provided in an embodiment of the present disclosure further includes a second metal layer located between the base substrate and the first metal layer, the second metal layer including a plurality of gate lines extending along the second direction and arranged along the first direction, the first metal layer also including a plurality of data lines extending along the first direction and arranged along the second direction, the data lines and the metal lines being alternately arranged between the sub-pixels in adjacent columns;

[0021] The plurality of gate lines and the plurality of data lines intersect to define the plurality of sub-pixels. The sub-pixels in the same row have different colors, and the sub-pixels in the same column have the same color. The sub-pixels in each row are electrically connected to two corresponding gate lines.

[0022] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the two gate lines electrically connected to the sub-pixels in the same row are respectively located on both sides of the sub-pixels, and there are two gate lines between two adjacent rows of sub-pixels.

[0023] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the orthographic projection of the first via hole on the base substrate is located between the orthographic projections of two gate lines between adjacent sub-pixels on the base substrate.

[0024] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the orthographic projection of the first portion on the base substrate is located between the orthographic projections of two gate lines between adjacent sub-pixels on the base substrate.

[0025] In a possible implementation, in the array substrate provided by an embodiment of the present disclosure, a width of a region of the second portion that overlaps with the gate line is greater than a width of a region of the second portion that does not overlap with the gate line.

[0026] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the two columns of the first transparent electrodes and the second connecting portions between two adjacent data lines are an integrated structure.

[0027] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the first transparent electrode layer further includes a third connection portion, and two adjacent second connection portions along the second direction are electrically connected via the third connection portion.

[0028] In a possible implementation, the array substrate provided in the embodiment of the present disclosure further includes: a second transparent electrode layer located between the second metal layer and the base substrate, a second insulating layer located between the second metal layer and the first metal layer, and an active layer located between the second insulating layer and the first metal layer; wherein,

[0029] The first metal layer also includes a source and a drain, the second transparent electrode layer includes a second transparent electrode located at each sub-pixel, and the first transparent electrode layer also includes a fourth connecting portion, which is electrically connected to the drain and the second transparent electrode respectively through a second via hole penetrating the first insulating layer and the second insulating layer, and the data line is electrically connected to the source.

[0030] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the active layer includes a channel portion electrically connected to the source and the drain, and a dummy portion located between the metal wire and the second insulating layer, the pattern of the dummy portion is the same as the pattern of the metal wire, and the dummy portion has a third notch at a position corresponding to the first notch.

[0031] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the first transparent electrode is a common electrode, and the first transparent electrode includes a plurality of slits;

[0032] The second transparent electrode is a pixel electrode, and the second transparent electrode is a planar electrode.

[0033] Correspondingly, an embodiment of the present disclosure further provides a display panel, comprising: the above-mentioned array substrate provided in an embodiment of the present disclosure, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

[0034] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure.

[0035] The beneficial effects of the embodiments of the present disclosure are as follows:

[0036] An array substrate, a display panel, and a display device provided by the embodiments of the present disclosure are configured such that a first notch is provided on a metal line, and a portion of a first via hole for connecting a first transparent electrode layer and the metal line is overlapped on the first notch, and the other portion is overlapped on the metal line, i.e., the first via hole is formed on the metal line in a semi-overlap manner. A plurality of step buffer structures can be formed at the first notch. When PI liquid is applied, when the PI liquid passes through the first via hole, the terrain at the location of the first via hole is relatively flat, which guides the flow of the PI liquid, thereby improving the PI fluidity and facilitating the diffusion of the PI liquid toward the first via hole, thereby preventing the PI liquid from gathering at the first via hole, improving the problem of uneven PI diffusion, and thus avoiding the problem of uneven pixel display (mura), thereby improving the product yield of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a Dual Gate pixel architecture for an LCD array substrate;

[0038] Figure 2 For the corresponding Figure 1 Schematic diagram of the layout of some sub-pixels in the middle;

[0039] Figure 3 for Figure 2 A partial enlarged schematic diagram;

[0040] Figure 4 for Figure 3 An enlarged schematic diagram of the position of the first via hole in FIG.

[0041] Figure 5 for Figure 4 Schematic diagram of the cross section of part of the film layer along the AA' direction;

[0042] Figure 6 The embodiment of the present disclosure provides Figure 1 A schematic diagram of the layout of the sub-pixels in the middle;

[0043] Figure 7 for Figure 6 A partial enlarged schematic diagram;

[0044] Figure 8 for Figure 7 A partial enlarged schematic diagram;

[0045] Figure 9 for Figure 8Schematic diagram of the cross section along CC' direction;

[0046] Figure 10 for Figure 8 Schematic diagram of the cross section along the FF' direction;

[0047] Figure 11 for Figure 8 An enlarged schematic diagram of the position of the first via hole in FIG.

[0048] Figure 12 for Figure 11 Schematic diagram of the cross section along the AA' direction;

[0049] Figure 13 for Figure 11 A local enlarged schematic diagram in FIG.

[0050] Figure 14 Another partially enlarged schematic diagram of a metal wire provided in an embodiment of the present disclosure;

[0051] Figure 15 Another partially enlarged schematic diagram of a metal wire provided in an embodiment of the present disclosure;

[0052] Figure 16 Another partially enlarged schematic diagram of a metal wire provided in an embodiment of the present disclosure;

[0053] Figure 17 for Figure 6 A local enlarged schematic diagram in FIG.

[0054] Figure 18 The embodiment of the present disclosure provides Figure 1 Another layout diagram of the middle sub-pixel;

[0055] Figure 19 for Figure 18 A partial enlarged schematic diagram;

[0056] Figure 20 A schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0059] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] As used in this disclosure, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 10% of either one.

[0061] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0062] The present disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0063] In the present disclosure, circles, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0064] An LCD display panel generally includes an array substrate and a counter substrate (i.e., a color film substrate) arranged opposite to each other, and a liquid crystal layer located between the array substrate and the counter substrate. A liquid crystal alignment layer is provided on both the side of the array substrate facing the liquid crystal layer and the side of the counter substrate facing the liquid crystal layer. The liquid crystal alignment layer can be a polyimide film, referred to as PI film.

[0065] As liquid crystal display technology continues to mature, LCD array substrates have gradually developed towards low cost and low power consumption. Currently, array substrates are driven in a time-sharing manner by adding gate drive circuits (GOA) and gate lines to reduce the number of data line (Data) signal channels, thereby reducing the number of driver chips (IC) used. However, the increase in gate lines will inevitably reduce the pixel aperture ratio. Therefore, in order to reduce costs and not sacrifice too much aperture ratio, the more commonly used pixel architecture is Dual Gate (dual gate, each row of pixel units is driven by two rows of gate lines). Figure 1 As shown, Figure 1 This is a schematic diagram of a dual-gate pixel architecture for an LCD array substrate. The array substrate includes multiple gate lines (G1, G2, ...) and multiple data lines (D1, D2, ...). The gate and data lines are insulated and intersected to define multiple pixel units arranged in an array. Each pixel unit includes multiple sub-pixels with different color-resistance colors. Optionally, each pixel unit includes three sub-pixels with color-resistance colors of red (R), green (G), and blue (B). Red, green, and blue are the basic colors in the display field. By varying the red, green, and blue color channels and superimposing them, a variety of colors can be generated, thus achieving full-color display.

[0066] Specifically, if Figure 2 and Figure 3As shown, Figure 2 for Figure 1 Schematic diagram of the layout of some sub-pixels in the middle. Figure 3 for Figure 2 The locally enlarged schematic diagram shows that the array substrate includes a base substrate 1, a gate metal layer (Gate, represented by G), a gate insulating layer (GI), an active layer (Act), a source-drain metal layer (SD), a passivation layer (PVX), and a double-layer ITO electrode layer, wherein one ITO electrode layer serves as a pixel electrode layer and the other ITO electrode layer serves as a common electrode layer. In order to reduce the number of masks used in the production of the array substrate, the lower ITO electrode layer (hereinafter referred to as 1ITO) can be produced using a single mask process with the gate metal layer (Gate), such as using a halftone mask (HTM) technology, with 1ITO being directly located below the gate metal layer (Gate); the active layer (Act) and the source-drain metal layer (SD) can be produced using a single mask process, such as using a halftone mask (HTM) technology, with the active layer (Act) being directly located below the source-drain metal layer (SD). Specifically, 1ITO can be used as a pixel electrode layer, and the upper ITO electrode layer (hereinafter referred to as 2ITO) is used as a common electrode layer. The common electrode layer is located above the source and drain metal layer. The pixel electrode layer includes multiple independent pixel electrodes P, and the common electrode layer includes multiple independent common electrodes com. The pixel electrodes P correspond one-to-one to the sub-pixels, and the common electrodes com correspond one-to-one to the sub-pixels. In order to ensure the common signal uniformity (com uniformity) of the entire LCD display panel, adjacent common electrodes com in the row direction are generally connected together through 2ITO, and adjacent common electrodes com in the column direction are connected together through 2ITO to improve the uniformity of the common signal. Due to the large resistance of ITO (square resistivity Rs = 31Ω), if only the adjacent common electrodes com in the row / column direction are connected through 2ITO, the uniformity of the common signal is poor, and the panel display will appear green.

[0067] Specifically, if Figure 1-Figure 3As shown, since the pixel architecture adopts Dual Gate, the number of data lines can be reduced by half compared with the traditional SingleGate pixel architecture. In this way, metal lines (D1', D2'...) set on the same layer as the data lines (D1, D2...) can be set between two adjacent columns of sub-pixels where no data lines are set, and the 2ITO electrically connected to the adjacent common electrodes com in the column direction is electrically connected to the metal lines (D1', D2'...) through the first via V1 penetrating PVX. Since the material of the data line is generally Cu, the resistance is relatively small (square resistivity Rs = 0.075Ω), so electrically connecting the common electrode layer with the metal line can reduce the resistance of the common electrode com, which is beneficial to improving the uniformity of the common signal and preventing the panel display from appearing green.

[0068] like Figure 4 As shown, Figure 4 for Figure 3 The enlarged schematic diagram of the position of the first via hole V1 in the display is shown. The common electrode layer (2ITO) is electrically connected to the metal lines (D1', D2'...) below through the first via hole V1. Since there is one first via hole V1 between every two sub-pixels in the column direction, multiple first via holes V1 are distributed in an array in the display area. In the actual production process, the inventors of this disclosure found that the first via hole V1 of PVX is not conducive to the diffusion of PI liquid. Figure 5 As shown, Figure 5 for Figure 4 A schematic cross-sectional view of part of the film layer along the AA' direction shows that due to the surface tension of the PI liquid itself, the PI liquid will accumulate around the first via V1. The PI closer to the first via V1 is thicker, and the PI farther away from the first via V1 is thinner. This will cause display problems such as uneven pixel display (mura), resulting in loss of product yield.

[0069] The present disclosure provides an array substrate, such as Figure 1 、 Figure 6-Figure 12 As shown, Figure 6 for Figure 1 Schematic diagram of the layout of some sub-pixels in the middle. Figure 7 for Figure 6 A partial enlarged schematic diagram, Figure 8 for Figure 7 A partial enlarged schematic diagram, Figure 9 for Figure 8 Schematic diagram of the cross section along CC' direction, Figure 10 for Figure 8 Schematic diagram of the cross section along the FF' direction, Figure 11 for Figure 8 An enlarged schematic diagram of the position of the first via V1 in FIG. Figure 12 for Figure 11The cross-sectional view along the AA' direction in FIG. 1 shows an array substrate having a plurality of sub-pixels P distributed in an array. The array substrate includes:

[0070] Base substrate 1;

[0071] A first metal layer 2 is located on one side of the base substrate 1. The first metal layer 2 includes metal lines (D1', D2', ...) located between adjacent sub-pixels. The metal lines (D1', D2', ...) extend in a first direction Y, and a direction intersecting the first direction Y is a second direction X.

[0072] A first insulating layer 3 is located on a side of the first metal layer 2 facing away from the substrate 1;

[0073] The first transparent electrode layer 4 is located on the side of the first insulating layer 3 facing away from the base substrate 1. The first transparent electrode layer 4 includes a first transparent electrode 41 located in each sub-pixel and a first connecting portion 42 and a second connecting portion 43. Two adjacent first transparent electrodes 41 arranged along the second direction X are electrically connected via the first connecting portion 42, and two adjacent first transparent electrodes 41 arranged along the first direction Y are electrically connected via the second connecting portion 43. The second connecting portion 43 is electrically connected to the metal line (D1', D2'...) via a first via hole V1 penetrating the first insulating layer 3; wherein the metal line (D1', D2'...) has a first notch H1 at a position corresponding to the first via hole V1, and the orthographic projection of the first notch H1 on the base substrate 1 partially covers the orthographic projection of the first via hole V1 on the base substrate 1.

[0074] Specifically, the first metal layer 2 is a source-drain metal layer (SD), the first transparent electrode layer 4 is a common electrode layer (2ITO), that is, the first transparent electrode 41 is a common electrode com, and the first insulating layer 3 can be a passivation layer (PVX).

[0075] The array substrate provided by the embodiment of the present disclosure provides a first notch on the metal wire, and overlaps a portion of the first via hole for connecting the first transparent electrode layer and the metal wire on the first notch, and overlaps the other portion on the metal wire, that is, the first via hole is formed on the metal wire in a semi-overlap manner, and multiple step buffer structures can be formed at the first notch. When PI liquid is coated, when the PI liquid passes through the first via hole, the terrain at the location of the first via hole is relatively flat, which has a guiding effect on the flow of the PI liquid, making the PI fluidity better and facilitating the diffusion of the PI liquid toward the first via hole, thereby preventing the PI liquid from gathering at the first via hole, improving the problem of uneven PI diffusion, thereby avoiding the problem of uneven pixel display (mura), and improving the product yield of the array substrate.

[0076] In the above array substrate provided in some embodiments of the present disclosure, Figure 6-Figure 8 、 Figure 11 and Figure 12 As shown, the metal lines (D1', D2', ...) include a first portion 21 corresponding to the location of the first via V1 and a second portion 22 corresponding to locations other than the first via V1. The width of the first portion 21 along the second direction X is greater than the width of the second portion 22 along the second direction X. The first portion 21 has a first notch H1. Specifically, the size of the second connecting portion 43 corresponding to the location of the first via V1 is substantially the same as the size of the first portion 21, thereby ensuring that the second connecting portion 43 is electrically connected to the first portion 21 through the first via V1. The width of the second portion 22 is greater than the width of the second connecting portion 43 corresponding to locations other than the first via V1. For example, the width of the second connecting portion 43 corresponding to locations other than the first via V1 is 5.5 μm, while the width of the second portion 22 is 8 μm. A larger line width reduces resistance, and a larger width of the second portion 22 helps reduce the resistance of the common electrode com, improves the uniformity of the common signal, and prevents the panel display from showing a green tint.

[0077] In the above array substrate provided in some embodiments of the present disclosure, Figure 6-Figure 12 As shown, it also includes: a second metal layer 5 located between the base substrate 1 and the first metal layer 2, a second transparent electrode layer 6 located between the second metal layer 5 and the base substrate 1, a second insulating layer 7 located between the second metal layer 5 and the first metal layer 2, and an active layer 8 (Act) located between the second insulating layer 7 and the first metal layer 2; specifically, the second metal layer 5 is a gate metal layer (Gate), the second transparent electrode layer 6 is a pixel electrode layer (1ITO), and the second insulating layer 7 is a gate insulating layer (GI).

[0078] Specifically, in order to save masks and reduce production costs, the second transparent electrode layer 6 and the second metal layer 5 can be produced using a mask process, that is, the second transparent electrode layer 6 and the second metal layer 5 can be produced using a halftone mask (HTM) technology.

[0079] Specifically, in order to save masks and reduce manufacturing costs, the first metal layer 2 and the active layer 8 can be manufactured using a mask process, that is, the first metal layer 2 and the active layer 8 can be manufactured using a halftone mask (HTM) technology.

[0080] In the above array substrate provided in some embodiments of the present disclosure, Figure 6-Figure 8 、 Figure 11 、 Figure 13 and Figure 14 As shown, Figure 13 for Figure 11 A local enlarged schematic diagram of Figure 14Another partially enlarged schematic diagram of the metal wire provided in the embodiment of the present disclosure. If the area of ​​the first notch H1 is too small, it is easy for the first notch H1 to not cover the first via V1. If the area of ​​the first notch H1 is too large, it is easy for the metal wire to break. Therefore, the present disclosure sets the area of ​​the first notch H1 to be less than 1 / 4 of the total area of ​​the first portion 21 and the first notch H1. Specifically, the total area of ​​the first portion 21 and the first notch H1 is Figure 4 The area of ​​the metal wire block pattern corresponding to the first via hole V1 in the present disclosure is Figure 4 A first gap H1 is formed by removing a portion of the square pattern of the metal wire corresponding to the first via V1 that is less than 1 / 4 of its area. The orthographic projection of the first gap H1 on the base substrate 1 covers the orthographic projection of a corner of the first via V1 on the base substrate 1. This allows the PI liquid to flow in relatively gentle terrain, and can better solve the problem of PI liquid gathering at the first via V1.

[0081] In the above array substrate provided in some embodiments of the present disclosure, Figure 6-Figure 8 、 Figure 11 and Figure 13 As shown, the orthographic projection of the inner wall of the first notch H1 on the base substrate 1 may be in the shape of a broken line; Figure 14 As shown, the orthographic projection of the inner wall of the first notch H1 on the base substrate 1 may be an arc; of course, it is not limited thereto.

[0082] In the above array substrate provided in some embodiments of the present disclosure, Figure 11 and Figure 12 As shown, the first via hole V1 is equally divided into four first sub-via holes V11 along the first direction Y and the second direction X, and the orthographic projection of the first notch H1 on the base substrate 1 at least covers the orthographic projection of a portion of one of the first sub-via holes V11 on the base substrate 1. Optionally, the shape of the first via hole V1 can be square, circular, elliptical, etc. The embodiment of the present disclosure takes a square hole as an example, and the orthographic projection of the first notch H1 on the base substrate 1 covers the orthographic projection of the upper right corner of the first via hole V1 on the base substrate 1. In this way, the PI liquid can flow in relatively gentle terrain, which can better solve the problem of PI liquid gathering at the first via hole V1. Specifically, Figure 11 The cross-sectional structure of the membrane layer at positions ①, ②, ③, ④, ⑤, ⑥, and ⑦ is as follows: Figure 12 As shown, the specific cross-sectional structure of the membrane layer is as follows:

[0083] ① There is a substrate 1 / 1ITO / Gate / GI / Act / SD / PVX / 2ITO at the location, which is at a higher altitude;

[0084] Position ② has substrate 1 / GI / Act / SD / PVX / 2ITO, which is slightly lower than position ①.

[0085] Position ③ has substrate 1 / GI / PVX / 2ITO, and the terrain is lower than position ②;

[0086] At position ④, there is substrate 1 / GI / 2ITO, and the terrain is lower than that at position ③;

[0087] At position ⑤, there is substrate 1 / GI / Act / SD / 2ITO, and the terrain is higher than that at position ④;

[0088] At position ⑥, there is substrate 1 / GI / Act / SD / PVX / 2ITO, which is higher than position ⑤;

[0089] At position ⑦, there is substrate 1 / 1ITO / Gate / GI / Act / SD / PVX / 2ITO, which is located at a higher altitude.

[0090] As can be seen from the terrain at positions ①, ②, ③, ④, ⑤, ⑥, and ⑦, the PI passes through the first via V1 through multiple steps, which guide its flow. The PI is buffered by the terrain, which alternates between high and low, causing it to descend and then climb. Because the terrain, which descends from high to low and then rises again, is relatively flat, it guides the flow of the PI, improving its fluidity and preventing PI accumulation at the first via V1, which can cause pixel display unevenness (mura), thereby improving the product yield of the array substrate.

[0091] In the above array substrate provided in some embodiments of the present disclosure, Figure 15 and Figure 16 As shown, the first portion 21 may also have a second notch H2, the orthographic projection of the second notch H2 on the base substrate 1 covering at least a portion of the orthographic projection of another first sub-via V11 (e.g., the upper left corner or lower left corner of the square hole) on the base substrate 1. By forming two notches in the first portion 21 of the metal line (D1', D2', ...), a large-area high-low buffer terrain can be formed at the location of the first via V1, improving the PI fluidity and forming a uniform PI film.

[0092] In the above array substrate provided in some embodiments of the present disclosure, Figure 15 As shown, the first notch H1 and the second notch H2 can be arranged relative to each other, that is, the orthographic projection of the second notch H2 on the base substrate 1 overlaps the orthographic projection of the lower left corner of the first via V1 on the base substrate 1. Optionally, the first portion 21 has a center point A, and the first notch H1 and the second notch H2 are centrally symmetrical about the center point A. In this embodiment, the orthographic projections of the inner walls of the first notch H1 and the second notch H2 on the base substrate 1 are zigzag shapes. Of course, the orthographic projections of the inner walls of the first notch H1 and the second notch H2 on the base substrate 1 can also be other shapes such as arcs.

[0093] In the above array substrate provided in some embodiments of the present disclosure, Figure 16 As shown, the first notch H1 and the second notch H2 can be arranged adjacent to each other, that is, the orthographic projection of the second notch H2 on the base substrate 1 covers the orthographic projection of the upper left corner of the first via V1 on the base substrate 1; optionally, the metal lines (D1', D2', ...) have a center line L extending along the first direction Y, and the first notch H1 and the second notch H2 can be arranged symmetrically about the center line L. This embodiment takes the orthographic projections of the inner walls of the first notch H1 and the second notch H2 on the base substrate 1 as an example, and of course, the orthographic projections of the inner walls of the first notch H1 and the second notch H2 on the base substrate 1 can also be other shapes such as a broken line.

[0094] In the above array substrate provided in some embodiments of the present disclosure, Figure 15 and Figure 16 As shown, the area of ​​the second notch H2 can be the same as the area of ​​the first notch H1; of course, they can also be different, as long as the orthographic projections of the first notch H1 and the second notch H2 on the base substrate 1 respectively cover the orthographic projections of one corner of the first via V1 on the base substrate 1.

[0095] It should be noted that the embodiment of the present disclosure takes the first part 21 of the metal wire having one notch or two notches as an example. Of course, the first part 21 can also have three notches or four notches, as long as the metal retained between two adjacent notches does not cause the metal wire to break. The principle of improving the flow of PI liquid by three notches or four notches is similar to that of one notch or two notches, and a gentler terrain can be achieved from different directions.

[0096] It should be noted that, in the above-mentioned array substrate provided in some embodiments of the present disclosure, the shape of the first via hole V1 is square as an example. When the shape of the first via hole V1 is circular or elliptical, when the first part 21 only includes the first notch H1, the orthographic projection of the first notch H1 on the base substrate 1 can cover the orthographic projection of 1 / 4 of the circular or elliptical hole on the base substrate 1; when the first part 21 includes the first notch H1 and the second notch H2, the orthographic projection of the first notch H1 on the base substrate 1 can cover the orthographic projection of one of the areas smaller than 1 / 4 of the circular or elliptical hole on the base substrate 1, and the orthographic projection of the second notch H2 on the base substrate 1 can cover the orthographic projection of the other area smaller than 1 / 4 of the circular or elliptical hole on the base substrate 1.

[0097] In the above array substrate provided in some embodiments of the present disclosure, Figure 1 、 Figure 6-Figure 8As shown, the second metal layer 6 includes a plurality of gate lines (G1, G2, ...) extending along the second direction X and arranged along the first direction Y, and the first metal layer 2 also includes a plurality of data lines (D1, D2, ...) extending along the first direction Y and arranged along the second direction X. The data lines (D1, D2, ...) and the metal lines (D1', D2', ...) are alternately arranged between adjacent columns of sub-pixels;

[0098] Multiple gate lines (G1, G2...) and multiple data lines (D1, D2...) intersect to define multiple sub-pixels. The colors of the sub-pixels in the same row are different (for example, the same row is arranged in RGBRGBRGB...), and the colors of the sub-pixels in the same column are the same. Each row of sub-pixels is electrically connected to two gate lines, that is, the pixel architecture of the embodiment of the present disclosure is dual gate, and dual gate drive can reduce power consumption and cost. An array substrate using Dual Gate technology can save half the number of data lines compared to an array substrate using Single Gate technology. In this way, metal lines (D1', D2'...) set on the same layer as the data lines (D1, D2...) can be set between two adjacent columns of sub-pixels where no data lines (D1, D2...) are set. The second connecting portion 43 connecting the adjacent first transparent electrodes 41 in the first direction Y is electrically connected to the metal lines (D1', D2'...) through the first via V1 penetrating PVX. Since the material of the data line is generally Cu, the resistance is relatively small (square resistivity Rs = 0.075Ω). Therefore, electrically connecting the common electrode layer to the metal line can reduce the resistance of the common electrode com, which is beneficial to improving the uniformity of the common signal, preventing the panel display from appearing green, and effectively preventing display defects such as flickering on the panel.

[0099] In the above array substrate provided in some embodiments of the present disclosure, Figure 1 、 Figure 6-Figure 8 As shown, two gate lines (G3 and G4) electrically connected to the same row of sub-pixels (e.g., the second row of sub-pixels) are respectively located on both sides of the sub-pixels (the second row of sub-pixels), and there are two gate lines (G2 and G3) between two adjacent rows of sub-pixels (e.g., the first row of sub-pixels and the second row of sub-pixels);

[0100] The orthographic projection of the first via hole V1 on the substrate 1 is located between the orthographic projections of two gate lines (G4 and G5) between adjacent sub-pixels (for example, the second and third rows of sub-pixels) on the substrate 1, and the orthographic projection of the first portion 21 on the substrate 1 is located between the orthographic projections of two gate lines (G4 and G5) between adjacent sub-pixels (for example, the second and third rows of sub-pixels) on the substrate 1, which is conducive to forming Figure 12 The high and low buffer terrains ①, ②, ③, ④, ⑤, ⑥, and ⑦ shown are conducive to the flow of PI liquid and form a uniform PI film.

[0101] In the above array substrate provided in some embodiments of the present disclosure, Figure 17 As shown, Figure 17 for Figure 6 In the partially enlarged schematic diagram, the width W2 of the second portion 22 overlapping the gate line (e.g., G4) is greater than the width W1 of the second portion 22 not overlapping the gate line (e.g., G4). This is because the film thickness in the area with the gate line is higher, and the second portion 22 needs to climb when crossing the gate line. To prevent the risk of the second portion 22 breaking when climbing, the width W2 of the second portion 22 overlapping the gate line (e.g., G4) can be set to be greater than the width W1 of the second portion 22 not overlapping the gate line (e.g., G4).

[0102] Specifically, if Figure 17 As shown, the width W4 of the non-notch position of the first portion 21 is greater than the width W3 of the notch position, and W3 can be set to be greater than W2, which can also prevent the metal line from climbing and breaking at the gate line position.

[0103] In the above array substrate provided in some embodiments of the present disclosure, Figure 1 and Figure 6 As shown, the two columns (the second column and the third column) of the first transparent electrodes 41 and the second connecting portion 43 between two adjacent data lines (for example, D1 and D2) can be an integral structure. This is because no data line is set between the two columns of the first transparent electrodes 41 between two adjacent data lines (for example, D1 and D2). Therefore, the two columns of the first transparent electrodes 41 of the integral structure will not have the problem of overlapping capacitance with the data lines, and the integral structure can further improve the uniformity of the common signal.

[0104] In the above array substrate provided in some embodiments of the present disclosure, Figure 18 and Figure 19 As shown, Figure 19 for Figure 18 In the partially enlarged schematic diagram, the first transparent electrode layer 4 further includes a third connecting portion 44, and two adjacent second connecting portions 43 along the second direction X are electrically connected via the third connecting portion 44. In this way, the second connecting portions 43 are connected via the third connecting portion 44 in the horizontal direction, which can further increase the uniformity of the common signal.

[0105] In the above array substrate provided in some embodiments of the present disclosure, Figure 6-Figure 8 、 Figure 10 and Figure 18As shown, the first metal layer 2 further includes a source electrode S and a drain electrode D, the second transparent electrode layer 6 includes a second transparent electrode 61 (i.e., a pixel electrode) located in each sub-pixel, and the first transparent electrode layer 4 further includes a fourth connecting portion 45. The fourth connecting portion 45 is electrically connected to the drain electrode D and the second transparent electrode 61, respectively, through a second via hole V2 penetrating the first insulating layer 3 and the second insulating layer 7. The data lines (D1, D2, ...) are electrically connected to the source electrode S. In addition, the second metal layer 6 further includes a gate electrode G electrically connected to the gate line. The gate electrode G, the source electrode S, the drain electrode D, and the active layer (Act) constitute a thin film transistor. In this way, the drain electrode D and the second transparent electrode 61 are electrically connected via the fourth connecting portion 45, thereby realizing independent driving of each sub-pixel.

[0106] In the above array substrate provided in some embodiments of the present disclosure, Figure 6 、 Figure 9 、 12 and Figure 18 As shown, the active layer 8 includes a channel portion 81 electrically connected to the source S and the drain D, and a dummy portion 82 located between the metal wires (D1', D2'...) and the second insulating layer 7. The pattern of the dummy portion 82 is consistent with the metal wires.

[0107] The patterns of the dummy portion 82 (D1', D2', ...) are identical, and the dummy portion 82 has a third notch at the position corresponding to the first notch H1. Specifically, because the active layer 8 and the first metal layer 2 are fabricated using the HTM process, the first metal layer 2 and the active layer 8 can be etched using the same mask, forming the dummy portion 82 and the metal lines (D1', D2', ...) with the same patterns.

[0108] In the above array substrate provided in some embodiments of the present disclosure, Figure 6 and Figure 18 As shown, the first transparent electrode 41 is a common electrode, and the first transparent electrode 41 may include a plurality of slits; the second transparent electrode 61 is a pixel electrode, and the second transparent electrode 61 may be a planar electrode.

[0109] Optionally, the material of the active layer may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (such as indium gallium zinc oxide IGZO), etc.

[0110] Specifically, if Figure 6 and Figure 18As shown, multiple sub-pixels emit different colors. For example, the multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel emits red (R), the second sub-pixel emits green (G), and the third sub-pixel emits blue (B). RGB is the basic color scheme in the display field. A variety of colors are generated by varying the three color channels R, G, and B and superimposing them, thereby achieving full-color display.

[0111] Optionally, the material of the first insulating layer and the second insulating layer may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0112] Optionally, materials of the first transparent electrode layer and the second transparent electrode layer respectively include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0113] Optionally, the material of the first metal layer may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The first metal layer may be a single-layer structure or a stacked structure. For example, the first metal layer is a stacked structure consisting of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0114] Optionally, the material of the second metal layer may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., and the second metal layer may be a single-layer structure or a stacked-layer structure. For example, the second metal layer is a single-layer structure composed of a molybdenum metal layer.

[0115] It should be noted that other essential components of the array substrate should be understood by those skilled in the art and will not be described in detail here, nor should they be considered as limitations of the present disclosure.

[0116] Based on the same utility model concept, the embodiment of the present disclosure further provides a display panel, comprising: the above-mentioned array substrate provided by the embodiment of the present disclosure, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

[0117] Specifically, the opposing substrate in the embodiment of the present disclosure can be a color filter substrate, on which a black matrix (BM) and multiple filters are provided; the BM is arranged in the gap between adjacent sub-pixels. On the one hand, the BM is used to limit multiple sub-pixels to avoid light crosstalk between adjacent sub-pixels. On the other hand, the BM is used to block metal signal lines, such as gate lines, data lines, etc., to prevent metal signal lines from being reflected and reduce the reflectivity of the display area; specifically, the BM includes openings corresponding one-to-one to the sub-pixels, and each filter is arranged in the corresponding opening. The multiple filters may include a red filter (such as a red color filter), a green filter (such as a green color filter) and a blue filter (such as a blue color filter).

[0118] Based on the same utility model concept, the present disclosure also provides a display device including the display panel provided in the present disclosure. Because the principles underlying the display device and the display panel are similar, the implementation of the display device provided in the present disclosure can refer to the implementation of the display panel, and any repetitions will not be repeated.

[0119] In some embodiments, the display device provided in the embodiments of the present disclosure further includes a backlight module located on the light incident side of the array substrate.

[0120] In some embodiments, in the above-mentioned display device provided in the embodiments of the present disclosure, the backlight module can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a reflective sheet stacked, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser and a brightening film, etc., and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0121] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0122] In specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure is a liquid crystal display device, which also includes other necessary components and components, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device. They will not be elaborated here and should not be regarded as a limitation to the present disclosure.

[0123] In specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a full-screen display device, or may be a flexible display device, etc., which is not limited here.

[0124] In specific implementation, the display device provided by the embodiment of the present disclosure may be as follows: Figure 20 The full-screen mobile phone shown. Of course, the above-mentioned display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. As for the other indispensable components of the display device, those skilled in the art should understand that they have them, and will not be elaborated here, nor should they be used as limitations on the present disclosure. The display device includes but is not limited to components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. In addition, it will be understood by those skilled in the art that the above-mentioned structure does not constitute a limitation on the above-mentioned display device provided in the embodiment of the present disclosure. In other words, the above-mentioned display device provided in the embodiment of the present disclosure may include more or fewer of the above-mentioned components, or a combination of certain components, or different component arrangements.

[0125] An array substrate, a display panel, and a display device provided by the embodiments of the present disclosure are configured such that a first notch is provided on a metal line, and a portion of a first via hole for connecting a first transparent electrode layer and the metal line is overlapped on the first notch, and the other portion is overlapped on the metal line, i.e., the first via hole is formed on the metal line in a semi-overlap manner. A plurality of step buffer structures can be formed at the first notch. When PI liquid is applied, when the PI liquid passes through the first via hole, the terrain at the location of the first via hole is relatively flat, which guides the flow of the PI liquid, thereby improving the PI fluidity and facilitating the diffusion of the PI liquid toward the first via hole, thereby preventing the PI liquid from gathering at the first via hole, improving the problem of uneven PI diffusion, and thus avoiding the problem of uneven pixel display (mura), thereby improving the product yield of the array substrate.

[0126] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0127] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate having a plurality of sub-pixels distributed in an array, wherein: The array substrate includes: substrate; a first metal layer located on one side of the base substrate, the first metal layer comprising metal lines located between adjacent sub-pixels, the metal lines extending in a first direction, and a direction intersecting the first direction being a second direction; a first insulating layer, located on a side of the first metal layer facing away from the substrate; A first transparent electrode layer is located on a side of the first insulating layer away from the base substrate, the first transparent electrode layer includes a first transparent electrode located in each sub-pixel and includes a first connecting portion and a second connecting portion, two adjacent first transparent electrodes arranged along the second direction are electrically connected via the first connecting portion, and two adjacent first transparent electrodes arranged along the first direction are electrically connected via the second connecting portion, and the second connecting portion is electrically connected to the metal wire via a first via hole penetrating the first insulating layer; wherein the metal wire has a first notch at a position corresponding to the first via hole, and the orthographic projection of the first notch on the base substrate partially covers the orthographic projection of the first via hole on the base substrate.

2. The array substrate according to claim 1, wherein: The metal line includes a first portion corresponding to the first via position and a second portion corresponding to a position other than the first via position. The width of the first portion along the second direction is greater than the width of the second portion along the second direction. The first portion has the first gap.

3. The array substrate according to claim 2, wherein: The area of ​​the first gap is smaller than 1 / 4 of the total area of ​​the first portion and the first gap.

4. The array substrate according to claim 3, wherein: The orthographic projection of the inner wall of the first notch on the base substrate is in the shape of a broken line.

5. The array substrate according to claim 3, wherein: The orthographic projection of the inner wall of the first notch on the base substrate is an arc.

6. The array substrate according to any one of claims 2 to 5, wherein: The first via hole is equally divided into four first sub-via holes along the first direction and the second direction, and the orthographic projection of the first notch on the base substrate at least covers the orthographic projection of a partial area of ​​one of the first sub-via holes on the base substrate.

7. The array substrate according to claim 6, wherein: The first portion further has a second notch, and an orthographic projection of the second notch on the base substrate at least covers an orthographic projection of a partial area of ​​another first sub-via hole on the base substrate.

8. The array substrate according to claim 7, wherein: The first notch and the second notch are arranged opposite to each other.

9. The array substrate according to claim 8, wherein: The first portion has a center point, and the first notch and the second notch are centrally symmetrical about the center point.

10. The array substrate according to claim 7, wherein: The first notch and the second notch are adjacent to each other.

11. The array substrate according to claim 10, wherein: The metal wire has a center line extending along the first direction, and the first notch and the second notch are symmetrically arranged about the center line.

12. The array substrate according to any one of claims 7 to 11, wherein: The area of ​​the second notch is the same as the area of ​​the first notch.

13. The array substrate according to any one of claims 2 to 12, wherein: Also included is a second metal layer located between the base substrate and the first metal layer, the second metal layer including a plurality of gate lines extending along the second direction and arranged along the first direction, the first metal layer also including a plurality of data lines extending along the first direction and arranged along the second direction, the data lines and the metal lines being alternately arranged between the sub-pixels in adjacent columns; The plurality of gate lines and the plurality of data lines intersect to define the plurality of sub-pixels. The sub-pixels in the same row have different colors, and the sub-pixels in the same column have the same color. The sub-pixels in each row are electrically connected to two corresponding gate lines.

14. The array substrate according to claim 13, wherein: The two gate lines electrically connected to the sub-pixels in the same row are respectively located on both sides of the sub-pixels, and there are two gate lines between the sub-pixels in two adjacent rows; The orthographic projection of the first via hole on the base substrate is located between the orthographic projections of two gate lines between adjacent sub-pixels on the base substrate.

15. The array substrate according to claim 14, wherein: The orthographic projection of the first portion on the substrate is located between orthographic projections of two gate lines between adjacent sub-pixels on the substrate.

16. The array substrate according to claim 15, wherein: The width of the second portion in an area overlapping with the gate line is greater than the width of the second portion in an area not overlapping with the gate line.

17. The array substrate according to any one of claims 14 to 16, wherein: The two columns of the first transparent electrodes and the second connecting portion between two adjacent data lines are an integrated structure.

18. The array substrate according to any one of claims 1 to 5, 7 to 11, and 14 to 16, wherein: The first transparent electrode layer further includes a third connecting portion, and two adjacent second connecting portions along the second direction are electrically connected via the third connecting portion.

19. The array substrate according to any one of claims 14 to 16, wherein: Also includes: a second transparent electrode layer located between the second metal layer and the base substrate, a second insulating layer located between the second metal layer and the first metal layer, and an active layer located between the second insulating layer and the first metal layer; wherein, The first metal layer also includes a source and a drain, the second transparent electrode layer includes a second transparent electrode located at each sub-pixel, and the first transparent electrode layer also includes a fourth connecting portion, which is electrically connected to the drain and the second transparent electrode respectively through a second via hole penetrating the first insulating layer and the second insulating layer, and the data line is electrically connected to the source.

20. The array substrate according to claim 19, wherein: The active layer includes a channel portion electrically connected to the source and the drain, and a dummy portion located between the metal line and the second insulating layer. The pattern of the dummy portion is the same as the pattern of the metal line, and the dummy portion has a third notch at a position corresponding to the first notch.

21. The array substrate according to claim 19, wherein: The first transparent electrode is a common electrode, and the first transparent electrode includes a plurality of slits; The second transparent electrode is a pixel electrode, and the second transparent electrode is a planar electrode.

22. A display panel, wherein: include: The array substrate according to any one of claims 1 to 21, a counter substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

23. A display device, wherein: Comprising the display panel as claimed in claim 22.

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