Display panel and display device

Abstract

The utility model discloses a display panel and a display device. The display panel comprises a substrate and a plurality of pixel circuits located on the substrate. Each pixel circuit comprises a first capacitor and a second capacitor; the first capacitor comprises a first capacitor electrode and a second capacitor electrode, the second capacitor comprises a third capacitor electrode and a fourth capacitor electrode, the third capacitor electrode is electrically connected with the second capacitor electrode, and the fourth capacitor electrode is configured to receive a constant voltage signal. The overlapping area of the first capacitor electrode and the second capacitor electrode is different from the overlapping area of the third capacitor electrode and the fourth capacitor electrode. The utility model provides an overall layout design of a pixel circuit, which comprehensively considers the size and pixel resolution of a display panel while enabling the compensation effect of threshold voltage to be better.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) displays are highly popular with users due to their rich colors, fast response time, and foldability. The tandem structure employed by these displays increases the lifespan and brightness of the OLED by adding at least one light-emitting layer and a charge-generating layer to the OLED, while also reducing power consumption. This approach meets user demands for both power consumption and longevity. Utility Model Content

[0003] The utility model provides a display panel and a display device.

[0004] An embodiment of the present invention provides a display panel comprising: a substrate; a plurality of pixel circuits located on the substrate, each pixel circuit comprising a first capacitor and a second capacitor; the first capacitor comprising a first capacitor electrode and a second capacitor electrode; the second capacitor comprising a third capacitor electrode and a fourth capacitor electrode; the third capacitor electrode being electrically connected to the second capacitor electrode; and the fourth capacitor electrode being configured to receive a constant voltage signal. An overlapping area between the first capacitor electrode and the second capacitor electrode is different from an overlapping area between the third capacitor electrode and the fourth capacitor electrode.

[0005] For example, according to an embodiment of the present invention, the pixel circuit also includes a driving transistor, which includes a first electrode, a gate and a second electrode; the first capacitor electrode is electrically connected to the gate of the driving transistor, and the second capacitor electrode is electrically connected to the first electrode of the driving transistor.

[0006] For example, according to an embodiment of the present invention, the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

[0007] For example, according to an embodiment of the present invention, the capacitance ratio of the second capacitor to the first capacitor is 0.5-1.5.

[0008] For example, according to an embodiment of the present invention, the plurality of pixel circuits include a first pixel circuit and a second pixel circuit, and the capacitance values ​​of the second capacitors in the first pixel circuit and the second pixel circuit are different.

[0009] For example, according to an embodiment of the present invention, the plurality of pixel circuits include a first pixel circuit and a second pixel circuit, and in the first pixel circuit and the second pixel circuit, a capacitance ratio between the second capacitor and the first capacitor is different.

[0010] For example, according to an embodiment of the present invention, the multiple pixel circuits include a first pixel circuit, a second pixel circuit and a third pixel circuit, and the ratio of the capacitance value of the second capacitor in the second pixel circuit and the first pixel circuit is 0.56-1, or the ratio of the capacitance value of the second capacitor in the second pixel circuit and the third pixel circuit is 0.56-1.

[0011] For example, according to an embodiment of the present invention, the plurality of pixel circuits include a first pixel circuit and a second pixel circuit, and an area of ​​the first capacitor electrode in the first pixel circuit is larger than an area of ​​the first capacitor electrode in the second pixel circuit.

[0012] For example, according to an embodiment of the present invention, the display panel further includes: a first metal layer located on the base substrate; and a second metal layer located on a side of the first metal layer away from the base substrate. The first metal layer includes at least a portion of the first capacitor electrode and the fourth capacitor electrode, the second metal layer includes at least a portion of the second capacitor electrode and at least a portion of the third capacitor electrode, the second capacitor electrode and the third capacitor electrode forming an integrally arranged capacitor plate, and the capacitor plate covering the gap between the first capacitor electrode and the fourth capacitor electrode.

[0013] For example, according to an embodiment of the present invention, the first metal layer includes alternating data lines and first power signal lines, the first capacitor electrode and the fourth capacitor electrode in the first metal layer are located between the data line and the first power signal line, and the fourth capacitor electrode is closer to the first power signal line than the first capacitor electrode.

[0014] For example, according to an embodiment of the present invention, the display panel also includes a plurality of light-emitting elements; the pixel circuit also includes a first light-emitting control transistor and a data writing transistor, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor is electrically connected to the light-emitting element, the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the gate of the driving transistor; the second metal layer includes a first light-emitting control signal line and a first scanning signal line arranged at intervals, the gate of the data writing transistor is electrically connected to the first scanning signal line, and the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line; the first capacitor electrode, the second capacitor electrode, the third capacitor electrode and the fourth capacitor electrode are all located between the first light-emitting control signal line and the first scanning signal line.

[0015] For example, according to an embodiment of the present invention, the display panel further includes a semiconductor layer located between the first metal layer and the base substrate, the semiconductor layer including at least an active layer pattern of the drive transistor. In a direction perpendicular to the base substrate, a portion of the semiconductor layer overlapping the first metal layer includes a conductive portion electrically connected to the second metal layer, the conductive portion facing the first metal layer to form a capacitor.

[0016] For example, according to an embodiment of the present invention, the ratio of the area of ​​at least one of the first capacitor electrode and the second capacitor electrode to the area of ​​the pixel circuit in which the first capacitor electrode is located is 0.12-0.19.

[0017] For example, according to an embodiment of the present invention, the display panel further includes: a reference signal line electrically connected to the fourth capacitor electrode and configured to transmit the constant voltage signal to the fourth capacitor electrode, and at least a portion of the reference signal line extends along the first direction.

[0018] For example, according to an embodiment of the present invention, the reference signal line is configured to transmit one of a pixel driving voltage signal, a low-potential power supply voltage signal, a reference voltage signal, and an initialization voltage signal.

[0019] For example, according to an embodiment of the present invention, the reference signal line is located between the second metal layer and the base substrate, the second metal layer includes a plurality of signal lines arranged along the first direction, and along a direction perpendicular to the base substrate, the reference signal line overlaps with at least three of the plurality of signal lines.

[0020] For example, according to an embodiment of the present invention, the display panel also includes a plurality of light-emitting elements; the pixel circuit also includes a first light-emitting control transistor and a first reset transistor; the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor is electrically connected to the light-emitting element, and the first electrode of the first reset transistor is electrically connected to the second electrode of the first light-emitting control transistor; the multiple signal lines include a first light-emitting control signal line, a second scanning signal line and an initialization voltage signal line arranged in sequence along the first direction; the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, the gate of the first reset transistor is electrically connected to the second scanning signal line, and the second electrode of the first reset transistor is electrically connected to the initialization voltage signal line; along a direction perpendicular to the substrate, the first light-emitting control signal line, the second scanning signal line and the initialization voltage signal line all overlap with the reference signal line, and the first light-emitting control signal line is located between the first capacitor electrode and the initialization voltage signal line.

[0021] For example, according to an embodiment of the present invention, the first metal layer includes a data line, the reference signal line, and a first power signal line arranged in sequence, and the reference signal line is located between at least a portion of the fourth capacitor electrode and the first power signal line.

[0022] For example, according to an embodiment of the present invention, the reference signal line is configured to transmit the reference voltage signal.

[0023] For example, according to an embodiment of the present invention, the reference signal line and at least a portion of the fourth capacitor electrode are integrated into one structure.

[0024] For example, according to an embodiment of the present invention, the reference signal line is configured to transmit the low-potential power supply voltage signal.

[0025] For example, according to an embodiment of the present invention, the second metal layer includes a second power signal line extending along a second direction, the second power signal line is located between adjacent pixel circuits, the reference signal line is electrically connected to the second power signal line to receive the low-potential power voltage signal, and the second direction intersects with the first direction.

[0026] For example, according to an embodiment of the present invention, the reference signal line is configured to transmit the pixel driving voltage signal.

[0027] For example, according to an embodiment of the present invention, the second metal layer includes a third power signal line extending along a second direction, the third power signal line is located on the side of the initialization voltage signal line away from the first light-emitting control signal line, the reference signal line is electrically connected to the third power signal line to receive the pixel driving voltage signal, and the second direction intersects with the first direction.

[0028] For example, according to an embodiment of the present invention, the first metal layer includes a data line and a first power signal line arranged at intervals, the reference signal line is located between at least a portion of the fourth capacitor electrode and the first power signal line, and the first power signal line is electrically connected to the third power signal line.

[0029] For example, according to an embodiment of the present invention, the first metal layer includes a data line and a first power signal line that are spaced apart, and the reference signal line and the first power signal line are integrated signal lines.

[0030] For example, according to an embodiment of the present invention, the display panel further includes: a semiconductor layer located between the first metal layer and the base substrate; and a third metal layer located between the semiconductor layer and the base substrate. In a direction perpendicular to the base substrate, the second capacitor electrode and the first power signal line both overlap with the third metal layer, and the third metal layer is configured to receive the pixel driving voltage signal.

[0031] For example, according to an embodiment of the present invention, the third metal layer is electrically connected to the first power signal line.

[0032] For example, according to an embodiment of the present invention, the pixel circuit includes a plurality of transistors, and the plurality of transistors include at least the driving transistor, the first light-emitting control transistor and the first reset transistor. Along a direction perpendicular to the substrate, the third metal layer overlaps with the channel region of at least some of the plurality of transistors.

[0033] For example, according to an embodiment of the present invention, the display panel further includes: a semiconductor layer located between the first metal layer and the base substrate; and a third metal layer located between the semiconductor layer and the base substrate. The pixel circuit includes a plurality of transistors, the plurality of transistors including at least the drive transistor, the first light emission control transistor, and the first reset transistor. Along a direction perpendicular to the base substrate, the third metal layer overlaps with channel regions of at least some of the plurality of transistors.

[0034] For example, according to an embodiment of the present invention, along a direction perpendicular to the substrate, the reference signal line overlaps with the plurality of signal lines.

[0035] For example, according to an embodiment of the present invention, the reference signal line is configured to transmit the initialization voltage signal.

[0036] For example, according to an embodiment of the present invention, the semiconductor layer includes the reference signal line, and the fourth capacitor electrode is electrically connected to the first electrode of the first reset transistor through the reference signal line.

[0037] For example, according to an embodiment of the present invention, the reference signal line and the first electrode of the first reset transistor are integrated into one structure.

[0038] For example, according to an embodiment of the present invention, the first metal layer includes the reference signal line, and the fourth capacitor electrode is electrically connected to the initialization voltage signal line through the reference signal line.

[0039] For example, according to an embodiment of the present invention, the reference signal line and the fourth capacitor electrode are integrated into one structure.

[0040] For example, according to an embodiment of the present invention, the pixel circuit also includes a data writing transistor, a second light-emitting control transistor and a second reset transistor; the multiple signal lines also include a second light-emitting control signal line, a reset power signal line, a first scanning signal line and a third scanning signal line; the first metal layer includes a data line and a first power signal line; the first electrode of the data writing transistor is electrically connected to the data line, the second electrode of the data writing transistor is electrically connected to the gate of the driving transistor, the gate of the data writing transistor is electrically connected to the first scanning signal line, the first electrode of the second light-emitting control transistor is electrically connected to the first power signal line, the second electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line, the first electrode of the second reset transistor is electrically connected to the reset power signal line, the second electrode of the second reset transistor is electrically connected to the first capacitor electrode, and the gate of the second reset transistor is electrically connected to the third scanning signal line.

[0041] For example, according to an embodiment of the present invention, the display panel further includes: a semiconductor layer located between the first metal layer and the base substrate. The display panel further includes a plurality of light-emitting elements, each of which includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence, the first electrode being located between the light-emitting functional layer and the base substrate, and electrically connected to the pixel circuit; the number of metal layers between the semiconductor layer and the first electrode of the light-emitting element is N1, and N1 is not greater than 2.

[0042] For example, according to an embodiment of the present invention, the display panel further includes: a semiconductor layer located between the first metal layer and the base substrate. The display panel further includes a plurality of light-emitting elements, each of which includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence, the first electrode being located between the light-emitting functional layer and the base substrate, and electrically connected to the pixel circuit; and the number of planar layers disposed between the semiconductor layer and the first electrodes of the light-emitting elements is N2, where N2 is not greater than 1.

[0043] For example, according to an embodiment of the present invention, each pixel circuit includes a plurality of transistors and a plurality of capacitors, the number of the plurality of transistors is greater than or equal to 5, and the number of the capacitors is greater than or equal to 2.

[0044] For example, according to an embodiment of the present invention, the multiple pixel circuits are arranged in an array along a first direction and a second direction, and the size of the pixel circuit in one of the first direction and the second direction is 90~180 microns, and in the other of the first direction and the second direction, the sum of the sizes of two pixel circuits or three pixel circuits is 90~180 microns.

[0045] For example, according to an embodiment of the present invention, the display panel includes a plurality of sub-pixels, each sub-pixel includes the pixel circuit and a light-emitting element electrically connected to the pixel circuit, the light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode that are stacked, the first electrode is located between the light-emitting functional layer and the base substrate, and the first electrode is electrically connected to the pixel circuit; the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, the first color sub-pixel and the second color sub-pixel are arranged along a first direction, the first color sub-pixel and the third color sub-pixel are arranged along a second direction, and the first direction intersects with the second direction.

[0046] For example, according to an embodiment of the present invention, the display panel further includes an isolation structure located on the base substrate, wherein the isolation structure is configured to isolate the light-emitting functional layer and the second electrode of the sub-pixel.

[0047] For example, according to an embodiment of the present invention, a plurality of isolation openings are provided in the isolation structure, and a portion of the film layer configured to form the light-emitting functional layer and the second electrode of the sub-pixel, which is located outside a specific isolation opening among the plurality of isolation openings, is removed by a photolithography process, and the specific isolation opening is an isolation opening corresponding to the sub-pixel on which the light-emitting functional layer and the second electrode are to be formed.

[0048] For example, according to an embodiment of the present invention, the display panel further includes: a first metal layer located on the base substrate; a second metal layer located on a side of the first metal layer away from the base substrate. The isolation structure is located on a side of the second metal layer away from the first metal layer, the first metal layer includes the first capacitor electrode, the fourth capacitor electrode, and a reference signal line, the second metal layer includes the second capacitor electrode and the third capacitor electrode, and the second capacitor electrode and the third capacitor electrode are integrally arranged capacitor plates, and the capacitor plates cover the gap between the first capacitor electrode and the fourth capacitor electrode, and the reference signal line is electrically connected to the fourth capacitor electrode and is configured to transmit a low-potential power supply voltage signal to the fourth capacitor electrode.

[0049] For example, according to an embodiment of the present invention, the reference signal line extends along the first direction, the second metal layer includes a second power signal line extending along the second direction, the second power signal line is located between the pixel circuits of adjacent sub-pixels, and the reference signal line is electrically connected to the second power signal line to receive the low-potential power supply voltage signal.

[0050] For example, according to an embodiment of the present invention, the second electrode is electrically connected to the isolation structure, and the isolation structure is electrically connected to the reference signal line.

[0051] For example, according to an embodiment of the present invention, the display panel further includes: a pixel-defining pattern located on a side of the second metal layer away from the base substrate, the pixel-defining pattern including a plurality of pixel openings and a pixel-defining portion surrounding the plurality of pixel openings, the plurality of pixel openings being configured to define light-emitting areas of the plurality of sub-pixels. The isolation structure is located on a side of the pixel-defining portion away from the base substrate, and the isolation structure is electrically connected to the reference signal line through a via in the pixel-defining portion.

[0052] For example, according to an embodiment of the present invention, the display panel further includes an auxiliary connection portion located in at least one of the film layer where the first electrode of the light-emitting element is located, the first metal layer, and the second metal layer. The isolation structure is electrically connected to the reference signal line via the auxiliary connection portion.

[0053] For example, according to an embodiment of the present invention, a display panel is provided, wherein, along a direction perpendicular to the base substrate, the reference signal line includes a first reference signal line portion overlapping with the auxiliary connection portion and a second reference signal line portion not overlapping with the auxiliary connection portion, and the maximum width of the first reference signal line portion is greater than the maximum width of the second reference signal line portion.

[0054] For example, according to an embodiment of the present invention, along a direction perpendicular to the substrate, the reference signal line and the second power signal line both overlap with the auxiliary connection portion, and the auxiliary connection portion includes a first auxiliary connection portion overlapping with the reference signal line and a second auxiliary connection portion overlapping with the second power signal line.

[0055] For example, according to an embodiment of the present invention, the isolation structure includes an annular isolation structure surrounding a light-emitting area of ​​at least one sub-pixel, and the annular isolation structure overlaps with the auxiliary connection portion along a direction perpendicular to the base substrate.

[0056] For example, according to an embodiment of the present invention, there are multiple annular isolation structures, each of which surrounds the light-emitting area of ​​a sub-pixel, and intervals are set between the isolation structures surrounding the light-emitting areas of sub-pixels of different colors.

[0057] For example, according to an embodiment of the present invention, at least one annular isolation structure surrounds the light-emitting areas of a plurality of sub-pixels of the same color.

[0058] For example, according to an embodiment of the present invention, the plurality of sub-pixels include sub-pixels of different colors, and the second electrodes of at least two sub-pixels of different colors are configured to transmit different low-potential power supply voltage signals.

[0059] For example, according to an embodiment of the present invention, the first electrode of the light-emitting element includes a main electrode and a connecting electrode, and the main electrode overlaps with the light-emitting area of ​​the sub-pixel; an insulating layer is provided between the connecting electrode and the second electrode of the first light-emitting control transistor in the pixel circuit, and the connecting electrode is electrically connected to the second electrode of the first light-emitting control transistor through the anode via in the insulating layer; in the same sub-pixel, the orthographic projection of the anode via on the substrate is a first orthographic projection, and the orthographic projection of the light-emitting area on the substrate is a second orthographic projection, and the distance between the edges of the first orthographic projection and the second orthographic projection close to each other is a first sub-distance, and the first sub-distance is 1~3 microns.

[0060] For example, according to an embodiment of the present invention, the orthographic projection of the isolation structure on the substrate is a third orthographic projection, the minimum distance between the third orthographic projection and the second orthographic projection is a second sub-distance, and the second sub-distance is 2 to 5 microns.

[0061] For example, according to an embodiment of the present invention, the first sub-distance is smaller than the second sub-distance.

[0062] For example, according to an embodiment of the present invention, the size of the isolation structure in a direction perpendicular to the substrate is 1.5 to 3 microns.

[0063] For example, according to an embodiment of the present invention, the first electrode includes a main electrode and a connecting electrode, the main electrode overlaps with the light-emitting area of ​​the sub-pixel, and the connecting electrode is electrically connected to the second electrode of the first light-emitting control transistor in the pixel circuit; the length of the connecting electrode of the first color sub-pixel in the preset direction is greater than the size of the light-emitting area of ​​the second color sub-pixel in the preset direction.

[0064] For example, according to an embodiment of the present invention, the preset direction is the first direction.

[0065] For example, according to an embodiment of the present invention, the display panel includes a plurality of sub-pixels, and the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; each sub-pixel includes the pixel circuit and a light-emitting element electrically connected to the pixel circuit, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode that are stacked, and the first electrode is located between the light-emitting functional layer and the base substrate; the light-emitting functional layer includes a first electron blocking layer, a first light-emitting layer, a charge generation layer, a second electron blocking layer, and a second light-emitting layer that are stacked in sequence, and the first light-emitting layer is located between the second light-emitting layer and the first electrode; there is a first distance between the surfaces of the first electrode and the second electrode that are close to each other L, a second distance L1 is provided between the surface of the second light-emitting layer facing the substrate and the surface of the second electrode facing the substrate, a third distance L2 is provided between the surface of the first light-emitting layer away from the substrate and the surface of the first electrode away from the substrate, a fourth distance L3 is provided between the surfaces of the first light-emitting layer and the second light-emitting layer close to each other, a fifth distance L4 is provided between the surface of the first light-emitting layer away from the substrate and the surface of the first electron blocking layer close to the substrate, the charge generating layer has a first thickness L5, and a sixth distance L6 is provided between the surface of the second light-emitting layer away from the substrate and the surface of the second electron blocking layer close to the substrate.

[0066] For example, according to an embodiment of the present invention, the ratio of the distance between the first light-emitting layer and the surfaces of the first electrode close to each other to the first distance L is 0.2~0.3, and the ratio of the distance between the second light-emitting layer and the surfaces of the first electrode close to each other to the first distance is 0.7~0.8.

[0067] For example, according to an embodiment of the present invention, in the first color sub-pixel, the third distance L2 and the fifth distance L4 satisfy 0.6≤L4 / L2≤0.9; in the second color sub-pixel, the third distance L2 and the fifth distance L4 satisfy 0.5≤L4 / L2≤0.8; in the third color sub-pixel, the third distance L2 and the fifth distance L4 satisfy 0.3≤L4 / L2≤0.7.

[0068] For example, according to an embodiment of the present invention, in the first color sub-pixel, the sixth distance L6 and the second distance L1 satisfy 0.8≤L6 / L1≤1.2; in the second color sub-pixel, the sixth distance L6 and the second distance L1 satisfy 0.5≤L6 / L1≤0.9; in the third color sub-pixel, the sixth distance L6 and the second distance L1 satisfy 0.3≤L6 / L1≤0.6.

[0069] For example, according to an embodiment of the present invention, in the first color sub-pixel, the first thickness L5 and the first distance L satisfy 0.07≤L5 / L≤0.12; in the second color sub-pixel, the first thickness L5 and the first distance L satisfy 0.09≤L5 / L≤0.15; in the third color sub-pixel, the first thickness L5 and the first distance L satisfy 0.12≤L5 / L≤0.18.

[0070] For example, according to an embodiment of the present invention, the light-emitting functional layer also includes a hole transport layer located between the second electron blocking layer and the charge generation layer, and the hole transport layer has a second thickness L7; in the first color sub-pixel, the second thickness L7 and the fourth distance L3 satisfy 0.1≤L7 / L3≤0.6; in the second color sub-pixel, the second thickness L7 and the fourth distance L3 satisfy 0.2≤L7 / L3≤0.7; in the third color sub-pixel, the second thickness L7 and the fourth distance L3 satisfy 0.25≤L7 / L3≤0.8.

[0071] For example, according to an embodiment of the present invention, the light-emitting functional layer further includes an electron injection layer located between the second light-emitting layer and the second electrode, and the thickness of the electron injection layer is 1 to 10 angstroms or 11 to 19 angstroms.

[0072] For example, according to an embodiment of the present invention, when the display panel is at maximum brightness and maintained for 10 minutes, the temperature does not exceed 40 degrees; when the display panel is at maximum brightness and maintained for 10 to 26 minutes, the temperature does not exceed 50 degrees.

[0073] For example, according to an embodiment of the present invention, the diagonal size of the display surface of the display panel is greater than or equal to 39.6 cm.

[0074] For example, according to an embodiment of the present invention, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels are divided into a plurality of pixel units, the plurality of pixel units include a plurality of pixel unit rows arranged along a first direction, and the number of pixel units in each pixel unit row is greater than or equal to 2560; the plurality of pixel units include a plurality of pixel unit columns arranged along the second direction, and the number of pixel units in each pixel unit column is greater than or equal to 1440; the first direction intersects with the second direction.

[0075] For example, according to an embodiment of the present invention, each pixel unit includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, the first color sub-pixel and the second color sub-pixel are arranged along a first direction, and the first color sub-pixel and the third color sub-pixel are arranged along a second direction.

[0076] An embodiment of the present invention provides a display device, comprising any of the above-mentioned display panels.

[0077] For example, according to an embodiment of the present invention, the display device is a vehicle-mounted display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, rather than limiting the present invention.

[0079] Figure 1 It is a schematic diagram of a partial planar structure of a display panel provided according to the utility model.

[0080] Figure 2 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0081] Figure 3 for Figure 2 Schematic diagram of the first metal layer in the pixel circuit shown.

[0082] Figure 4 for Figure 2 Schematic diagram of the second metal layer in the pixel circuit shown.

[0083] Figure 5 for Figure 2 Schematic diagram of the semiconductor layers in the pixel circuit shown.

[0084] Figure 6 for Figure 2 Schematic diagram of the equivalent circuit of the pixel circuit and its connection to the light-emitting element.

[0085] Figure 7 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0086] Figure 8 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0087] Figure 9 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0088] Figure 10 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0089] Figure 11 for Figure 10 Schematic diagram of the stacking relationship between the first metal layer and the third metal layer in the structure shown.

[0090] Figure 12 for Figure 10 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown.

[0091] Figure 13 for Figure 10 Schematic diagram of the stacking relationship between the second metal layer and the third metal layer in the structure shown.

[0092] Figure 14 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0093] Figure 15 for Figure 14 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown.

[0094] Figure 16 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0095] Figure 17 for Figure 16 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown.

[0096] Figure 18 for Figure 16 Schematic diagram of the third metal layer in the shown structure.

[0097] Figure 19 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0098] Figure 20 for Figure 19 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown.

[0099] Figure 21 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0100] Figure 22 for Figure 21 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown.

[0101] Figure 23 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0102] Figure 24 for Figure 23 Schematic diagram of the semiconductor layers in the shown structure.

[0103] Figure 25 for Figure 23 Equivalent circuit diagram of the pixel circuit shown.

[0104] Figure 26 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0105] Figure 27 for Figure 26 Schematic diagram of the first metal layer in the shown structure.

[0106] Figure 28 for Figure 26 Equivalent circuit diagram of the pixel circuit shown.

[0107] Figure 29 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0108] Figure 30 for Figure 29 Schematic diagram of the semiconductor layers in the shown structure.

[0109] Figure 31 A diagram showing the stacking relationship between a portion of the pixel circuit and the first electrode of the light-emitting element.

[0110] Figure 32 For the Figure 31 The schematic diagram of the local cross-section structure taken along line AA' is shown.

[0111] Figure 33 The diagram shows an arrangement of sub-pixels in a display panel according to an embodiment of the present invention.

[0112] Figure 34 A schematic diagram of a partial interface structure of a display panel provided according to an example of an embodiment of the present utility model.

[0113] Figure 35 The diagram is a planar diagram of a partial isolation structure in a display panel provided according to an example of an embodiment of the present utility model.

[0114] Figures 36 to 38 Schematic diagrams of the planar shape of the isolation structure in the display panel provided according to different examples of the embodiment of the present utility model.

[0115] Figure 39 Schematic diagram of the stacking relationship between the isolation structure and the pixel circuit.

[0116] Figure 40 For the Figure 39The schematic diagram of the local cross-section structure taken along line BB' is shown.

[0117] Figure 41 Schematic diagram of the stacking relationship among the isolation structure, auxiliary connection portion, and pixel circuit.

[0118] Figure 42 For the Figure 41 The schematic diagram of the local cross-section structure taken along line CC' is shown.

[0119] Figure 43 This is a diagram showing the stacking relationship between the film layer where the reference signal line is located and the auxiliary connection part.

[0120] Figure 44 A diagram showing the stacking relationship between a portion of the pixel circuit and the first electrode of the light-emitting element.

[0121] Figure 45 Schematic diagram of the stacking relationship of light-emitting elements of sub-pixels of different colors provided according to an embodiment of the present invention.

[0122] Figure 46 The following is a curve showing temperature changes over time when different areas of the display panel are at maximum brightness according to an embodiment of the present invention.

[0123] Figure 47 It is a curve showing the temperature change over time when different areas of the display panel are at maximum brightness.

[0124] Figure 48 The present invention is a schematic block diagram of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0125] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0126] Unless otherwise defined, technical or scientific terms used in this utility model should have the ordinary meaning understood by people with ordinary skills in the field to which this utility model belongs. The words "first", "second" and similar terms used in this utility model do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar words mean that the elements or objects listed before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0127] When the number of a component is not specifically indicated in the following embodiments of the present invention, it means that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0128] The utility model provides a display panel and a display device. The display panel includes a substrate and a plurality of pixel circuits located on the substrate. Each pixel circuit includes a first capacitor and a second capacitor; the first capacitor includes a first capacitor electrode and a second capacitor electrode; the second capacitor includes a third capacitor electrode and a fourth capacitor electrode; the third capacitor electrode is electrically connected to the second capacitor electrode; and the fourth capacitor electrode is configured to receive a constant voltage signal. The overlapping area of ​​the first capacitor electrode and the second capacitor electrode is different from the overlapping area of ​​the third capacitor electrode and the fourth capacitor electrode.

[0129] In the display panel provided by the present invention, two capacitors are provided in each pixel circuit, one capacitor electrode of the second capacitor receives a constant voltage signal, and the overlapping areas of the capacitor electrodes in different capacitors are different. The present invention provides an overall layout design of the pixel circuit, which comprehensively considers the size and pixel resolution of the display panel while achieving a better compensation effect for the threshold voltage.

[0130] The display panel and the display device provided by the embodiments of the present invention are described below with reference to the accompanying drawings.

[0131] Figure 1 It is a schematic diagram of a partial planar structure of a display panel provided according to the utility model. Figure 2 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown.

[0132] like Figure 1 As shown, the display panel includes a base substrate 01 and a plurality of pixel circuits located on the base substrate 01. For example, the plurality of pixel circuits 100 are arranged in an array along a first direction and a second direction, and the first direction intersects the second direction, such as the first direction is perpendicular to the second direction. For example, the first direction can be Figure 1 The X direction shown, the second direction can be Figure 1 The Y direction is shown. However, the present invention is not limited thereto, and the first direction and the second direction can be interchanged. Figure 1 The pixel circuit is schematically illustrated in a dotted box, and the specific structure of the pixel circuit is not specifically illustrated. The specific structure of the pixel circuit can be found in subsequent drawings.

[0133] like Figure 2As shown, each pixel circuit includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 includes a first capacitor electrode C11 and a second capacitor electrode C12. The second capacitor C2 includes a third capacitor electrode C23 and a fourth capacitor electrode C24. The third capacitor electrode C23 is electrically connected to the second capacitor electrode C12, and the fourth capacitor electrode C24 is configured to receive a constant voltage signal. The overlapping area of ​​the first capacitor electrode C11 and the second capacitor electrode C12 is different from the overlapping area of ​​the third capacitor electrode C23 and the fourth capacitor electrode C24. For example, the capacitance value of the first capacitor C1 is different from the capacitance value of the second capacitor C2.

[0134] In the display panel provided by the present invention, two capacitors are provided in each pixel circuit, one capacitor electrode of the second capacitor receives a constant voltage signal, and the overlapping areas of the capacitor electrodes in different capacitors are different. The present invention provides an overall layout design of the pixel circuit, which comprehensively considers the size and pixel resolution of the display panel while achieving a better compensation effect for the threshold voltage.

[0135] In some examples, such as Figure 2 As shown, each pixel circuit further includes a driving transistor DT, which includes a first electrode, a gate electrode, and a second electrode; the first capacitor electrode C11 of the first capacitor C1 is electrically connected to the gate electrode of the driving transistor DT, and the second capacitor electrode C12 of the first capacitor C1 is electrically connected to the first electrode of the driving transistor DT.

[0136] For example, the first capacitor C1 stores the gate-source voltage Vgs of the driving transistor DT. The gate-source voltage Vgs of the driving transistor DT has a value of (1-C')*(Vdata-Vref)+Vth in the light-emitting phase. Vdata is the data voltage, and Vref is the base voltage or reference voltage, such as Vref can be set to a voltage at which the driving transistor DT can be turned on; Vref can be set within the voltage range of the data voltage Vdata output from the data driver. Vth is the threshold voltage of the driving transistor DT. C'=C01 / (C01+C02), where C01 is the capacitance value of the first capacitor C1, and C02 is the capacitance value of the second capacitor C2. In the above calculation formula, if C02=0, then C'=1, and (1-C')=0, so that Vgs=Vth. Therefore, in order to change the gate-source voltage Vgs of the driving transistor DT according to the data voltage Vdata of the pixel data, a second capacitor C2 needs to be set in the pixel circuit.

[0137] In some examples, such as Figure 2 As shown, the capacitance value of the second capacitor C2 is greater than the capacitance value of the first capacitor C1.

[0138] The transmission rate of the data voltage in the gate-source voltage Vgs of the driving transistor DT is related to the ratio of the capacitance value of the first capacitor C1 to the capacitance value of the second capacitor C2. By setting the capacitance value of the second capacitor C2 to be greater than the capacitance value of the first capacitor C1, it is beneficial to reduce the value of C', thereby achieving a better compensation effect for the threshold voltage.

[0139] In some examples, such as Figure 2 and Figure 3 As shown, the capacitance ratio of the second capacitor C2 to the first capacitor C1 is 0.5-1.5. For example, the capacitance ratio of the second capacitor C2 to the capacitance of the first capacitor C1 is 0.6-1. For example, the capacitance ratio of the second capacitor C2 to the capacitance of the first capacitor C1 is 0.7-1.2. For example, the capacitance ratio of the second capacitor C2 to the capacitance of the first capacitor C1 is 0.8-1.4. For example, the capacitance ratio of the second capacitor C2 to the capacitance of the first capacitor C1 is 0.9-1.3. The embodiments of the present utility model no longer enumerate the specific values ​​of the capacitance ratios of the second capacitor C2 to the first capacitor C1 one by one. The capacitance ratio of the second capacitor C2 to the first capacitor C1 can be any value between 0.5-1.5.

[0140] By setting the capacitance ratio of the second capacitor C2 to the first capacitor C1 , it is advantageous to achieve a compensation effect for the threshold voltage while improving the resolution of the display panel.

[0141] In some examples, such as Figure 1 and Figure 2 As shown, the plurality of pixel circuits 1100 include a first pixel circuit 101 and a second pixel circuit 102 , and the capacitance values ​​of the second capacitors C2 in the first pixel circuit 101 and the second pixel circuit 102 are different.

[0142] In some examples, such as Figure 1 and Figure 2 As shown, the plurality of pixel circuits 100 include a first pixel circuit 101 and a second pixel circuit 102. The capacitance ratios of the second capacitor C2 to the first capacitor C1 are different in the first pixel circuit 101 and the second pixel circuit 102. For example, the capacitance ratio of the second capacitor C2 to the first capacitor C1 in the first pixel circuit 101 is greater than or less than the capacitance ratio of the second capacitor C2 to the first capacitor C1 in the second pixel circuit 102.

[0143] For example, Figure 1As shown, the first pixel circuit 101 and the second pixel circuit 102 are pixel circuits electrically connected to the light emitting element 300 emitting different colors. For example, the display panel includes sub-pixels of different colors, and the first pixel circuit 101 and the second pixel circuit 102 are pixel circuits in the sub-pixels of different colors.

[0144] For example, the different color sub-pixels may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. For example, one of the first pixel circuit 101 and the second pixel circuit 102 may be a pixel circuit in a green sub-pixel, and the other of the first pixel circuit 101 and the second pixel circuit 102 may be a pixel circuit in a red sub-pixel or a blue sub-pixel. For example, the capacitance ratio of the second capacitor C2 to the first capacitor C1 in at least two different color sub-pixels may be different. For example, the capacitance ratio of the second capacitor C2 to the first capacitor C1 in two different color sub-pixels may be the same.

[0145] By setting the capacitance value of the second capacitor in the pixel circuit electrically connected to the light-emitting elements emitting different colors to be different, it is beneficial to make the gate-source voltage Vgs of the driving transistor in the sub-pixels of different colors have different values ​​during the light-emitting stage to adjust the light-emitting intensity of the sub-pixels of different colors, while improving the pixel arrangement density and the flatness of the film layer in the light-emitting area.

[0146] In some examples, such as Figure 1 and Figure 2 As shown, the multiple pixel circuits 100 include a first pixel circuit 101, a second pixel circuit 102 and a third pixel circuit 103, and the ratio of the capacitance value of the second capacitor C2 in the second pixel circuit 102 and the first pixel circuit 101 is 0.56-1, or the ratio of the capacitance value of the second capacitor C2 in the second pixel circuit 102 and the third pixel circuit 103 is 0.56-1.

[0147] For example, Figure 1 and Figure 2 As shown, the capacitance value of the second capacitor C2 in the first pixel circuit 101 and the third pixel circuit 103 is not less than the capacitance value of the second capacitor C2 in the second pixel circuit 102. For example, the capacitance value of the second capacitor C2 in the first pixel circuit 101 and the capacitance value of the second capacitor C2 in the third pixel circuit 103 may be equal or different.

[0148] For example, Figure 1As shown, the first pixel circuit 101, the second pixel circuit 102, and the third pixel circuit 103 are pixel circuits for sub-pixels of different colors. For example, the first pixel circuit 101 may be a pixel circuit for a red sub-pixel that emits red light, the second pixel circuit 102 may be a pixel circuit for a green sub-pixel that emits green light, and the third pixel circuit 103 may be a pixel circuit for a blue sub-pixel that emits blue light. However, this is not limiting, and the first pixel circuit 101 and the third pixel circuit 103 may be interchangeable.

[0149] By setting a second capacitor in the pixel circuit and setting the capacitance value of the first capacitor to be greater than the capacitance value of the second capacitor but not much greater than the capacitance value of the second capacitor, it is not only beneficial to improve the compactness of the pixel arrangement, but also beneficial to ensure voltage jump.

[0150] In some examples, such as Figure 1 and Figure 2 As shown, the plurality of pixel circuits 100 include a first pixel circuit 101 and a second pixel circuit 102 , and the area of ​​the first capacitor electrode C11 in the first pixel circuit 101 is larger than the area of ​​the first capacitor electrode C11 in the second pixel circuit 102 .

[0151] For example, the first pixel circuit 101 and the second pixel circuit 102 are pixel circuits in sub-pixels of different colors, such as the first pixel circuit 101 for at least one of a red sub-pixel and a blue sub-pixel, and the second pixel circuit 102 for a green sub-pixel.

[0152] In some examples, such as Figure 2 As shown, the ratio of the area of ​​at least one of the first capacitor electrode C11 and the second capacitor electrode C12 to the area of ​​the pixel circuit where it is located is 0.12-0.19.

[0153] The area of ​​the pixel circuit described above may refer to the area enclosed by the data line DATA (described later), the first power signal line 2181 (described later), the reset power signal line REF1 (described later), and the third power signal line 2182 (described later). The present invention is not limited to the area of ​​the pixel circuit being the area enclosed by the data line, the first power signal line, the reset power signal line, and the third power signal line. The area may also refer to the area enclosed by the other four signal lines that are farthest from the first capacitor and the second capacitor and that intersect with each other.

[0154] For example, Figure 2As shown, in the same first capacitor C1, the area ratio of the first capacitor electrode C11 to the pixel circuit in which it is located is 0.12~0.19, and the area ratio of the second capacitor electrode C12 to the pixel circuit in which it is located is 0.12~0.19. For example, the area ratio of at least one of the first capacitor electrode C11 and the second capacitor electrode C12 to the pixel circuit in which it is located is 0.13~0.17. For example, the area ratio of at least one of the first capacitor electrode C11 and the second capacitor electrode C12 to the pixel circuit in which it is located is 0.14~0.16. For example, the area ratio of at least one of the first capacitor electrode C11 and the second capacitor electrode C12 to the pixel circuit in which it is located is 0.15~0.18. The embodiments of the present utility model no longer list the area ratios of the capacitor plates and the pixel circuit in which they are located one by one, and the area ratio can be any value between 0.12~0.19.

[0155] In the layout design of the pixel circuit provided by the present invention, the relative position relationship of each structure in the large-size pixel circuit layout is adjusted by setting the capacitance plate in the first capacitor C1 and the area of ​​the pixel circuit where it is located.

[0156] Figure 3 for Figure 2 Schematic diagram of the first metal layer in the pixel circuit shown. Figure 4 for Figure 2 Schematic diagram of the second metal layer in the pixel circuit shown. Figure 5 for Figure 2 Schematic diagram of the semiconductor layers in the pixel circuit shown.

[0157] In some examples, such as Figures 1 to 4 As shown, the display panel further includes a first metal layer 210 located on the base substrate and a second metal layer 220 located on a side of the first metal layer 210 away from the base substrate. The first metal layer 210 includes at least a portion of the first capacitor electrode C11 and the fourth capacitor electrode C24, and the second metal layer 220 includes at least a portion of the second capacitor electrode C12 and at least a portion of the third capacitor electrode C23. The second capacitor electrode C12 and the third capacitor electrode C23 form an integrated capacitor plate, and the capacitor plate covers the gap between the first capacitor electrode C11 and the fourth capacitor electrode C24.

[0158] In some examples, such as Figures 2 to 4 As shown, the first metal layer 210 includes alternating data lines DATA and first power signal lines 2181, and the first capacitor electrode C11 and the fourth capacitor electrode C24 in the first metal layer 210 are located between the data line DATA and the first power signal line 2181, and the fourth capacitor electrode C24 is closer to the first power signal line 2181 than the first capacitor electrode C11.

[0159] For example, Figures 2 to 4 As shown, the first power signal line 2181 extends along the first direction, and the overall extension direction of the data lines DATA is the first direction. For example, there are multiple data lines DATA and multiple first power signal lines 2181, and the multiple data lines DATA and the multiple first power signal lines 2181 are alternately arranged along the second direction.

[0160] Figure 6 for Figure 2 Schematic diagram of the equivalent circuit of the pixel circuit and its connection to the light-emitting element.

[0161] In some examples, such as Figure 6 As shown, the display panel further includes a plurality of light-emitting elements, and each pixel circuit is electrically connected to a light-emitting element. For example, the light-emitting element may be an organic light-emitting diode (OLED).

[0162] In some examples, such as Figures 2 to 6 As shown, the pixel circuit further includes a first light-emitting control transistor T4 and a data-writing transistor T1. The first electrode of the first light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor DT, the second electrode of the first light-emitting control transistor T4 is electrically connected to the light-emitting element 300, the first electrode of the data-writing transistor T1 is electrically connected to the data line DATA, and the second electrode of the data-writing transistor T1 is electrically connected to the gate of the driving transistor DT. For example, the first electrode of the driving transistor DT, the first electrode of the first light-emitting control transistor T4, the second capacitor plate of the first capacitor C1, and the third capacitor plate of the second capacitor C2 are connected to the node N02.

[0163] In some examples, such as Figures 2 to 6 As shown, the second metal layer 220 includes a first light-emitting control signal line EM2 and a first scanning signal line G1 that are spaced apart, the gate of the data writing transistor T1 is electrically connected to the first scanning signal line G1, and the gate of the first light-emitting control transistor T4 is electrically connected to the first light-emitting control signal line EM2; the first capacitor electrode C11, the second capacitor electrode C12, the third capacitor electrode C23 and the fourth capacitor electrode C24 are all located between the first light-emitting control signal line EM2 and the first scanning signal line G1.

[0164] In some examples, such as Figures 2 to 5As shown, the display panel further includes a semiconductor layer 230 located between the first metal layer 210 and the base substrate. The semiconductor layer 230 includes at least an active layer pattern of the driving transistor DT. In a direction perpendicular to the base substrate, the portion of the semiconductor layer 230 overlapping with the first metal layer 210 includes a conductive portion 231 electrically connected to the second metal layer 220. The conductive portion 231 faces the first metal layer 210 to form a capacitor. For example, the portion of the conductive portion 231 facing the first capacitor electrode C11 can form the capacitance of the first capacitor C1 with the first capacitor electrode C11, and the portion of the conductive portion 231 facing the fourth capacitor electrode C24 can form the capacitance of the second capacitor C2 with the fourth capacitor electrode C24. The portion of the conductive portion overlapping with the first capacitor plate can also be referred to as the capacitor plate of the first capacitor C1, and the portion of the conductive portion overlapping with the fourth capacitor plate can also be referred to as the capacitor plate of the second capacitor C2. The capacitance of the first capacitor C1 can be adjusted by adjusting the area of ​​the first capacitor electrode C11, the area of ​​the second capacitor electrode C12, and the area of ​​the portion of the conductive portion directly opposite the first capacitor electrode C11. When adjusting the area of ​​each capacitor plate to adjust the capacitance of the first capacitor C1, the size of the capacitor plates of the first capacitor C1 must meet the requirements for rapid charging. The capacitance of the second capacitor C2 can be adjusted by adjusting the area of ​​the third capacitor electrode C23, the area of ​​the fourth capacitor electrode C24, and the area of ​​the portion of the conductive portion directly opposite the fourth capacitor electrode C24.

[0165] For example, Figures 2 to 5 As shown, the conductive portion 231 is electrically connected through a via 2310 located in the insulating layer between the semiconductor layer 230 and the second metal layer 220. For example, the orthographic projection of the via 2310 on the substrate is located at the interval between the orthographic projections of the first capacitor electrode and the fourth capacitor electrode on the substrate.

[0166] For example, Figures 2 to 5 As shown, the first capacitor electrode C11 includes a notch 2101. The two parts on both sides of the notch 2101 in the first direction include two channel regions of the driving transistor DT. The two channel regions overlap with the first capacitor electrode C11 in the first metal layer 210. The material of the channel region of the driving transistor DT is a semiconductor material, and the conductive part 231 outside the channel region is a conductor obtained by doping the semiconductor material.

[0167] For example, Figure 3 As shown, the driving transistor DT is a dual-gate transistor, for example, the driving transistor DT includes a sub-transistor DT1 and a sub-transistor DT2, which are connected in series. The embodiment of the present invention is described using the driving transistor DT as a dual-gate transistor as an example, but is not limited thereto. The driving transistor DT may also be a single-gate transistor.

[0168] In some examples, such as Figures 2 to 6 As shown, the pixel circuit further includes a data writing transistor T1, a second light emitting control transistor T2, a first reset transistor T5 and a second reset transistor T3; the plurality of signal lines further include a second light emitting control signal line EM1, a reset power signal line REF1, an initialization voltage signal line INI, a first scanning signal line G1, a second scanning signal line G3 and a third scanning signal line G2; a first electrode of the data writing transistor T1 is electrically connected to the data line DATA, a second electrode of the data writing transistor T1 is electrically connected to the gate of the driving transistor DT, the gate of the data writing transistor T1 is electrically connected to the first scanning signal line G1, a first electrode of the second light emitting control transistor T2 is electrically connected to the first power signal line 2181, and a second electrode of the second light emitting control transistor T2 is electrically connected to the gate of the driving transistor DT. The second electrode is electrically connected to the second electrode of the driving transistor DT, the gate of the second light-emitting control transistor T2 is electrically connected to the second light-emitting control signal line EM1, the first electrode of the first reset transistor T5 is electrically connected to the second electrode of the first light-emitting control transistor T4, the gate of the first reset transistor T5 is electrically connected to the second scanning signal line G3, the second electrode of the first reset transistor T5 is electrically connected to the initialization voltage signal line INI, the gate of the first light-emitting control transistor T4 is electrically connected to the first light-emitting control signal line EM2, the first electrode of the second reset transistor T3 is electrically connected to the reset power supply signal line REF1, the second electrode of the second reset transistor T3 is electrically connected to the first capacitor electrode C11, and the gate of the second reset transistor T3 is electrically connected to the third scanning signal line G2.

[0169] For example, the initialization voltage signal line INI is a signal line for applying an initialization voltage. The first power signal line 2181 is a signal line for applying a pixel driving voltage VDD.

[0170] For example, Figure 6 As shown, the second electrode of the data writing transistor T1, the second electrode of the second reset transistor T3, the gate of the driving transistor DT and the first capacitor electrode C11 of the first capacitor C1 are connected to the node N01, and the second electrode of the driving transistor DT and the second electrode of the second light emitting control transistor T2 are connected to the node N03.

[0171] It should be noted that Figure 2The dotted rectangular boxes in the figure show the parts where the semiconductor layer 230 overlaps with the first metal layer 210, namely the channel regions. As the channel regions of each transistor, the active semiconductor layer 230 on both sides of each channel region is conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiment of the present invention, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiment of the present invention can be interchangeable as needed.

[0172] The display panel provided by the embodiment of the present invention optimizes the balance between luminous uniformity and power consumption by matching the pattern design of the semiconductor layer with the channel of the driving transistor and the pattern design of the capacitor plate located in the semiconductor layer, thereby improving the luminous uniformity of the display panel and reducing power consumption.

[0173] For example, Figure 6 As shown, the transistors included in the pixel circuit can be implemented as oxide thin film transistors including n-channel oxide semiconductors, low-temperature polysilicon (LTPS) transistors including low-temperature polysilicon, etc. In the embodiment, the transistors of the pixel circuit are implemented as n-channel oxide transistors as an example, but the present invention is not limited thereto. Figure 6 It is schematically shown that the pixel circuit can be a 6T2C structure, but is not limited to this. The number of transistors in the pixel circuit is greater than or equal to 5, and the number of capacitors is greater than or equal to 2. For example, the number of transistors can be 5, 7, 8, 9, etc., and the number of capacitors can be 3, 4, etc., and the embodiment of the present invention does not limit this.

[0174] For example, Figure 3 and Figure 5 As shown, the first metal layer 210 further includes a first gate portion 211, a second gate portion 212, a third gate portion 213, a fourth gate portion 214 and a fifth gate portion 215. The first gate portion 211 overlaps with the first semiconductor portion 232 in the semiconductor layer 230 to serve as the gate of the data write transistor T1, the second gate portion 212 overlaps with the second semiconductor portion 233 in the semiconductor layer 230 to serve as the gate of the second light emission control transistor T2, the third gate portion 213 overlaps with the first semiconductor portion 232 in the semiconductor layer 230 to serve as the gate of the second reset transistor T3, the fourth gate portion 214 overlaps with the second semiconductor portion 233 in the semiconductor layer 230 to serve as the gate of the first light emission control transistor T4, and the fifth gate portion 215 overlaps with the second semiconductor portion 232 in the semiconductor layer 230 to serve as the gate of the first reset transistor T5.

[0175] For example, Figure 5 As shown, the channel regions of the data write transistor T1 and the second reset transistor T3 are two regions in the first semiconductor portion 232. For example, the channels of the data write transistor T1 and the second reset transistor T3 are integrated. For example, the two channel regions of the drive transistor DT, the channel region of the second emission control transistor T2, the channel region of the first emission control transistor T4, and the channel region of the first reset transistor T5 are different regions in the second semiconductor portion 233. For example, the second semiconductor portion 233 also includes a conductive portion 231. For example, the channels of the drive transistor DT, the second emission control transistor T2, the first emission control transistor T4, and the first reset transistor T5 and the conductive portion are integrated.

[0176] For example, Figure 3 As shown, at least one of the first gate portion 211, the second gate portion 212, the third gate portion 213, the fourth gate portion 214, and the fifth gate portion 215 is curved, thereby, at least one of the data write transistor T1, the second emission control transistor T2, the second reset transistor T3, the first emission control transistor T4, and the first reset transistor T5 is a dual-gate transistor, and in the same dual-gate transistor, the portion between the two channels is a conductor. The curved shape can be C-shaped, and is not limited to the opening direction of the curved shape. For example, the opening can be upward, downward, left, or right. For example, the direction indicated by the arrow in the X direction in the figure is upward, and the arrow in the Y direction is right. For example, the shape of the first gate portion 211, the second gate portion 212, the third gate portion 213, the fourth gate portion 214, and the fifth gate portion 215 are all curved, thereby, the data write transistor T1, the second emission control transistor T2, the second reset transistor T3, the first emission control transistor T4, and the first reset transistor T5 are all dual-gate transistors.

[0177] For example, Figure 3 As shown, the first gate portion 211 and the third gate portion 213 are located on one side of the first capacitor electrode C11, and the second gate portion 212, the fourth gate portion 214, and the fifth gate portion 215 are located on the other side of the first capacitor electrode C11. For example, the openings in the first gate portion 211 and the third gate portion 213 are oriented in the same direction, such as both facing downward. For example, the third gate portion 213 is located on the side of the first gate portion 211 away from the first capacitor electrode C11. For example, the fourth gate portion 214 is closer to the fourth capacitor electrode C24 than the fifth gate portion 215. For example, the second gate portion 212 is farther away from the first capacitor electrode C11 than the fourth gate portion 214. For example, the openings of the second gate portion 212 and the fifth gate portion 215 are oriented in the same direction, such as both facing left. For example, the fourth gate portion 214 and the fifth gate portion 215 are oriented in opposite directions, such as towards the right.

[0178] For example, Figure 3 As shown, a straight line extending along the first direction and passing through the interval between the first capacitor electrode C11 and the fourth capacitor electrode C24 passes through the fourth gate portion 214, and the second gate portion 212 and the fifth gate portion 215 are located on both sides of the straight line in the second direction. For example, a straight line extending along the first direction passes through the first capacitor electrode C11, the first gate portion 211, the second gate portion 212, and the third gate portion 213.

[0179] For example, Figure 2 and Figure 3 As shown, the first metal layer 210 further includes a connecting portion 216 , and the first electrode of the second reset transistor T3 is electrically connected to the reset power signal line REF1 through the connecting portion 216 .

[0180] For example, Figure 2 and Figure 4 As shown, the second metal layer 220 includes a connecting portion 221 and a connecting portion 222. The second electrode of the data write transistor T1 is electrically connected to the conductive portion in the semiconductor layer 230 via the connecting portion 221 to achieve electrical connection with the gate of the drive transistor DT. The data line DATA includes two portions located in a first direction of the connecting portion 222, and these two portions are electrically connected via the connecting portion 222. For example, the connecting portion 222 can also be referred to as a portion of the data line DATA. For example, the connecting portion 222 is located between the first scan signal line G1 and the first light emission control signal line EM2. For example, the connecting portion 221 is located between the second capacitor electrode C12 and the first scan signal line G1. For example, the second capacitor electrode C12 is provided with a notch, and the connecting portion 221 is inserted into the notch.

[0181] In an embodiment of the present invention, components located in the first metal layer can be connected to components located in the second metal layer and components located in the semiconductor layer through vias in an insulating layer disposed between adjacent layers. For example, the insulating layer that the via penetrates can be determined based on the insulating layer between the two pattern layers connected by the via.

[0182] For example, Figures 2 to 5As shown, the first semiconductor portion 232 includes two strip portions extending along the second direction and one strip portion extending along the first direction and connecting the two strip portions, the two strip portions include a first strip portion and a second strip portion, the one strip portion includes a third strip portion, the first strip portion includes a channel of the data write transistor T1, the second strip portion includes a channel of the second reset transistor T3, the distance between the end of the first strip portion close to the data line DATA and the first power signal line 2181 is greater than the distance between the end of the second strip portion close to the data line DATA and the first power signal line 2181, and the distance between the end of the first strip portion away from the data line DATA and the first power signal line 2181 is greater than the distance between the end of the second strip portion away from the data line DATA and the first power signal line 2181. For example, the portion of the first strip portion close to the data line DATA is connected to the connecting portion 216, the portion of the second strip portion close to the data line DATA is connected to the portion of the data line DATA that protrudes toward the first semiconductor portion 232, and the portion of the second strip portion away from the data line DATA is connected to the gate of the driving transistor DT through the connecting portion 221.

[0183] For example, Figure 2 As shown, the first electrode 310 of the light emitting element 300 (see Figure 31 ) and the second electrode of the first light emission control transistor T4 are provided with a via 2320 and a via 2330, so that the first electrode is electrically connected to the second electrode of the first light emission control transistor T4 through the via 2320 and the anode via 2330.

[0184] For example, Figure 2 As shown, the distance between the first light-emitting control signal line EM2 and the second scanning signal line G3 is greater than the distance between the second scanning signal line G3 and the second light-emitting control signal line EM1, so as to facilitate the setting of the position of the anode via 2330 while achieving a compact setting of the pixel layout.

[0185] For example, Figure 2As shown, one end of the connecting portion 216 is electrically connected to the reset power signal line REF1 through a via 2311 in the insulating layer between the connecting portion 216 and the reset power signal line REF1, and the other end of the connecting portion 216 is electrically connected to the first semiconductor portion 232 through a via 2312 in the insulating layer between the connecting portion 216 and the first semiconductor portion 232. For example, the third gate portion 213 is electrically connected to the third scan signal line G2 through a via 2313 in the insulating layer between the third gate portion 213 and the third scan signal line G2, and the fourth gate portion 214 is electrically connected to the first scan signal line G1 through a via 2314 in the insulating layer between the fourth gate portion 214 and the first scan signal line G1. For example, the first semiconductor portion 232 is electrically connected to the data line DATA through a via 2315 in the insulating layer between the first semiconductor portion 232 and the data line DATA. For example, the two ends of the connecting portion 222 are electrically connected through vias 2316, 2319, and 2321 in the insulating layer between the connecting portion 222 and the data line DATA, respectively. For example, the first semiconductor portion 232 is electrically connected to the connecting portion 221 via a via 2317 in the insulating layer between the first semiconductor portion 232 and the connecting portion 221. For example, the connecting portion 221 is electrically connected to the conductive portion 231 via a via 2318 in the insulating layer between the first semiconductor portion 232 and the conductive portion 231. For example, the fourth gate portion 214 is electrically connected to the first emission control signal line EM2 via a via 2322 in the insulating layer between the fourth gate portion 214 and the first emission control signal line EM2. For example, the fifth gate portion 215 is electrically connected to the second scan signal line G3 via a via in the insulating layer between the fifth gate portion 215 and the second scan signal line G3. For example, the semiconductor layer 230 is electrically connected to the initialization voltage signal line INI via a via 2324 in the insulating layer between the semiconductor layer 230 and the initialization voltage signal line INI. For example, the second gate portion 212 is electrically connected to the second emission control signal line EM1 via a via 2325 in the insulating layer between the second gate portion 212 and the second emission control signal line EM1.

[0186] In some examples, such as Figures 2 to 6 As shown, the display panel further includes a reference signal line 217 electrically connected to the fourth capacitor electrode C24 and configured to transmit a constant voltage signal to the fourth capacitor electrode C24. At least a portion of the reference signal line 217 extends along the first direction.

[0187] In some examples, such as Figure 2 and Figure 6 As shown, the reference signal line 217 is configured to transmit one of a pixel driving voltage signal, a low potential power supply voltage signal, a reference voltage signal, and an initialization voltage signal. For example, the constant voltage can be any one of the pixel driving voltage ELVDD, the low potential power supply voltage ELVSS, the reference voltage Vref, and the initialization voltage Vinit.

[0188] In some examples, such as Figures 1 to 5As shown, the reference signal line 217 is located between the second metal layer 220 and the base substrate. The second metal layer 220 includes multiple signal lines arranged along a first direction. Along a direction perpendicular to the base substrate, the reference signal line 217 overlaps with at least three of the multiple signal lines.

[0189] In some examples, such as Figure 2 As shown, along a direction perpendicular to the substrate, the first emission control signal line EM2, the second scan signal line G3, and the initialization voltage signal line INI all overlap with the reference signal line 217, and the first emission control signal line EM2 is located between the first capacitor electrode C11 and the initialization voltage signal line INI. For example, the at least three signal lines include the first emission control signal line EM2, the second scan signal line G3, and the initialization voltage signal line INI.

[0190] In some examples, such as Figure 2 and Figure 3 As shown, the reference signal line 217 is located in the first metal layer 210, and the reference signal line 217 is located between at least a portion of the fourth capacitor electrode C24 and the first power signal line 2181. For example, there are multiple reference signal lines 217, and the fourth capacitor electrodes C24 of the second capacitors C2 in multiple pixel circuits arranged along the first direction are electrically connected to the same reference signal line 217, while the fourth capacitor electrodes C24 of the second capacitors C2 in different pixel circuits arranged along the second direction are electrically connected to different reference signal lines 217.

[0191] In some examples, such as Figure 2 and Figure 3 As shown, the reference signal line 217 is configured to transmit a reference voltage signal Vref. For example, the reference signal line 217 is independently controlled to transmit a constant voltage signal.

[0192] In some examples, such as Figure 3 As shown, the reference signal line 217 and at least a portion of the fourth capacitor electrode C24 of the second capacitor C2 are integrated. For example, the fourth capacitor electrode C24 of the second capacitor C2 and the reference signal line 217 are integrated.

[0193] For example, Figure 2 As shown, the positive projection of the reference signal line 217 on the substrate passes through the reset power signal line REF1, the third scanning signal line G2, the first scanning signal line G1, the first light-emitting control signal line EM2, the second scanning signal line G3, the initialization voltage signal line INI and the positive projection of the second light-emitting control signal line EM1 on the substrate.

[0194] In another example of the embodiment of the present invention, Figures 2 to 6As shown, the reference signal line 217 is configured to transmit a low potential power supply voltage signal VSS.

[0195] In the embodiment of the present invention, the pixel circuit layout may have the same structure in the example where the reference signal line 217 transmits the reference voltage signal Vref and the example where the reference signal line 217 transmits the low potential power supply voltage signal VSS. Figures 2 to 5 The structure shown in FIG. 1 and the equivalent circuit of the pixel circuit have the same features except that the fourth capacitor electrode C24 of the second capacitor C2 is connected to a different constant voltage, which will not be described in detail here.

[0196] Figure 7 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 7 The structure shown is Figure 2 The difference between the structures shown is that the second metal layer 220 further includes a second power signal line VSS extending along the second direction.

[0197] In some examples, such as Figure 7 As shown, the second metal layer 220 includes a second power signal line VSS extending along the second direction. The second power signal line VSS is located between adjacent pixel circuits. The reference signal line 217 is electrically connected to the second power signal line VSS to receive a low-potential power supply voltage signal. For example, there may be multiple second power signal lines VSS, with one second power signal line VSS provided between adjacent pixel circuits arranged along the first direction, such as one second power signal line VSS provided between adjacent first capacitors C1. Each reference signal line 217 is electrically connected to at least one second power signal line VSS. For example, the multiple second power signal lines VSS and the multiple reference signal lines 217 may form a grid, which helps reduce resistance and thus power consumption.

[0198] In some examples, the reference signal line 217 is configured to transmit a pixel driving voltage signal.

[0199] Figure 8 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 8 The structure shown is Figure 2 The difference between the structures shown is that the reference signal line 217 is configured to transmit the pixel driving voltage signal VDD. In the embodiment of the present invention, Figure 2 The pixel circuit shown is Figure 8 The equivalent circuit of the pixel circuit shown has the same features except that the fourth capacitor electrode C24 of the second capacitor C2 is connected to a different constant voltage, which will not be described again. Figure 8 The pixel circuit shown is Figure 2The pixel circuit shown in FIG. 1 is similar to the pixel circuit shown in FIG. 1 except that the connection relationship of the reference signal line 217 is different. Figure 2 The corresponding structures shown have the same features and will not be described again here.

[0200] In some examples, such as Figure 8 As shown, the second metal layer 220 includes a third power signal line 2182 extending along the second direction. The third power signal line 2182 is located on a side of the initialization voltage signal line INI away from the first emission control signal line EM2. The reference signal line 217 is electrically connected to the third power signal line 2182 to receive the pixel driving voltage signal. For example, the third power signal line 2182 is located on a side of the second emission control signal line EM1 away from the initialization voltage signal line INI.

[0201] For example, Figure 8 As shown, the first electrode of the second light emission control transistor T2 is electrically connected to the third power signal line 2182 via a via 2327 in the insulating layer between the first electrode and the third power signal line 2182. For example, the first power signal line 2181 is electrically connected to the third power signal line 2182 via a via 2326 in the insulating layer between the first electrode and the third power signal line 2182. For example, the reference signal line 217 is electrically connected to the third power signal line 2182 via a via 2328 in the insulating layer between the first electrode and the third power signal line 2182.

[0202] In some examples, such as Figure 8 As shown, the reference signal line 217 is located between at least a portion of the fourth capacitor electrode C24 and the first power signal line 2181, and the first power signal line 2181 is electrically connected to the third power signal line 2182. For example, there are multiple third power signal lines 2182, and each reference signal line 217 is electrically connected to at least one third power signal line 2182. For example, the multiple first power signal lines 2181 and the multiple third power signal lines 2182 form a grid. For example, the multiple reference signal lines 217 and the multiple third power signal lines 2182 form a grid.

[0203] By setting a third power signal line and setting both the reference signal line and the first power signal line to be electrically connected to the third power signal line, a constant voltage can be provided to the fourth capacitor electrode of the second capacitor while further improving the display uniformity of medium and large-sized display panels.

[0204] Figure 9 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 9 The structure shown is Figure 8 The difference between the structures shown is that the reference signal line 217 and the first power signal line 2181 are integrated into one structure. Figure 9The pixel circuit shown is Figure 2 The pixel circuit shown in FIG. 1 is similar to the pixel circuit shown in FIG. 1 except that the connection relationship of the reference signal line 217 is different. Figure 2 The corresponding structures shown have the same features and will not be described again here.

[0205] For example, Figure 8 As shown, the fourth capacitor electrode C24 of the second capacitor C2 is electrically connected to the first power signal line 2181. For example, the fourth capacitor electrode C24 of the second capacitor C2 and the first power signal line 2181 are integrally provided.

[0206] By setting the reference signal line for transmitting the pixel driving voltage signal as a structure that is integrated with the first power signal line, that is, the first power signal line is electrically connected to the fourth capacitor electrode of the second capacitor, there is no need to set up an additional signal line, which is beneficial to saving design space of the pixel circuit layout.

[0207] Figure 10 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 11 for Figure 10 Schematic diagram of the stacking relationship between the first metal layer and the third metal layer in the structure shown. Figure 12 for Figure 10 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown. Figure 13 for Figure 10 Schematic diagram of the stacking relationship between the second metal layer and the third metal layer in the structure shown.

[0208] Figure 10 The structure shown is Figure 1 The difference from the structure shown is that the display panel further includes a third metal layer 240 . Figure 10 The layout design of the pixel circuit shown is similar to Figure 9 In the layout design of the pixel circuit shown, other structures except the third metal layer 240 and the first power signal line 2181 may have the same features.

[0209] In some examples, such as Figures 10 to 13 As shown, the third metal layer 240 is located between the semiconductor layer 230 and the base substrate; perpendicular to the direction of the base substrate, the second capacitor electrode C12 and the first power signal line 2181 both overlap with the third metal layer 240, and the third metal layer 240 is configured to receive a pixel driving voltage signal.

[0210] The third metal layer 240 can shield the channel region in the semiconductor layer 230 from light while overlapping with the second capacitor electrode C12 to form the capacitance of the first capacitor C1, and overlapping with the third capacitor electrode C23 to form the capacitance of the second capacitor C2. For example, the portion of the third metal layer 240 overlapping with the second capacitor electrode C12 can be referred to as the capacitor plate of the first capacitor C1, and the portion of the third metal layer 240 overlapping with the third capacitor electrode C23 can be referred to as the capacitor plate of the second capacitor C2.

[0211] In some examples, such as Figure 10 As shown, the third metal layer 240 is electrically connected to the first power signal line 2181. For example, the third metal layer 240 is electrically connected to the first power signal line 2181 through a via 241 in the insulating layer between the third metal layer 240 and the first power signal line 2181. For example, the number of vias 241 can be one or more. For example, if there are multiple vias 241, the multiple vias 241 can be arranged in two columns, and the two columns of vias 241 can be arranged along the second direction.

[0212] For example, relative to Figure 9 The first power signal line 2181 in the pixel circuit shown in FIG. 2 is not provided with the third metal layer 240. Figure 10 As shown, the width of the first power signal line 2181 electrically connected to the third metal layer 240 is wider to facilitate the setting of the position and number of the vias 241.

[0213] Figure 14 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 15 for Figure 14 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown.

[0214] Figure 14 The structure shown is Figure 10 The structure shown differs in that the third metal layer 240 overlaps the channel regions of at least some of the plurality of transistors.

[0215] In some examples, such as Figure 14 and Figure 15As shown, the pixel circuit includes multiple transistors, including at least a driving transistor DT, a first light-emitting control transistor T4, and a first reset transistor T5. The third metal layer 240 overlaps with the channel regions of at least some of the multiple transistors to shield the channel regions of at least some of the transistors from light. In this embodiment of the utility model, the overlap of the third metal layer 240 with the channel region of the transistor means that the third metal layer 240 overlaps with the channel region of the transistor in a direction perpendicular to the substrate, such as the orthographic projection of the third metal layer 240 on the substrate overlaps with the orthographic projection of the channel region of the transistor on the substrate.

[0216] For example, Figure 14 and Figure 15 As shown, the third metal layer 240 overlaps with the channel regions of the driving transistor DT, the data writing transistor T1, the second light emission control transistor T2, the second reset transistor T3, the first light emission control transistor T4 and the first reset transistor T5 to shield the channel regions of each transistor from light.

[0217] For example, Figure 14 and Figure 15 As shown, the portion of the third metal layer 240 that overlaps with the channel region of the drive transistor DT, the portion that overlaps with the channel region of the data write transistor T1, the portion that overlaps with the channel region of the second reset transistor T3, and the portion that overlaps with the channel region of the first emission control transistor T4 are integrated into a structure. For example, the third metal layer 240 also includes multiple overlapping portions 242, such as two overlapping portions 242, which overlap with the channel region of the second emission control transistor T2 and the channel region of the first reset transistor T5, respectively. However, this is not limiting, and the portions of the third metal layer 240 that overlap with the channel regions of different transistors can be spaced apart from each other.

[0218] For example, Figure 14 As shown, the third metal layer 240 is electrically connected to the first power signal line 2181 through a via 241 in the insulation layer between the third metal layer 240 and the first power signal line 2181 .

[0219] Figure 16 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 17 for Figure 16 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown. Figure 18 for Figure 16 Schematic diagram of the third metal layer in the shown structure.

[0220] Figure 16 The structure shown is Figure 14The difference of the structure shown is that the third metal layer 240 is not electrically connected to the first power signal line 2181 through a via in the insulating layer between the third metal layer 240 and the first power signal line 2181 .

[0221] For example, Figures 16 to 18 As shown, the third metal layer 240 includes an overlapping portion that overlaps with the channel region of a transistor, such as the channel region of the driving transistor DT, and a signal line portion 243 that connects the overlapping portion and extends along the second direction. The signal line portion 243 is configured to transmit the pixel driving voltage signal VDD. For example, the signal line portion 243 is configured to be electrically connected to a pixel driving power supply located in the peripheral area of ​​the display panel.

[0222] For example, Figures 16 to 18 As shown, the third metal layer 240 overlaps with the channel regions of at least some of the transistors. For example, the third metal layer 240 overlaps with the channel regions of each transistor to shield the channel regions of each transistor from light.

[0223] For example, Figures 16 to 18 As shown, the portion of the third metal layer 240 that overlaps with the channel region of each transistor can be an integrated structure. For example, the portion of the third metal layer 240 that overlaps with the channel region of the drive transistor DT, the channel region of the data write transistor T1, the channel region of the second reset transistor T3, and the channel region of the first emission control transistor T4 can be a monolithic structure 245. The overlapping portion 242 of the third metal layer 240 that overlaps with the channel region of the second emission control transistor T2 and the channel region of the first reset transistor T5 can be connected to the monolithic structure 245 via a connecting portion 246. For example, the third metal layer 240 further includes a signal line portion 244 extending along the first direction, which is connected to the overlapping portion 242.

[0224] By providing a signal line portion extending along the first direction and the second direction in the third metal layer, an integrated structure of the third metal layer can be achieved, thereby improving the uniformity of the power supply voltage signal VDD in the display panel.

[0225] Figure 19 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 20 for Figure 19 Schematic diagram of the stacking relationship between the semiconductor layer and the third metal layer in the structure shown. Figure 19 The structure shown is Figure 11 The difference between the structures shown is that the third metal layer 240 is not electrically connected to the first power signal line 2181 .

[0226] In some examples, such as Figure 19 and Figure 20As shown, the pixel circuit includes multiple transistors, which include at least a driving transistor DT, a first light-emitting control transistor T4 and a first reset transistor T5. Along the direction perpendicular to the substrate, the third metal layer 240 overlaps with the channel region of at least some of the multiple transistors.

[0227] For example, Figure 19 and Figure 20 As shown, the third metal layer 240 only overlaps the channel region of the driving transistor DT along a direction perpendicular to the substrate. For example, the third metal layer 240 does not overlap the portion of the first power signal line 2181 extending along the first direction along the direction perpendicular to the substrate.

[0228] For example, Figure 19 As shown, along a direction perpendicular to the substrate, the third metal layer 240 overlaps the first capacitor electrode C11 of the first capacitor C1 and the fourth capacitor electrode C24 of the second capacitor C2. For example, along a direction perpendicular to the substrate, the third metal layer 240 does not overlap with the reset power signal line REF1, the third scan signal line G2, the first scan signal line G1, the first light-emitting control signal line EM2, the second scan signal line G3, the initialization voltage signal line INI, the second light-emitting control signal line EM1, and the third power signal line 2182.

[0229] Figure 21 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 22 for Figure 21 Schematic diagram of the stacking relationship between the semiconductor layer 230 and the third metal layer 240 in the structure shown. Figure 21 The structure shown is Figure 11 The difference between the structures shown is that the third metal layer 240 is not electrically connected to the first power signal line 2181 .

[0230] For example, Figure 21 and Figure 22 As shown, along the direction perpendicular to the substrate, the third metal layer 240 overlaps with the channel region of the driving transistor DT, the channel region of the data writing transistor T1, the channel region of the second light-emitting control transistor T2, the channel region of the second reset transistor T3, the channel region of the first light-emitting control transistor T4, and the channel region of the first reset transistor T5, so as to shield the channel region of each transistor.

[0231] For example, Figure 21As shown, along a direction perpendicular to the substrate, the third metal layer 240 overlaps the third scan signal line G2, the first scan signal line G1, the first light emission control signal line EM2, the second scan signal line G3, the initialization voltage signal line INI, and the second light emission control signal line EM1. For example, along a direction perpendicular to the substrate, the third metal layer 240 does not overlap the reset power signal line REF1 and the third power signal line 2182.

[0232] Figure 23 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 24 for Figure 23 Schematic diagram of the semiconductor layer 230 in the illustrated structure. Figure 25 for Figure 23 Equivalent circuit diagram of the pixel circuit shown.

[0233] Figure 23 The structure shown is Figure 2 The difference of the illustrated structure is that the reference signal line 217 is configured to transmit an initialization voltage signal. Figure 25 The equivalent circuit diagram shown is Figure 6 The difference between the illustrated equivalent circuit diagram is that the reference signal line 217 is configured to transmit an initialization voltage signal.

[0234] In some examples, such as Figures 23 to 25 As shown, the semiconductor layer 230 includes a reference signal line 217, and the fourth capacitor electrode C24 of the second capacitor C2 is electrically connected to the first electrode of the first reset transistor T5 through the reference signal line 217. For example, when the first reset transistor T5 is in an on state, the initialization voltage signal is input to the reference signal line 217 through the first reset transistor T5, and is transmitted to the fourth capacitor electrode C24 of the second capacitor C2 through the reference signal line 217.

[0235] By setting the position of the reference signal line and transmitting the initialization voltage signal, no additional wiring is required, which is conducive to saving space in the pixel circuit layout.

[0236] In some examples, such as Figure 23 and Figure 24 As shown, the reference signal line 217 and the first electrode of the first reset transistor T5 are integrated into one structure.

[0237] For example, Figure 23As shown, the reference signal line 217 is electrically connected to the fourth capacitor electrode C24 via a via 2329 in the insulating layer between the reference signal line 217 and the fourth capacitor electrode C24. For example, the reference signal line 217 extends along the first direction. For example, the reference signal line 217 and the second electrode of the first emission control transistor T4 are integrally arranged. For example, the reference signal line 217 and the channel region of the first reset transistor T5 are located on a straight line extending along the first direction. For example, the fourth capacitor electrode C24 is closer to the first emission control signal line EM2 than the first capacitor electrode C11 to achieve electrical connection between the fourth capacitor electrode C24 and the reference signal line 217.

[0238] For example, Figure 23 As shown, in a direction perpendicular to the substrate, the reference signal line 217 overlaps with the first light-emitting control signal line EM2, the second scan signal line G3, and the initialization voltage signal line INI. For example, in a direction perpendicular to the substrate, the reference signal line 217 does not overlap with the second light-emitting control signal line EM1, the third power signal line 2182, the first scan signal line G1, the third scan signal line G2, and the reset power signal line REF1.

[0239] For example, Figure 23 As shown, the distance between the fourth capacitor electrode C24 and the first power signal line 2181 is smaller than the distance between the reference signal line 217 and the first power signal line 2181 .

[0240] Figure 26 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 27 for Figure 26 Schematic diagram of the first metal layer in the shown structure. Figure 28 for Figure 26 Equivalent circuit diagram of the pixel circuit shown.

[0241] Figure 26 The structure shown is Figure 2 The difference of the illustrated structure is that the reference signal line 217 is configured to transmit an initialization voltage signal. Figure 28 The equivalent circuit diagram shown is Figure 6 The difference between the illustrated equivalent circuit diagram is that the reference signal line 217 is configured to transmit an initialization voltage signal.

[0242] In some examples, such as Figures 26 to 28As shown, the first metal layer 210 includes a reference signal line 217, and the fourth capacitor electrode C24 is electrically connected to the initialization voltage signal line INI through the reference signal line 217. For example, the reference signal line 217 can be electrically connected to the initialization voltage signal line INI. For example, the reference signal line 217 can be electrically connected to the initialization voltage signal line INI through a via 2331 in the insulating layer between the reference signal line 217 and the initialization voltage signal line INI.

[0243] By setting the position of the reference signal line to transmit the initialization voltage signal, no additional wiring is required, which is beneficial to saving space in the pixel circuit layout.

[0244] For example, Figures 26 to 28 As shown, the reference signal line 217 is electrically connected to the second electrode of the first reset transistor T5.

[0245] In some examples, such as Figure 26 As shown, the reference signal line 217 and the fourth capacitor electrode C24 are integrally configured. For example, the reference signal line 217 is located between the channel region of the first reset transistor T5 and the first power signal line 2181. For example, the distance between the fourth capacitor electrode C24 and the first power signal line 2181 is greater than the distance between the reference signal line 217 and the first power signal line 2181.

[0246] For example, Figure 26 As shown, in a direction perpendicular to the substrate, the reference signal line 217 overlaps with the first light-emitting control signal line EM2, the second scan signal line G3, and the initialization voltage signal line INI. For example, in a direction perpendicular to the substrate, the reference signal line 217 does not overlap with the second light-emitting control signal line EM1, the third power signal line 2182, the first scan signal line G1, the third scan signal line G2, and the reset power signal line REF1.

[0247] Figure 29 for Figure 1 A schematic diagram of a pixel circuit stacking structure in an example of the embodiment shown. Figure 30 for Figure 29 Schematic diagram of the semiconductor layers in the shown structure. Figure 29 The equivalent circuit diagram of the pixel circuit shown can be Figure 6 The equivalent circuit is shown. Figure 29 The pixel circuit shown is Figure 2 The pixel circuit shown is different in that the shape of the semiconductor layer 230 is different, and the areas of the first capacitor electrode C11 and the fourth capacitor electrode C24 are different.

[0248] For example, Figure 29 and Figure 30As shown, the portion of the semiconductor layer 230 overlapping the first capacitor electrode C11 has an inverted U-shape. For example, the driving transistor DT is a single-gate transistor.

[0249] For example, Figure 29 As shown, the semiconductor layer 230 is electrically connected to the second capacitor electrode through a via 2310 in the insulating layer between the semiconductor layer 230 and the second capacitor electrode.

[0250] For example, Figure 29 As shown, the area of ​​the first capacitor electrode C11 is larger than the area of ​​the fourth capacitor electrode C24. For example, in the first direction, the size of the first capacitor electrode C11 is smaller than the size of the second capacitor electrode C12. For example, in the first direction, the size of the fourth capacitor electrode C24 is larger than the size of the first capacitor electrode C11. For example, in the second direction, the size of the first capacitor electrode C11 is larger than the size of the fourth capacitor electrode C24. For example, the fourth capacitor electrode C24 can be integrated with the reference signal line 217.

[0251] For example, Figure 29 As shown, along a direction perpendicular to the substrate, the fourth capacitor electrode C24 does not overlap with the semiconductor layer 230. For example, along a direction perpendicular to the substrate, the first capacitor electrode C11 overlaps with the semiconductor layer 230. The portion of the semiconductor layer 230 overlapping with the first capacitor electrode C11 can serve as a plate of the first capacitor C1. The capacitance of the first capacitor C1 can be adjusted by adjusting the area of ​​the portion of the semiconductor layer 230 overlapping with the first capacitor electrode C11, the area of ​​the first capacitor electrode C11, and the area of ​​the second capacitor electrode C12.

[0252] Figure 29 In the display panel shown in FIG, other structures except the semiconductor layer 230, the first capacitor electrode C11 and the fourth capacitor electrode C24 can be Figure 2 The corresponding structures in the display panel shown have the same features, which will not be described in detail here.

[0253] Figure 31 A diagram showing the stacking relationship between a portion of the pixel circuit and the first electrode of the light-emitting element. Figure 32 For the Figure 31 The schematic diagram of the local cross-section structure taken along line AA' is shown. Figure 31 Only the first electrode 310 of the light emitting element 300 is schematically shown, and the light emitting functional layer 330 and the second electrode 320 of the light emitting element 300 are not shown. Figure 31 Schematically showing four pixel circuits, the four pixel circuits can be Figure 9 The pixel circuit shown is, but not limited to, the four pixel circuits can also be Figure 2 、 Figure 7 、 Figure 8 、 Figure 10 、 Figure 14 、 Figure 16 、 Figure 19 、 Figure 21 、 Figure 23 、 Figure 26 、 Figure 29 Pixel circuit in any of the examples shown.

[0254] In some examples, such as Figure 31 and Figure 32 As shown, the display panel includes multiple light-emitting elements 300, each of which includes a first electrode 310, a light-emitting functional layer 330, and a second electrode 320 stacked in sequence. The first electrode 310 is located between the light-emitting functional layer 330 and the base substrate 01 and is electrically connected to the pixel circuit. The number of metal layers between the semiconductor layer 230 and the first electrode 310 of the light-emitting element 300 is N1, and N1 is not greater than 2.

[0255] In some examples, each pixel circuit includes multiple transistors and multiple capacitors, the number of the multiple transistors is greater than or equal to 5, and the number of the capacitors is greater than or equal to 2. Figure 28 It is schematically shown that the pixel circuit can be a 6T2C structure, but is not limited to this. The number of transistors in the pixel circuit is greater than or equal to 5, and the number of capacitors is greater than or equal to 2. For example, the number of transistors can be 5, 7, 8, 9, etc., and the number of capacitors can be 3, 4, etc., and the embodiment of the present invention does not limit this.

[0256] By setting the number of metal layers between the semiconductor layer and the first electrode of the light-emitting element, it is beneficial to reduce the number of masks, improve the yield of the display panel, and reduce costs.

[0257] For example, Figure 32 As shown, the number of metal layers between the semiconductor layer 230 and the first electrode 310 of the light-emitting element 300 can be two layers, such as the first metal layer 210 and the second metal layer 220. However, the present invention is not limited thereto, and the number of metal layers disposed between the semiconductor layer 230 and the first electrode 310 of the light-emitting element 300 can be one layer.

[0258] For example, Figure 32 As shown, an insulating layer 02 is provided between the semiconductor layer 230 and the first metal layer 210 , and an insulating layer 03 is provided between the first metal layer 210 and the second metal layer 220 .

[0259] In some examples, such as Figure 31 and Figure 32 As shown, the number of the planar layers 04 disposed between the semiconductor layer 230 and the first electrode of the light emitting element 300 is N2, and N2 is not greater than 1.

[0260] By matching the number of planar layers and the number of metal layers between the semiconductor layer and the first electrode of the light-emitting element, it is beneficial to reduce the number of masks while improving the flatness of the film layer in the effective light-emitting area of ​​the light-emitting element and reducing color deviation.

[0261] For example, Figure 32 As shown, the number of the planar layer 04 provided between the semiconductor layer 230 and the first electrode 30 of the light emitting element 300 is one.

[0262] In some examples, such as Figure 31 and Figure 32 As shown, the display panel also includes a pixel-defining pattern 400 located on the side of the second metal layer 220 away from the base substrate 01. The pixel-defining pattern 400 includes a plurality of pixel openings 420 and a pixel-defining portion 410 surrounding the plurality of pixel openings 420. The plurality of pixel openings 420 are configured to define the light-emitting areas 3000 of the plurality of sub-pixels. For example, the light-emitting areas 3000 of the sub-pixels can be a two-dimensional pattern projected by the pixel openings 420 on the base substrate. For example, the pixel openings 420 are configured to expose the first electrodes 310. For example, each sub-pixel corresponds to a pixel opening 420. The light-emitting functional layer 330 located within the pixel opening 420 emits light by contacting the first and second electrodes 310 and 320. The first electrode injects holes into the light-emitting layer of the light-emitting functional layer, and the second electrode injects electrons into the light-emitting layer. The injected electrons and holes form excitons (i.e., electron-hole pairs) in the light-emitting layer. The excitons return to the ground state through radiative transitions, emitting photons. It can be seen that in the process of luminescence, efficient charge generation, effective charge injection, and rapid charge transport are three indispensable processes. The above charges are holes or electrons.

[0263] For example, Figure 32 As shown, the material of the pixel defining portion 410 includes an organic material, but is not limited thereto and may also include an inorganic material. For example, the material of the pixel defining portion 410 may include polyimide, acrylic, or polyethylene terephthalate.

[0264] In some examples, such as Figure 1 As shown, a plurality of pixel circuits 100 are arranged in an array along a first direction and a second direction. For example, the first direction may be an X direction, and the second direction may be a Y direction. The size of the pixel circuit in one of the first and second directions is 90 to 180 microns, and the sum of the sizes of two or three pixel circuits in the other of the first and second directions is 90 to 180 microns.

[0265] The aforementioned "the sum of the dimensions of two pixel circuits or three pixel circuits in the other of the first direction and the second direction" may include the sum of the dimensions of each pixel circuit in the same direction (the first direction or the second direction) and the distance between adjacent pixel circuits. For example, the first direction may be vertical, and the second direction may be horizontal.

[0266] Compared to display panels with small pixel circuits and multiple metal layers, the display panel provided by the present invention reduces the number of metal layers provided between the semiconductor layer and the first electrode of the light-emitting element by adjusting the size of the pixel circuit, such as by designing the pixel circuit to be larger, such as with a width greater than 30 microns. This reduces the number of masking steps and improves the yield of the display panel. The display panel provided by the present invention can be used in automotive display devices.

[0267] For example, Figure 1 and Figure 31 As shown, when the sum of the sizes of two pixel circuits or three pixel circuits is 90 to 180 microns, the above two pixel circuits or three pixel circuits are used as a pixel circuit group, and the shape of the pixel circuit group can be rectangular. The same pixel circuit group is the pixel circuit in a pixel unit. If the pixel unit includes sub-pixels of different colors, the pixel circuits in the same pixel circuit group are configured to be electrically connected to the first electrode of the light-emitting element emitting light of different colors. For example, the same pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. For example, the shape of the above pixel circuit group can be square.

[0268] For example, Figure 1 and Figure 31 As shown, the size of the pixel circuit 100 in the first direction can be 90-180 microns, and the sum of the sizes of the three pixel circuits 100 in the second direction is 90-180 microns. For example, the size of the same pixel circuit 100 in the first direction is larger than the size in the second direction.

[0269] For example, Figure 1 and Figure 31As shown, the sizes of different pixel circuits 100 in the first direction can be equal. For example, the sizes of different pixel circuits 100 in the second direction can be the same or different. For example, in the second direction, the size of the pixel circuit electrically connected to the light-emitting element 300 that emits blue light is larger than the size of the pixel circuit electrically connected to the light-emitting element 300 that emits at least one of red light and green light. For example, in the second direction, the size of the pixel circuit electrically connected to the light-emitting element 300 that emits blue light is twice the size of the pixel circuit electrically connected to the light-emitting element 300 that emits at least one of red light and green light. For example, the size of the pixel circuit of the blue sub-pixel in the second direction can be 70 to 80 microns, and the size of the pixel circuits of the green sub-pixel and the red sub-pixel in the second direction can be 35 to 40 microns.

[0270] For example, Figure 1 and Figure 31 As shown, the size of the pixel circuit 100 in one of the first and second directions is 100-150 microns, and the sum of the sizes of the two pixel circuits 100 or three pixel circuits 100 in the other of the first and second directions is 100-150 microns. For example, the size of the pixel circuit 100 in one of the first and second directions is 80-120 microns, and the sum of the sizes of the two pixel circuits 100 or three pixel circuits 100 in the other of the first and second directions is 80-120 microns. In the embodiments of the present invention, the numerical ranges of the sizes of the above-mentioned pixel circuits are not listed one by one. The size of the pixel circuit in one direction can be any value between 90 and 180, and the sum of the sizes of the two pixel circuits or three pixel circuits in the other direction can be any value between 90 and 180.

[0271] Figure 33 The diagram shows an arrangement of sub-pixels in a display panel according to an embodiment of the present invention.

[0272] In some examples, such as Figures 31 to 33 As shown, the display panel includes multiple sub-pixels, each of which includes a pixel circuit and a light-emitting element 300 electrically connected to the pixel circuit. The multiple sub-pixels are divided into multiple pixel units 3001, each of which includes a first-color sub-pixel 301, a second-color sub-pixel 302, and a third-color sub-pixel 303. The first-color sub-pixels 301 and the second-color sub-pixels 302 are arranged along a first direction, while the first-color sub-pixels 301 and the third-color sub-pixels 303 are arranged along a second direction. For example, the multiple sub-pixels in the same pixel unit can be arranged in a real pixel arrangement, without borrowing sub-pixels. Figure 33 The pixel arrangement shown schematically illustrates the arrangement of light-emitting areas 3000 of sub-pixels of different colors.

[0273] For example, Figure 33 As shown, each pixel unit 3001 may be rectangular in shape. For example, a plurality of pixel units may be arranged in an array along a first direction and a second direction.

[0274] For example, Figure 31 As shown, along a direction perpendicular to the substrate, the first electrode 310 in the light-emitting element 300 of the first color sub-pixel 301 overlaps with the first capacitor electrode C11, the second capacitor electrode C12, the third capacitor electrode C23, and the fourth capacitor electrode C24 of the first color sub-pixel 301. For example, along a direction perpendicular to the substrate, the first electrode 310 in the light-emitting element 300 of the first color sub-pixel 301 overlaps with the first capacitor electrode C11 and the second capacitor electrode C12 of the second color sub-pixel 302. For example, along a direction perpendicular to the substrate, the first electrode 310 in the light-emitting element 300 of the first color sub-pixel 301 overlaps with the channel region of the first emission control transistor T4 of the first color sub-pixel 301.

[0275] For example, Figure 31 As shown, along a direction perpendicular to the substrate, the first electrode 310 in the light-emitting element 300 of the second color sub-pixel 302 does not overlap with the first capacitor electrode C11, the second capacitor electrode C12, the third capacitor electrode C23, and the fourth capacitor electrode C24 in the pixel circuit electrically connected thereto. For example, along a direction perpendicular to the substrate, the first electrode 310 in the light-emitting element 300 of the second color sub-pixel 302 overlaps with the channel region of the second emission control transistor T2 in the first color sub-pixel 301 and the channel region of the second emission control transistor T2 in the second color sub-pixel 302.

[0276] For example, Figure 31 As shown, along a direction perpendicular to the substrate, the first electrode 310 of the light-emitting element 300 of the third color sub-pixel 303 overlaps with the first capacitor electrode C11 and the second capacitor electrode C12 of the third color sub-pixel 303, and does not overlap with the fourth capacitor electrode C24 of the third color sub-pixel 303. For example, along a direction perpendicular to the substrate, the first electrode 310 of the light-emitting element 300 of the third color sub-pixel 303 overlaps with the third capacitor electrode C23 and the fourth capacitor electrode C24 of the second color sub-pixel 302.

[0277] In some examples, such as Figure 33As shown, the display panel includes a plurality of sub-pixels, and the plurality of sub-pixels are divided into a plurality of pixel units 3001. The plurality of pixel units 3001 include a plurality of pixel unit rows 3010 arranged along a first direction, and the number of pixel units 3001 in each pixel unit row 3010 is greater than or equal to 2560; the plurality of pixel units 3001 include a plurality of pixel unit columns 3020 arranged along a second direction, and the number of pixel units 3001 in each pixel unit column 3020 is greater than or equal to 1440.

[0278] In some examples, such as Figure 31 and 32 As shown, the first electrode 310 of the light-emitting element 300 includes a main electrode 311 and a connecting electrode 312. The main electrode 311 overlaps the light-emitting area 3000 of the sub-pixel. An insulating layer, such as a planar layer 04, is provided between the connecting electrode 312 and the second electrode of the first emission control transistor T4 in the pixel circuit. The connecting electrode 312 is electrically connected to the second electrode of the first emission control transistor T4 via an anode via 2330 in the insulating layer 04. For example, vias 2320 are provided in the insulating layers 02 and 03. The connecting electrode 312 of the first electrode 310 of the light-emitting element 300 is electrically connected to the second electrode of the first emission control transistor T4 via the anode via 2330 and the via 2320. For example, in a direction parallel to the base substrate 01, the size of the anode via 2330 is larger than the size of the via 2320. For example, the anode via 2330 and the via 2320 form a nested hole.

[0279] For example, Figure 31 As shown, the main electrode 311 and the light-emitting area 3000 of at least one sub-pixel are both rectangular in shape. For example, the main electrode 311 and the light-emitting area 3000 of each color sub-pixel are both rectangular in shape. For example, the area of ​​the light-emitting area 3000 of the third color sub-pixel 303 is larger than the area of ​​the light-emitting area 3000 of the first color sub-pixel 301, and the area of ​​the light-emitting area 3000 of the third color sub-pixel 303 is larger than the area of ​​the light-emitting area 3000 of the second color sub-pixel 302.

[0280] For example, Figure 31 As shown, in the same pixel unit, the connecting electrode of the first color sub-pixel 301 is located between its main electrode 311 and the main electrode 311 of the second color sub-pixel 302, the connecting electrode 312 of the second color sub-pixel 302 is located between its main electrode 311 and the main electrode 311 of the first color sub-pixel 301, and the connecting electrode 312 of the third color sub-pixel 303 is located on the side of its main electrode 311 away from the second color sub-pixel 302.

[0281] For example, Figure 31As shown, the connection electrode 312 of the first color sub-pixel 301 is rectangular in shape, the connection electrode 312 of the third color sub-pixel 303 is rectangular in shape, and the connection electrode 312 of the second color sub-pixel 302 is bent in shape.

[0282] In some examples, such as Figure 31 and 32 As shown, in the same sub-pixel, the orthographic projection of the anode via 2330 on the base substrate 01 is the first orthographic projection, and the orthographic projection of the light-emitting area 3000 on the base substrate 01 is the second orthographic projection. The distance between the edges of the first and second orthographic projections that are close to each other is the first sub-distance D1, and the first sub-distance D1 is 1-3 microns. For example, the anode via 2330 is very close to the light-emitting area 3000 of the sub-pixel where its corresponding connection electrode 312 is located.

[0283] By setting the distance between the anode via hole and the light emitting area 3000 to be very small, such as only close to the light emitting area 3000, the isolation structure 500 ( Figures 34 to 38 The location of the pin (as shown) provides design space or facilitates the transmission of the VSS signal.

[0284] For example, Figure 31 As shown, the first sub-distances between the light-emitting areas 3000 of sub-pixels of different colors and their corresponding anode via holes may be the same or different.

[0285] For example, Figure 31 As shown, the first sub-distance between the light-emitting area 3000 of the first color sub-pixel 301 and its corresponding anode via 2330 can be greater than the first sub-distance between the light-emitting area 3000 of the third color sub-pixel 303 and its corresponding anode via 2330. For example, the first sub-distance between the light-emitting area 3000 of the second color sub-pixel 302 and its corresponding anode via 2330 can be greater than the first sub-distance between the light-emitting area 3000 of the third color sub-pixel 303 and its corresponding anode via 2330.

[0286] For example, Figure 31 As shown, the first sub-distance D1 can be 1.5 to 2 microns. For example, the first sub-distance D1 can be 1.7 to 2.5 microns. The embodiment of the present invention does not enumerate the specific numerical range of the first sub-distance one by one, and the first sub-distance can be any value between 1 and 3 microns.

[0287] Figure 34 A schematic diagram of a partial interface structure of a display panel provided according to an example of an embodiment of the present utility model. Figure 34 The film layer between the base substrate 01 and the first electrode 310 of the light emitting element is omitted.

[0288] In some examples, such as Figure 34As shown, the display panel further includes an isolation structure 500 located on the base substrate 01 . The isolation structure 500 is configured to isolate the light-emitting functional layer 330 and the second electrode 320 of the sub-pixel.

[0289] For example, Figure 34 As shown, isolation structure 500 can be located in the display area, such as between the effective light-emitting areas of adjacent sub-pixels. For example, adjacent sub-pixels may include sub-pixels that emit light of different colors, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this is not limiting, and isolation structure 500 may also include a portion located in a peripheral area surrounding the display area.

[0290] In some examples, such as Figure 34 As shown, a plurality of isolation openings 501 are provided in the isolation structure 500, and a portion of the film layer of the light-emitting functional layer 330 and the second electrode 320 configured to form a sub-pixel, located outside a specific isolation opening 501 among the plurality of isolation openings 501, is removed by a photolithography process, and the specific isolation opening 501 is an isolation opening 501 corresponding to the sub-pixel on which the light-emitting functional layer 330 and the second electrode 320 are to be formed.

[0291] For example, Figure 34 As shown, when forming the light-emitting functional layer 330 and the second electrode 320 of a sub-pixel, such as the light-emitting functional layer 330 and the second electrode 320 of the first color sub-pixel 301, the light-emitting functional layer 330 and the second electrode 320 of the second color sub-pixel 302, or the light-emitting functional layer 330 and the second electrode 320 of the third color sub-pixel 303, the light-emitting functional layer 330 and the second electrode 320 of the light-emitting element 300 can be formed in the display panel by a maskless photolithography process, so that each light-emitting element 300 is at least partially located within an isolation opening 501. The isolation opening 501 for forming the light-emitting functional layer 330 and the second electrode 320 is a specific isolation opening 501, for example, each isolation opening 501 can be the specific isolation opening 501.

[0292] On the one hand, when forming light-emitting elements through a maskless photolithography process, it is not dependent on the precision limitations of physical masks, which facilitates the formation of more precise light-emitting devices within the display panel, thereby improving the precision of the display panel. In the display panel provided by the present invention, multiple second power signal lines VSS are provided to achieve electrical connection with the second electrode separated by the isolation opening, so the second electrode does not need to be designed as a whole layer.

[0293] For example, Figure 34As shown, the isolation structure 500 can be an integrated structure or include multiple film layers. For example, the structure includes a first isolation portion, a second isolation portion, and a third isolation portion stacked in sequence. The third isolation portion is located on a side of the second isolation portion away from the substrate, and the edge of the third isolation portion protrudes relative to the edge of the second isolation portion. When forming light-emitting elements in the display panel using a maskless photolithography process, the light-emitting functional layers of two adjacent light-emitting elements can be disconnected at the edge of the third isolation portion, thereby reducing crosstalk between two adjacent sub-pixels and improving the display effect of the display panel.

[0294] For example, Figure 34 As shown, at least a portion of the isolation structure 500 may be a conductive structure to electrically connect the second electrodes 320 of adjacent sub-pixels. However, the present invention is not limited thereto. The isolation structure 500 may also be made of an inorganic non-metallic material, such as silicon oxide, silicon nitride, or an organic material, such as a negative photoresist.

[0295] For example, Figure 34 As shown, the isolation structure 500 is located on the side of the pixel defining portion 410 away from the substrate 01. For example, the isolation structure 500 is located on the side of the first electrode 310 away from the substrate 01. For example, the surface of the pixel defining portion 410 on which the isolation structure 500 is located can be a flat surface, and the isolation structure 500 can be disposed on the flat surface, but this is not limited to this. The pixel defining portion 410 can also be provided with a groove, and the isolation structure 500 can be disposed within the groove. However, in other examples, the isolation structure 500 can be located between the first electrode and the substrate, such as between the pixel defining portion 410 and the substrate, with the edges of the isolation structure 500 exposed by the openings in the pixel defining pattern 400 to separate the light-emitting functional layer 330 from the second electrode. In other examples, the cross-sectional shape of the isolation structure 500 can be T-shaped, inverted trapezoidal, or other shapes. In other examples, the isolation structure 500 can be located between the pixel defining portion 410 and the substrate, and disposed on the same layer as the first electrode of the light-emitting element 300, with the openings in the pixel defining pattern 400 exposing the edges of the isolation structure 500.

[0296] In some examples, such as Figure 34 As shown, the dimension of the isolation structure 500 in the direction perpendicular to the substrate is 1.5 to 3 microns. For example, the dimension of the isolation structure 500 in the direction perpendicular to the substrate can be the height of the isolation structure 500, and the height of the isolation structure 500 can be 2 to 2.5 microns. For example, the height of the isolation structure 500 can be 1.8 to 2.7 microns. The embodiments of the present invention do not enumerate the specific numerical range of the height of the isolation structure 500 one by one, and the height of the isolation structure 500 can be any value between 1.5 and 3 microns.

[0297] In some examples, such as Figure 34 As shown, the orthographic projection of the isolation structure 500 on the substrate is the third orthographic projection, the minimum distance between the third orthographic projection and the second orthographic projection is the second sub-distance D2, and the second sub-distance D2 is 2-5 microns.

[0298] By setting the height of the isolation structure and the distance between the isolation structure and the light-emitting area, it is helpful to adjust the angle of the light emitted by the sub-pixel to alleviate the color deviation problem.

[0299] For example, Figure 34 As shown, the second sub-distance D2 is 3 to 4 microns. For example, the second sub-distance D2 is 2.5 to 4.5 microns. The embodiment of the present invention does not enumerate the specific numerical range of the second sub-distance one by one, and the second sub-distance can be any value between 2 and 5 microns.

[0300] In some examples, such as Figure 31 、 Figure 32 as well as Figure 34 As shown, the first sub-distance D1 is smaller than the second sub-distance D2.

[0301] By setting the relationship between the first sub-distance and the second sub-distance, interference between the anode via and the isolation structure can be avoided.

[0302] For example, the display panel further includes an encapsulation layer (not shown) located on a side of the isolation structure 500 away from the base substrate.

[0303] Figure 35 The diagram is a planar diagram of a partial isolation structure in a display panel provided according to an example of an embodiment of the present utility model.

[0304] In some examples, such as Figure 35 As shown, the isolation structure 500 includes a ring-shaped isolation structure 500 surrounding the light-emitting region 3000 of at least one sub-pixel. For example, the light-emitting functional layers of adjacent sub-pixels are spaced apart from each other. For example, the second electrodes of adjacent sub-pixels are spaced apart from each other. For example, the ring-shaped isolation structure 500 can have a closed ring shape.

[0305] In some examples, such as Figure 35 As shown, there are multiple annular isolation structures 500, each of which surrounds the light-emitting region 3000 of a sub-pixel. Spaces are provided between the isolation structures 500 surrounding the light-emitting regions 3000 of sub-pixels of different colors. For example, the isolation structures 500 include an annular isolation structure 500 surrounding the light-emitting region 3000 of the first-color sub-pixel 301, an annular isolation structure 500 surrounding the light-emitting region 3000 of the second-color sub-pixel 302, and an annular isolation structure 500 surrounding the light-emitting region 3000 of the third-color sub-pixel 303.

[0306] Figures 36 to 38 Schematic diagrams of the planar shape of the isolation structure in the display panel provided according to different examples of the embodiment of the present utility model.

[0307] For example, Figure 36 The isolation structure 500 is shown with Figure 35 The difference between the isolation structures 500 shown is that there is no space between the annular isolation structures 500 surrounding the light emitting regions 3000 of adjacent sub-pixels. For example, the adjacent sub-pixels may include sub-pixels of the same color or sub-pixels of different colors.

[0308] For example, Figure 37 The isolation structure 500 is shown with Figure 35 The difference between the illustrated isolation structures 500 is that the annular isolation structures 500 surrounding the light-emitting regions 3000 of adjacent, different-color sub-pixels are spaced apart, while the annular structures surrounding the light-emitting regions 3000 of adjacent, same-color sub-pixels are not spaced apart. For example, the adjacent, same-color sub-pixels may be third-color sub-pixels 303, such as blue sub-pixels. However, the adjacent, same-color sub-pixels may be at least one of the first-color sub-pixel 301 and the second-color sub-pixel 302.

[0309] For example, Figure 38 The isolation structure 500 is shown with Figure 35 The difference between the isolation structures 500 shown is that there are gaps between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent sub-pixels of different colors, and the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent sub-pixels of the same color are an integrated structure.

[0310] In some examples, such as Figure 38 As shown, at least one annular isolation structure 500 surrounds the light-emitting regions 3000 of multiple sub-pixels of the same color. The light-emitting functional layers of the multiple sub-pixels of the same color may be integrated. The second electrodes of the sub-pixels of the same color may also be integrated.

[0311] For example, Figure 38 As shown, the adjacent and same color sub-pixels may be the third color sub-pixel 303 , such as a blue sub-pixel. However, the adjacent and same color sub-pixels may be at least one of the first color sub-pixel 301 and the second color sub-pixel 302 .

[0312] For example, Figure 38It is schematically shown that the same annular isolation structure 500 can surround the light-emitting areas 3000 of two sub-pixels of the same color, but is not limited to this. The annular isolation structure 500 can surround the light-emitting areas 3000 of three or more sub-pixels of the same color, such as the annular isolation structure 500 can surround the light-emitting areas 3000 of a row or a column of sub-pixels of the same color.

[0313] The embodiments of the present invention are not limited to this. For example, there is no gap between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent first color sub-pixels 301 and second color sub-pixels 302, there is a gap between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent first color sub-pixels 301 and third color sub-pixels 303, and there is a gap between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent second color sub-pixels 302 and third color sub-pixels 303; for example, there is a gap between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent first color sub-pixels 301 and second color sub-pixels 302, there is no gap between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent first color sub-pixels 301 and third color sub-pixels 303, and there is no gap between the annular isolation structures 500 surrounding the light-emitting areas 3000 of adjacent second color sub-pixels 302 and third color sub-pixels 303.

[0314] Figure 39 Schematic diagram of the stacking relationship between the isolation structure and the pixel circuit. Figure 39 The isolation structure 500 is schematically shown as Figure 36 The isolation structure 500 is shown, but is not limited thereto. The isolation structure 500 may also be Figure 35 、 Figure 38 as well as Figure 39 An isolation structure 500 is shown in any example.

[0315] In some examples, such as Figure 39 As shown, the isolation structure 500 is located on a side of the second metal layer 220 away from the first metal layer 210 , and the reference signal line 217 is electrically connected to the fourth capacitor electrode C24 and is configured to transmit the low potential power supply voltage signal VSS to the fourth capacitor electrode C24 .

[0316] In some examples, such as Figure 39 As shown, the reference signal line 217 extends along the first direction, the second metal layer 220 includes a second power signal line VSS extending along the second direction, the second power signal line VSS is located between the pixel circuits of adjacent sub-pixels, and the reference signal line 217 is electrically connected to the second power signal line VSS to receive a low-potential power voltage signal.

[0317] Providing a transverse second power signal line for transmitting the low-potential power voltage signal VSS can help reduce the resistance of the reference signal line 217 .

[0318] For example, Figure 39 As shown, the reference signal line 217 is electrically connected to the second power signal line VSS through a via 2341 in the insulating layer therebetween. For example, the second power signal line VSS is located between the third power signal line 2182 and the reset power signal line REF1.

[0319] In some examples, such as Figure 34 and Figure 39 As shown, the second electrode of the light emitting element is electrically connected to the isolation structure 500 , and the isolation structure 500 is electrically connected to the reference signal line 217 .

[0320] In the display panel provided by the present invention, the second electrode of the light-emitting element is electrically connected to the reference signal line via the isolation structure, which is beneficial to reducing the resistance of the second electrode.

[0321] Figure 40 For the Figure 39 The schematic diagram of the local cross-section structure taken along line BB' is shown.

[0322] In some examples, such as Figure 39 and Figure 40 As shown, the isolation structure 500 is located on a side of the pixel defining portion 410 away from the base substrate 01 , and the isolation structure 500 is electrically connected to the reference signal line 217 through a via hole 411 in the pixel defining portion 410 .

[0323] For example, Figure 39 and Figure 40 As shown, the isolation structure 500 can be electrically connected to the second power signal line VSS through the via 411 in the pixel defining portion 410 and the via 041 in the planar layer 04, and the second power signal line VSS is electrically connected to the reference signal line 217 through the via 2341 in the insulating layer 03. Of course, the present invention is not limited to this embodiment. For example, the display panel may not be provided with a second power signal line. The isolation structure 500 is electrically connected to the reference signal line 217 through the vias in the pixel defining portion 410, the planar layer, and the insulating layer.

[0324] For example, Figure 40 As shown, the surface of the pixel defining portion 410 on which the isolation structure 500 is provided may be a flat surface, but is not limited thereto. A groove may also be provided on the surface of the pixel defining portion 410 away from the substrate to reduce the distance between the isolation structure 500 and the reference signal line 217 and reduce the depth of the via provided in the pixel defining portion 410, which is beneficial to improving the process yield.

[0325] Figure 41Schematic diagram of the stacking relationship among the isolation structure, auxiliary connection portion, and pixel circuit. Figure 42 For the Figure 41 The schematic diagram of the local cross-section structure taken along line CC' is shown. Figure 43 This is a diagram showing the stacking relationship between the film layer where the reference signal line is located and the auxiliary connection part.

[0326] In some examples, such as Figure 41 and Figure 42 As shown, the display panel further includes an auxiliary connection portion 600 located in at least one of the film layer where the first electrode of the light-emitting element 300 is located, the first metal layer, and the second metal layer. The isolation structure 500 is electrically connected to the reference signal line 217 via the auxiliary connection portion 600. For example, the auxiliary connection portion 600 is made of a conductive material.

[0327] Providing the auxiliary connection portion is beneficial to improving the electrical connection effect between the isolation structure and the reference signal line, thereby reducing the resistance of the second electrode and serving as a transition layer to reduce the impact of deep hole etching.

[0328] Figure 41 and Figure 43 Three auxiliary connection parts 600 in the film layer where the first electrode is located are schematically shown.

[0329] For example, Figure 41 and Figure 42 As shown, the auxiliary connection portion 600 is located in the film layer where the first electrode is located, and the reference signal line 217 is located in the first metal layer 210. The auxiliary connection portion 600 is electrically connected to the reference signal line 217 through the via 2342 in the insulating layer 03 and the planar layer 04. For example, the auxiliary connection portion 600 can be made of the same material as the first electrode so that the auxiliary connection portion 600 and the first electrode can be formed in the same patterning process.

[0330] The embodiments of the present invention are not limited to this. For example, the reference signal line can be located in the semiconductor layer, and the auxiliary connection part can be located in at least one of the film layer where the first electrode is located, the first metal layer, and the second metal layer; for example, the reference signal line can be located in the second metal layer, and the auxiliary connection part can be located in the first metal layer; for example, the auxiliary connection part can include a single film layer or multiple film layers.

[0331] For example, Figure 42 As shown, a pixel defining portion 410 is provided between the isolation structure 500 and the auxiliary connection portion 600 , and the isolation structure 500 is electrically connected to the auxiliary connection portion 600 through a via hole 412 in the pixel defining portion 410 .

[0332] In some examples, such as Figure 41 and Figure 42As shown, the isolation structure 500 includes a ring-shaped isolation structure 500 surrounding the light-emitting region 3000 of at least one sub-pixel. Along a direction perpendicular to the base substrate, the ring-shaped isolation structure 500 overlaps with the auxiliary connection portion 600 .

[0333] For example, Figure 41 As shown, in a direction perpendicular to the substrate, the same auxiliary connection portion 600 may overlap with at least one annular isolation structure 500. For example, the isolation structure 500 overlapping the auxiliary connection portion 600 may be electrically connected to the auxiliary connection portion 600 or may not be electrically connected to the auxiliary connection portion 600.

[0334] In some examples, such as Figure 41 and Figure 43 As shown, along a direction perpendicular to the substrate, the reference signal line 217 includes a first reference signal line portion 2171 overlapping with the auxiliary connection portion 600 and a second reference signal line portion 2172 not overlapping with the auxiliary connection portion 600, and the maximum width of the first reference signal line portion 2171 is greater than the maximum width of the second reference signal line portion 2172.

[0335] By setting the portion of the reference signal line that overlaps with the auxiliary connection portion to have a larger width, the electrical connection effect between the auxiliary connection portion and the reference signal line is improved.

[0336] For example, Figure 43 As shown, first reference signal line portion 2171 and second reference signal line portion 2172 are integrally configured. For example, the number of first reference signal line portions 2171 within a single reference signal line 217 is not less than the number of auxiliary connection portions 600 overlapping with the reference signal line 217. For example, the number of first reference signal line portions 2171 within a single reference signal line 217 is equal to the number of auxiliary connection portions 600 overlapping with the reference signal line 217.

[0337] For example, Figure 43 As shown, along the first direction, the width of the same first reference signal line portion 2171 can be gradual, such as first increasing and then decreasing. However, this is not limiting, and the first reference signal line portion 2171 can have a uniform width. For example, along the first direction, the width of the same second reference signal line portion 2172 can be gradual, such as first decreasing and then increasing. For example, the edge of the second reference signal line portion 2172 near the first power signal line 2181 can be configured as a curved shape, and the edge of the second reference signal line portion 2172 near the data line DATA can be configured as a straight shape. This allows the width of the reference signal line 217 at different locations to be adjusted while avoiding interference between the reference signal line 217 and other signal lines.

[0338] For example, Figure 43As shown, the auxiliary connection portion 600 overlaps the fourth capacitor electrode C24 of the second capacitor C2. For example, the first reference signal line portion 2171 is adjacent to the fourth capacitor electrode C24, or the first reference signal line portion 2171 and the fourth capacitor electrode C24 are integrally arranged.

[0339] The fourth capacitor electrode C24 of the second capacitor and the reference signal line 217 are integrated into a structure. The first reference signal line portion 2171 is arranged around the fourth capacitor electrode C24, which is beneficial to further increase the overlapping area between the reference signal line 217 and the auxiliary connection portion 600, thereby improving the electrical connection effect between the auxiliary connection portion 600 and the reference signal line 217.

[0340] In some examples, such as Figure 41 As shown, along the direction perpendicular to the substrate, the reference signal line 217 and the second power signal line VSS both overlap with the auxiliary connection portion 600, and the auxiliary connection portion 600 includes a first auxiliary connection portion 610 overlapping with the reference signal line 217 and a second auxiliary connection portion 620 overlapping with the second power signal line VSS.

[0341] For example, Figure 41 As shown, the first auxiliary connection portion 610 is electrically connected to the reference signal line 217, and the second auxiliary connection portion 620 can be electrically connected to the second power signal line VSS. For example, the first auxiliary connection portion 610 extends along a first direction, and the second auxiliary connection portion 620 extends along a second direction. For example, in a direction perpendicular to the base substrate, the first auxiliary connection portion 610 does not overlap with the first power signal line 2181 and the data line DATA. For example, in a direction perpendicular to the base substrate, the second auxiliary connection portion 620 overlaps with the first power signal line 2181, the reference signal line 217, and the data line DATA.

[0342] In some examples, such as Figure 41 As shown, the plurality of sub-pixels include sub-pixels of different colors, and the second electrodes of at least two of the sub-pixels of different colors are configured to transmit different low-potential power supply voltage signals. For example, when the second electrodes of the sub-pixels of different colors are configured to apply different low-potential power supply voltage signals, the second power signal line may not be provided.

[0343] The second electrodes of different color sub-pixels are configured to transmit different low-potential power supply voltage signals, so that the voltage difference between the high-potential power supply voltage signal ELVDD and the low-potential power supply voltage signal ELVSS in different color sub-pixels is different, such as achieving the effect of differentiated VSS resistance reduction.

[0344] For example, Figure 41As shown, different annular isolation structures 500 surrounding the light emitting regions 3000 of different sub-pixels are electrically connected to different isolation structures 500 to electrically connect different reference signal lines 217. For example, the second electrodes of different sub-pixels are electrically connected to different auxiliary connection portions 600.

[0345] By setting the isolation structure 500 to be in a ring shape, the second electrodes of different sub-pixels can be separated from each other to receive different low-potential power supply voltage signals, which is beneficial to reducing power consumption.

[0346] Of course, the shape of the isolation structure is not limited to a ring shape. The isolation structure can be provided at a key position and connected to the same low-potential power supply voltage signal.

[0347] In other examples, such as Figure 38 and Figure 41 As shown, at least two sub-pixels in the same column are sub-pixels of the same color, such as the third color sub-pixel 303. The same annular isolation structure 500 surrounding the at least two sub-pixels can be electrically connected to the same auxiliary connection portion 600. For example, the second electrodes of different sub-pixels are integrally arranged and electrically connected to the same auxiliary connection portion 600.

[0348] In other examples, orthographic projections of the second electrodes of different sub-pixels on the base substrate overlap with the same auxiliary connection portion, and the auxiliary connection portion is electrically connected to only one second electrode.

[0349] Figure 44 A diagram showing the stacking relationship between a portion of the pixel circuit and the first electrode of the light-emitting element. Figure 44 The pixel circuit shown can be Figure 21 The pixel circuit in the example shown is, but not limited to, the pixel circuit in the display panel shown in this example may also adopt the pixel circuit in other examples. Figure 44 The display panel in the example shown is Figure 31 The differences in the display panels in the examples shown include Figure 44 The display panel in the illustrated example is not provided with the isolation structure 500 .

[0350] In some examples, such as Figure 44 As shown, the first electrode 310 includes a main electrode 311 and a connecting electrode 312. The main electrode 311 overlaps with the light-emitting area 3000 of the sub-pixel, and the connecting electrode 312 is electrically connected to the second electrode of the first light-emitting control transistor T4 in the pixel circuit, such as the connecting electrode 312 is electrically connected to the first light-emitting control transistor T4 through an anode via in the insulating layer between the connecting electrode 312 and the second electrode of the first light-emitting control transistor T4; the length of the connecting electrode 312 of the first color sub-pixel 301 in the preset direction is greater than the size of the light-emitting area 3000 of the second color sub-pixel 302 in the preset direction.

[0351] When the isolation structure 500 is not provided in the display panel, the distance between the anode via hole of the sub-pixel and its light-emitting area 3000 can be set to be larger without considering the position of the isolation structure 500 .

[0352] In some examples, such as Figure 44 As shown, the above-mentioned preset direction is the first direction. For example, the length of the connecting electrode 312 of the first color sub-pixel 301 is greater than the length of the connecting electrodes 312 of the other color sub-pixels. For example, the orthographic projection of the light-emitting area 3000 of the second color sub-pixel 302 on a straight line extending along the first direction overlaps with the orthographic projection of the connecting electrode 312 of the first color sub-pixel 301 on the same straight line. For example, the connecting electrode 312 of the first color sub-pixel 301 includes a first portion extending along the first direction and a second portion extending along the second direction. The second portion and the main electrode 311 of the first color sub-pixel 301 are respectively located on either side of the main electrode 311 of the second color sub-pixel 302 in the first direction.

[0353] Figure 45 Schematic diagram of the stacking relationship of light-emitting elements of sub-pixels of different colors provided according to an embodiment of the present invention.

[0354] For example, the light-emitting elements of the sub-pixels in a display panel use Tandem technology, stacking the sub-pixel light-emitting layers in series. A full charge generation layer, such as a P-type doped charge generation layer (P-CGL) and an N-type doped charge generation layer (N-CGL), is placed between the stacked light-emitting layers. Compared to display substrates without Tandem devices, Tandem devices use N / P-CGL as a heterojunction, connecting two light-emitting layers in series. This technology achieves dual light-emitting device series connection, significantly reducing the light-emitting current of the light-emitting device at the same light-emitting intensity, extending the lifespan of organic light-emitting elements, such as organic light-emitting devices, and reducing power consumption.

[0355] The charge generation layers of adjacent sub-pixels are continuous layers, subject to lateral charge migration, which can cause monochromatic chromaticity shifts at low grayscale levels on the display substrate. This can easily lead to crosstalk between adjacent sub-pixels, resulting in color shift on the display substrate. The isolation structure described in the above embodiment can be used to isolate the charge generation layers of adjacent sub-pixels to reduce crosstalk between them.

[0356] In some examples, such as Figure 45As shown, the light-emitting functional layer 330 includes a first electron blocking layer EBL1, a first light-emitting layer EML1, a charge generation layer CGL, such as a P-type charge generation layer PCGL and an N-type charge generation layer NCGL, a second electron blocking layer EBL2 and a second light-emitting layer EML2, which are stacked in sequence. The first light-emitting layer EML1 is located between the second light-emitting layer EML2 and the first electrode 310; there is a first distance L between the surfaces of the first electrode 310 and the second electrode 320 that are close to each other, and there is a second distance L between the surface of the second light-emitting layer EML2 facing the substrate and the surface of the second electrode 320 facing the substrate. 1, a third distance L2 is present between a surface of the first light-emitting layer EML1 away from the substrate and a surface of the first electrode 310 away from the substrate, a fourth distance L3 is present between surfaces of the first light-emitting layer EML1 and the second light-emitting layer EML2 close to each other, a fifth distance L4 is present between a surface of the first light-emitting layer EML1 away from the substrate and a surface of the first electron blocking layer EBL1 close to the substrate, the charge generation layer CGL has a first thickness L5, and a sixth distance L6 is present between a surface of the second light-emitting layer EML2 away from the substrate and a surface of the second electron blocking layer EBL2 close to the substrate.

[0357] For example, Figure 45 As shown, an electron injection layer EIL, a second electron transport layer ETL2 and a second hole blocking layer HBL2 are arranged between the second electrode 320 and the second light-emitting layer EML2, a second hole transport layer HTL2 is arranged between the second electron blocking layer EBL2 and the charge generation layer, a first electron transport layer ETL1 and a first hole blocking layer HBL1 are arranged between the charge generation layer and the first light-emitting layer EML1, and a hole injection layer HIL and a first hole transport layer HTL1 are arranged between the first electron blocking layer EBL1 and the first electrode 310.

[0358] In some examples, such as Figure 45 As shown, the ratio of the distance between the first light-emitting layer EML1 and the surfaces of the first electrode 310 close to each other to the first distance L is 0.2-0.3, and the ratio of the distance between the second light-emitting layer EML2 and the surfaces of the first electrode 310 close to each other to the first distance is 0.7-0.8.

[0359] In some examples, such as Figure 45 As shown, in the first color sub-pixel 301, the third distance L2 and the fifth distance L4 satisfy 0.6≤L4 / L2≤0.9; in the second color sub-pixel 302, the third distance L2 and the fifth distance L4 satisfy 0.5≤L4 / L2≤0.8; in the third color sub-pixel 303, the third distance L2 and the fifth distance L4 satisfy 0.3≤L4 / L2≤0.7.

[0360] For example, Figure 45As shown, the first color sub-pixel 301, the second color sub-pixel 302 and the third color sub-pixel 303 are at a current density of 15 mA / cm 2 The voltage (V), current efficiency (cd / A) and device life under the following conditions were tested, and the test results are as follows.

[0361] Example 1: When L4 / L2 is 0.4 in the first color sub-pixel 301, the voltage is 100%, the current efficiency is 94%, and the device life is 99%; when L4 / L2 is 0.3 in the second color sub-pixel 302, the voltage is 100%, the current efficiency is 91%, and the device life is 99%; when L4 / L2 is 0.2 in the third color sub-pixel 303, the voltage is 100%, the current efficiency is 86%, and the device life is 97%.

[0362] Example 2: When L4 / L2 is 1.2 in the first color sub-pixel 301, the voltage is 102%, the current efficiency is 90%, and the device life is 97%; when L4 / L2 is 1 in the second color sub-pixel 302, the voltage is 101%, the current efficiency is 93%, and the device life is 97%; when L4 / L2 is 0.9 in the third color sub-pixel 303, the voltage is 102%, the current efficiency is 88%, and the device life is 96%.

[0363] Example 3: When L4 / L2 in the first color sub-pixel 301 is 0.74, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L4 / L2 in the second color sub-pixel 302 is 0.63, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L4 / L2 in the third color sub-pixel 303 is 0.5, the voltage is 100%, the current efficiency is 100%, and the device life is 100%.

[0364] It can be seen that, relative to Example 1 and Example 2, by adjusting L4 / L2 in different color sub-pixels, such as 0.6≤L4 / L2≤0.9 in the first color sub-pixel 301, 0.5≤L4 / L2≤0.8 in the second color sub-pixel 302, and 0.3≤L4 / L2≤0.7 in the third color sub-pixel 303, for example, in Example 3, L4 / L2 in the first color sub-pixel 301 is 0.74, L4 / L2 in the second color sub-pixel 302 is 0.63, and L4 / L2 in the third color sub-pixel 303 is 0.5, the first light-emitting layer EML1 can be set on the microcavity enhancement node, and the voltage, current efficiency and device life can be adjusted to the optimal level.

[0365] For example, Figure 45As shown, the light-emitting functional layer 330 further includes a hole transport layer, such as a second hole transport layer HTL2, located between the second electron blocking layer EBL2 and the charge generation layer. The second hole transport layer has a second thickness L7. For example, the light-emitting functional layer 330 further includes a first hole transport layer HTL1 located between the first light-emitting layer EML1 and the first electrode.

[0366] By setting the relationship between the thicknesses of the various film layers to adjust the microcavity structure formed between the first electrode and the second electrode, the light-emitting region is located in the microcavity enhancement region, the emitted spectrum is optimized, and the light extraction efficiency is improved.

[0367] For example, Figure 45 As shown, the first color sub-pixel 301 can be a red sub-pixel R, and the light-emitting layer and the electron blocking layer of the first color sub-pixel 301 can be expressed as REML and REBL, respectively; the second color sub-pixel 302 can be a green sub-pixel G, and the light-emitting layer and the electron blocking layer of the second color sub-pixel 302 can be expressed as GEML and GEBL, respectively; the third color sub-pixel 303 can be a blue sub-pixel B, and the light-emitting layer and the electron blocking layer of the third color sub-pixel 303 can be expressed as BEML and BEBL, respectively.

[0368] For example, Figure 45 As shown, in the first color sub-pixel 301, the third distance L2 and the fifth distance L4 satisfy 0.7≤L4 / L2≤0.8; in the second color sub-pixel 302, the third distance L2 and the fifth distance L4 satisfy 0.6≤L4 / L2≤0.7; and in the third color sub-pixel 303, the third distance L2 and the fifth distance L4 satisfy 0.4≤L4 / L2≤0.6. For example, in the first color sub-pixel 301, the third distance L2 and the fifth distance L4 satisfy 0.65≤L4 / L2≤0.75; in the second color sub-pixel 302, the third distance L2 and the fifth distance L4 satisfy 0.55≤L4 / L2≤0.65; and in the third color sub-pixel 303, the third distance L2 and the fifth distance L4 satisfy 0.5≤L4 / L2≤0.65. The embodiment of the present invention does not list the specific numerical ranges of the relationship satisfied by the third distance L2 and the fifth distance L4 in sub-pixels of different colors one by one, and the numerical value of each relationship can be any numerical value in the above relationship.

[0369] In some examples, such as Figure 45 As shown, in the first color sub-pixel 301, the sixth distance L6 and the second distance L1 satisfy 0.8≤L6 / L1≤1.2; in the second color sub-pixel 302, the sixth distance L6 and the second distance L1 satisfy 0.5≤L6 / L1≤0.9; in the third color sub-pixel 303, the sixth distance L6 and the second distance L1 satisfy 0.3≤L6 / L1≤0.6.

[0370] For example, Figure 45 As shown, the first color sub-pixel 301, the second color sub-pixel 302 and the third color sub-pixel 303 are at a current density of 15 mA / cm 2 The voltage (V), current efficiency (cd / A) and device life under the following conditions were tested, and the test results are as follows.

[0371] Example 1: When L6 / L1 is 0.6 in the first color sub-pixel 301, the voltage is 101%, the current efficiency is 96%, and the device life is 98%; when L6 / L1 is 0.4 in the second color sub-pixel 302, the voltage is 103%, the current efficiency is 90%, and the device life is 100%; when L6 / L1 is 0.2 in the third color sub-pixel 303, the voltage is 102%, the current efficiency is 86%, and the device life is 97%.

[0372] Example 2: When L6 / L1 is 1.5 in the first color sub-pixel 301, the voltage is 103%, the current efficiency is 95%, and the device life is 97%; when L6 / L1 is 1 in the second color sub-pixel 302, the voltage is 100%, the current efficiency is 90%, and the device life is 101%; when L6 / L1 is 0.8 in the third color sub-pixel 303, the voltage is 101%, the current efficiency is 82%, and the device life is 96%.

[0373] Example 3: When L6 / L1 is 1 in the first color sub-pixel 301, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L6 / L1 is 0.7 in the second color sub-pixel 302, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L6 / L1 is 0.45 in the third color sub-pixel 303, the voltage is 100%, the current efficiency is 100%, and the device life is 100%.

[0374] It can be seen that, relative to Example 1 and Example 2, by adjusting L6 / L1 in different color sub-pixels, such as 0.8≤L6 / L1≤1.2 in the first color sub-pixel 301, 0.5≤L6 / L1≤0.9 in the second color sub-pixel 302, and 0.3≤L6 / L1≤0.6 in the third color sub-pixel 303, for example, in Example 3, L6 / L1 in the first color sub-pixel 301 is 1, L6 / L1 in the second color sub-pixel 302 is 0.7, and L6 / L1 in the third color sub-pixel 303 is 0.45, the voltage, current efficiency and device life can be adjusted to the optimal level.

[0375] For example, Figure 45 As shown, the thickness of the first light emitting layer EML1 may be equal to the thickness of the second light emitting layer EML2.

[0376] By adjusting the optical microcavity, the light-emitting effect of the device is optimized, so that the light-emitting layers of the blue sub-pixel, the red sub-pixel, and the green sub-pixel are all located at the nodes enhanced by the microcavity, thereby improving the light-emitting efficiency of the device.

[0377] For example, in the first color sub-pixel 301, the sixth distance L6 and the second distance L1 satisfy 0.9≤L6 / L1≤1.1; in the second color sub-pixel 302, the sixth distance L6 and the second distance L1 satisfy 0.6≤L6 / L1≤0.8; and in the third color sub-pixel 303, the sixth distance L6 and the second distance L1 satisfy 0.4≤L6 / L1≤0.5. For example, in the first color sub-pixel 301, the sixth distance L6 and the second distance L1 satisfy 0.85≤L6 / L1≤1; in the second color sub-pixel 302, the sixth distance L6 and the second distance L1 satisfy 0.7≤L6 / L1≤0.8; and in the third color sub-pixel 303, the sixth distance L6 and the second distance L1 satisfy 0.45≤L6 / L1≤0.55. The present embodiment does not enumerate the specific numerical ranges of the relationship between the sixth distance L6 and the second distance L1 in different color sub-pixels one by one; the numerical values ​​of each relationship can be any numerical value within the above relationship.

[0378] In some examples, such as Figure 45 As shown, in the first color sub-pixel 301, the first thickness L5 and the first distance L satisfy 0.07≤L5 / L≤0.12; in the second color sub-pixel 302, the first thickness L5 and the first distance L satisfy 0.09≤L5 / L≤0.15; in the third color sub-pixel 303, the first thickness L5 and the first distance L satisfy 0.12≤L5 / L≤0.18.

[0379] For example, Figure 45 As shown, the first color sub-pixel 301, the second color sub-pixel 302 and the third color sub-pixel 303 are at a current density of 15 mA / cm 2 The voltage (V), current efficiency (cd / A) and device life under the following conditions were tested, and the test results are as follows.

[0380] Example 1: When L5 / L is 0.05 in the first color sub-pixel 301, the voltage is 101%, the current efficiency is 89%, and the device life is 93%; when L5 / L is 0.05 in the second color sub-pixel 302, the voltage is 101%, the current efficiency is 90%, and the device life is 98%; when L5 / L is 0.1 in the third color sub-pixel 303, the voltage is 102%, the current efficiency is 96%, and the device life is 98%.

[0381] Example 2: When L5 / L is 0.2 in the first color sub-pixel 301, the voltage is 92%, the current efficiency is 85%, and the device life is 97%; when L5 / L is 0.2 in the second color sub-pixel 302, the voltage is 94%, the current efficiency is 89%, and the device life is 96%; when L5 / L is 0.3 in the third color sub-pixel 303, the voltage is 92%, the current efficiency is 91%, and the device life is 95%.

[0382] Example 3: When L5 / L is 0.1 in the first color sub-pixel 301, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L5 / L is 0.15 in the second color sub-pixel 302, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L5 / L is 0.15 in the third color sub-pixel 303, the voltage is 100%, the current efficiency is 100%, and the device life is 100%.

[0383] It can be seen that, relative to Example 1 and Example 2, by adjusting L5 / L in different color sub-pixels, such as 0.07≤L5 / L≤0.12 in the first color sub-pixel 301, 0.09≤L5 / L≤0.15 in the second color sub-pixel 302, and 0.12≤L5 / L≤0.18 in the third color sub-pixel 303, for example, in Example 3, L5 / L in the first color sub-pixel 301 is 0.1, L5 / L in the second color sub-pixel 302 is 0.2, and L5 / L in the third color sub-pixel 303 is 0.3, the voltage, current efficiency, and device life can all be adjusted to the optimal level.

[0384] By setting the thickness of different film layers in sub-pixels of different colors, such as setting the thickness of the charge generation layer separated by the isolation structure 500 , it is beneficial to optimize the optical and electrical characteristics of the light-emitting element 300 .

[0385] For example, Figure 45 As shown, in the first color sub-pixel 301, the first thickness L5 and the first distance L satisfy 0.08≤L5 / L≤0.1; in the second color sub-pixel 302, the first thickness L5 and the first distance L satisfy 0.1≤L5 / L≤0.12; in the third color sub-pixel 303, the first thickness L5 and the first distance L satisfy 0.13≤L5 / L≤0.17. For example, Figure 45As shown, in the first color sub-pixel 301, the first thickness L5 and the first distance L satisfy 0.09≤L5 / L≤0.11; in the second color sub-pixel 302, the first thickness L5 and the first distance L satisfy 0.11≤L5 / L≤0.14; and in the third color sub-pixel 303, the first thickness L5 and the first distance L satisfy 0.15≤L5 / L≤0.16. The present embodiment does not enumerate the specific numerical ranges of the relationship between the first thickness L5 and the first distance L in different color sub-pixels one by one; the numerical values ​​of each relationship can be any of the above-mentioned relationships.

[0386] In some examples, such as Figure 45 As shown, in the first color sub-pixel 301, the second thickness L7 and the fourth distance L3 satisfy 0.1≤L7 / L3≤0.6; in the second color sub-pixel 302, the second thickness L7 and the fourth distance L3 satisfy 0.2≤L7 / L3≤0.7; in the third color sub-pixel 303, the second thickness L7 and the fourth distance L3 satisfy 0.25≤L7 / L3≤0.8.

[0387] For example, Figure 45 As shown, the first color sub-pixel 301, the second color sub-pixel 302 and the third color sub-pixel 303 are at a current density of 15 mA / cm 2 The voltage (V), current efficiency (cd / A) and device life under the following conditions were tested, and the test results are as follows.

[0388] Example 1: When L7 / L3 in the first color sub-pixel 301 is 0.05, the voltage is 102%, the current efficiency is 93%, and the device life is 100%; when L7 / L3 in the second color sub-pixel 302 is 0.15, the voltage is 103%, the current efficiency is 90%, and the device life is 97%; when L7 / L3 in the third color sub-pixel 303 is 0.15, the voltage is 102%, the current efficiency is 89%, and the device life is 98%.

[0389] Example 2: When L7 / L3 is 0.8 in the first color sub-pixel 301, the voltage is 102%, the current efficiency is 95%, and the device life is 101%; when L7 / L3 is 0.8 in the second color sub-pixel 302, the voltage is 102%, the current efficiency is 94%, and the device life is 101%; when L7 / L3 is 1 in the third color sub-pixel 303, the voltage is 103%, the current efficiency is 91%, and the device life is 101%.

[0390] Example 3: When L7 / L3 in the first color sub-pixel 301 is 0.35, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L7 / L3 in the second color sub-pixel 302 is 0.4, the voltage is 100%, the current efficiency is 100%, and the device life is 100%; when L7 / L3 in the third color sub-pixel 303 is 0.57, the voltage is 100%, the current efficiency is 100%, and the device life is 100%.

[0391] It can be seen that, relative to Example 1 and Example 2, by adjusting L7 / L3 in different color sub-pixels, such as 0.1≤L7 / L3≤0.6 in the first color sub-pixel 301, 0.2≤L7 / L3≤0.7 in the second color sub-pixel 302, and 0.25≤L7 / L3≤0.8 in the third color sub-pixel 303, for example, in Example 3, L7 / L3 in the first color sub-pixel 301 is 0.35, L7 / L3 in the second color sub-pixel 302 is 0.4, and L7 / L3 in the third color sub-pixel 303 is 0.57, the voltage, current efficiency and device life can be adjusted to the optimal level.

[0392] By adjusting the thickness of the second hole transport layer, the position of the second light-emitting layer EML2 can be adjusted. By setting the thickness of different layers in different color sub-pixels, it is beneficial to optimize the superposition effect of the two light-emitting layers included in each sub-pixel.

[0393] For example, Figure 45 As shown, in the first color sub-pixel 301, the second thickness L7 and the fourth distance L3 satisfy 0.2≤L7 / L3≤0.5; in the second color sub-pixel 302, the second thickness L7 and the fourth distance L3 satisfy 0.4≤L7 / L3≤0.6; in the third color sub-pixel 303, the second thickness L7 and the fourth distance L3 satisfy 0.3≤L7 / L3≤0.7. For example, Figure 45 As shown, in the first color sub-pixel 301, the second thickness L7 and the fourth distance L3 satisfy 0.3≤L7 / L3≤0.4; in the second color sub-pixel 302, the second thickness L7 and the fourth distance L3 satisfy 0.3≤L7 / L3≤0.5; and in the third color sub-pixel 303, the second thickness L7 and the fourth distance L3 satisfy 0.4≤L7 / L3≤0.6. The present embodiment does not enumerate the specific numerical ranges of the relationship between the second thickness L7 and the fourth distance L3 in different color sub-pixels one by one; the numerical values ​​of each relationship can be any of the above-mentioned relationships.

[0394] In some examples, such as Figure 45 As shown, the light-emitting functional layer 330 further includes an electron injection layer EIL located between the second light-emitting layer EML2 and the second electrode. The thickness of the electron injection layer EIL is 1-10 angstroms or 11-19 angstroms.

[0395] The thickness of the electron injection layer EIL can be relatively thin, such as 1 to 10 angstroms, which is beneficial to improving efficiency; the thickness of the electron injection layer EIL can also be relatively thick, which is beneficial to reducing voltage to match different device requirements and be applied to different end products.

[0396] For example, Figure 45 As shown, the material of the electron injection layer (EIL) may include ytterbium (Yb). For example, the thickness of the electron injection layer (EIL) may be 3 to 7 angstroms. For example, the thickness of the electron injection layer (EIL) may be 3 to 5 angstroms. For example, the thickness of the electron injection layer (EIL) may be 13 to 17 angstroms. For example, the thickness of the electron injection layer (EIL) may be 2 to 6 angstroms. For example, the thickness of the electron injection layer (EIL) may be 15 to 18 angstroms. The present embodiment does not enumerate specific thickness ranges for the electron injection layer (EIL). The thickness of the electron injection layer (EIL) may be any value within the aforementioned range of 1 to 10 angstroms or 11 to 19 angstroms.

[0397] For example, Figure 45 As shown, the first electrode can be an anode, and the second electrode can be a cathode. To ensure that the light-emitting device can emit light effectively, the anode can be made of a material with a high work function, so that the holes in the anode can effectively migrate to the light-emitting layer under the drive of the electric field, thereby recombining with the electrons in the cathode to emit light. The material of the anode can be a transparent conductive metal oxide material, for example, the material of the anode can be indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the anode can be a composite electrode containing multiple materials, for example, the material of the anode can be ITO / Ag / ITO, Ag / IZO, CNT / ITO, CNT / IZO, GO / ITO, or GO / IZO, where Ag is silver, CNT is carbon nanotube, and GO is graphene oxide.

[0398] For example, the cathode can be made of a material with a low work function, which makes it easier for electrons from the cathode to be injected into the target film layer (such as the electron injection layer). This allows the electrons in the cathode to effectively migrate to the light-emitting layer under the drive of the electric field, where they recombine with holes in the anode to emit light. Furthermore, the cathode must have both good light transmittance and good electrical conductivity. The material of the cathode may be a metal material, a metal oxide or a metal alloy, such as aluminum (Al), silver (Ag), gold (Au), magnesium (Mg), calcium (Ca), ytterbium (Yb), indium (In), lithium (Li), potassium (K), sodium (Na), tin (Sn), titanium (Ti), lead (Pb), samarium (Sm), yttrium (Y), indium tin oxide (ITO), magnesium silver alloy (Mg:Ag), ytterbium gold alloy (Yb:Au), ytterbium silver alloy (Yb:Ag), lithium aluminum alloy (Li:Al) or lithium calcium magnesium alloy (Li:Ca:Al); alternatively, the material of the cathode may be a laminated material, such as magnesium / aluminum (Mg / Al), magnesium / silver (Mg / Ag), aluminum / silver (Al / Ag), aluminum / gold (Al / Au), ytterbium / gold (Yb / Au), ytterbium / silver (Yb / Ag), calcium / magnesium (Ca / Mg), calcium / silver (Ca / Ag), barium / silver (Ba / Ag), etc.

[0399] For example, the material of the charge generation layer can be an electronic material, such as an electronic material containing phenanthroline or a phosphine group. For example, the charge generation layer contains a dopant, and the dopant can be a combination of any one or more of an alkali metal, an alkaline earth metal, an alkali metal oxide, and an alkaline earth metal oxide. Among them, the alkali metal is, for example, lithium (Li), sodium (Na), potassium (K), or cesium (Cs), and the alkaline earth metal is, for example, magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra). The material of the charge generation layer can also include ytterbium (Yb).

[0400] For example, the N-type charge generation layer NCGL may include a material having a structure as shown in the following formula.

[0401] .

[0402] A represents an alkyl group or an aryl group, B represents a phenylene group or a naphthylene group, and p is a non-negative integer.

[0403] For example, the P-type charge generation layer NCGL may include a material having a structure as shown in the following formula.

[0404] .

[0405] X1 and X2 are each independently one of C, N, and Si; Y1 and Y2 are each independently one of O, N, and S; Ar1-Ar4 are substituted or unsubstituted halogen, substituted or unsubstituted cyano, substituted or unsubstituted phenyl, substituted or unsubstituted biphenyl, substituted or unsubstituted terphenyl, substituted or unsubstituted fluorene, substituted or unsubstituted adamantane, or substituted or unsubstituted heteroaryl. R1 and R2 represent deuterium, a halogen group, a cyano group, a substituted or unsubstituted heteroaryl group having 3 to 20 carbon atoms, a substituted or unsubstituted aryl group having 6 to 20 carbon atoms, a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, a substituted or unsubstituted heterocycloalkyl group having 2 to 10 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 10 carbon atoms, a substituted or unsubstituted alkylthio group having 1 to 10 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 carbon atoms, an arylthio group having 6 to 18 carbon atoms, a phosphino group having 6 to 24 carbon atoms, or a substituted or unsubstituted alkylsulfonyl group having 6 to 18 carbon atoms. a and b are each independently an integer from 1 to 5.

[0406] For example, the P-type charge generation layer NCGL may also include a material having a structure as shown in the following formula.

[0407] .

[0408] A1-A6 are substituted or unsubstituted halogen, substituted or unsubstituted cyano, substituted or unsubstituted aryl, or substituted or unsubstituted heteroaryl, and are substituted with electron-deficient groups, and are electron-withdrawing groups, and all contain groups such as cyano. When the substituent is an aryl group, the group may be substituted with an electron-withdrawing group. A can be a 3-membered ring, a 4-membered ring, a 5-membered ring, or a 6-membered ring.

[0409] For example, the hole transport layer may include a material having a structure as shown in the following formula.

[0410] .

[0411] For example, the hole blocking layer may include a material having a structure as shown in the following formula.

[0412] .

[0413] For example, the electron transport layer may include a material having a structure as shown in the following formula.

[0414] .

[0415] For example, the electron blocking layer in the first color sub-pixel 301 includes a material having a structure as shown in the following formula.

[0416] .

[0417] For example, the electron blocking layer in the second color sub-pixel 302 includes a material having a structure as shown in the following formula.

[0418] .

[0419] For example, the electron blocking layer in the third color sub-pixel 303 includes a material having a structure as shown in the following formula.

[0420] .

[0421] For example, the N-type host dopant material of the light-emitting layer of the first color sub-pixel 301 includes a material having a structure as shown in the following formula.

[0422] .

[0423] For example, the P-type host dopant material of the light-emitting layer of the first color sub-pixel 301 includes a material having a structure as shown in the following formula.

[0424] .

[0425] For example, the P-type host dopant material of the light-emitting layer of the second color sub-pixel 302 includes a material having a structure as shown in the following formula.

[0426] .

[0427] For example, the N-type host dopant material of the light-emitting layer of the second color sub-pixel 302 includes a material having a structure as shown in the following formula.

[0428] .

[0429] For example, the host material of the light-emitting layer of the third color sub-pixel 303 includes a material having a structure as shown in the following formula.

[0430] .

[0431] For example, the above R1-R17 are the same as or different from each other, and are each independently hydrogen, deuterium, a halogen group, a nitrile group, a nitro group, a hydroxyl group, a carbonyl group, an ester group, an imide group, an amino group, a substituted or unsubstituted silyl group, a substituted or unsubstituted boron group, a substituted or unsubstituted alkyl group, a substituted or unsubstituted cycloalkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryloxy group, a substituted or unsubstituted alkylthio group, a substituted or unsubstituted arylthio group, a substituted or unsubstituted alkylsulfonyl group, a substituted or unsubstituted arylsulfonyl group, a substituted or unsubstituted alkenyl group, a substituted or unsubstituted aralkyl group, a substituted or unsubstituted aralkenyl group, a substituted or unsubstituted alkylaryl group, a substituted or unsubstituted alkylamino group, a substituted or unsubstituted aralkylamino group, a substituted or unsubstituted heteroarylamino group, a substituted or unsubstituted arylamino group, a substituted or unsubstituted arylheteroarylamino group, a substituted or unsubstituted arylphosphino group, a substituted or unsubstituted phosphine oxide group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group; or a substituted or unsubstituted aryl group having 6 to 30 carbon atoms or a substituted or unsubstituted heteroaryl group having 6 to 30 carbon atoms. Ar1 to Ar15 are the same or different and are each independently hydrogen, deuterium, an aryl group having 6 to 30 carbon atoms substituted or unsubstituted by deuterium, a dibenzothienyl group substituted or unsubstituted by deuterium, or a carbazolyl group substituted or unsubstituted by an aryl group having 6 to 30 carbon atoms or by deuterium. L through L4 are independently selected from the group consisting of a single bond; a C6-C60 arylene group; a fluorenylene group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a C3-C60 aliphatic ring; and combinations thereof. A represents an alkyl or aryl group, and B represents a phenylene or naphthylene group. m, n, a, p, and q are the same or different and are non-negative integers. X, Y, and E are O, S, C, and N, respectively.

[0432] Figure 46 The following is a curve showing temperature changes over time when different areas of the display panel are at maximum brightness according to an embodiment of the present invention. Figure 47 It is a curve showing the temperature change over time when different areas of the display panel are at maximum brightness.

[0433] Figure 46 The sub-pixels in the display panel shown include Figure 45 The tandem device shown, Figure 47 The sub-pixel in the display panel shown has only one light-emitting layer, ie the sub-pixel includes a single device.

[0434] For example, Figure 46 As shown, the display panel includes Figure 1The first, second, and third regions are arranged sequentially in the X-direction. The second region is the center of the display panel, e.g., the intersection of two diagonals of the display area is the center of the display panel. The third region is the region near the driver IC. For example, the first, second, and third regions can be referred to as the upper, middle, and lower regions of the display panel, respectively. For example, along the X-direction, the sizes of the different regions can be the same or different. For example, the size of the second region can be larger than the size of the first and third regions.

[0435] In some examples, such as Figure 46 As shown, the temperature difference between the first, second, and third areas of the display panel is small. When the display panel is at maximum brightness for 10 minutes, the temperature does not exceed 40 degrees Celsius. When the display panel is at maximum brightness for 10 to 26 minutes, the temperature does not exceed 50 degrees Celsius. The method for measuring the temperature-time relationship curve is to illuminate the light sensor with a strong flashlight until it reaches the brightness of High Brightness Mode (HBM). The changes in different locations are recorded at regular intervals. For example, the maximum brightness mentioned above refers to the global maximum brightness, which can be 1000-3000 nits.

[0436] Therefore, the display panel provided by the present invention is beneficial to achieving a better temperature rise level of the entire device by matching the setting of the light-emitting devices including parameters such as the number and position of the light-emitting layers with the design of the pixel circuit, such as the setting of the reference signal lines and the number of metal layers.

[0437] For example, the display panel can be single-sided bound.

[0438] For example, Figure 47 As shown, the temperature difference between the first area, the second area and the third area of ​​the display panel is small. Figure 46 The temperature of the display panel at maximum brightness is shown to be slightly higher than Figure 47 The temperature of the display panel is shown when it is at maximum brightness, but the temperature difference at the same position of the two display panels is small.

[0439] For example, the maximum brightness of a mobile phone using a single-layer luminous layer design is 1200-3000 nits, while the maximum brightness of an in-vehicle display device using a multi-layer luminous layer design is 1000-2500 nits. For example, the voltage difference between VDD and VSS in a display panel using a single-layer luminous layer design is 7V, while the voltage difference between VDD and VSS in an in-vehicle display panel using a tandem device is 12V. For example, the white light efficiency of a display panel using a single-layer luminous layer design is 60 cd / A, while the white light efficiency of a display panel using a multi-layer luminous layer design is 82 cd / A.

[0440] Compared with a display panel in which only one light-emitting layer is provided in a sub-pixel, the light-emitting device provided in the display panel provided by the present invention has multiple light-emitting layers, and has a longer lifespan. No large voltage needs to be applied to each light-emitting layer, and the white light efficiency is higher, which is conducive to controlling the temperature of the display panel.

[0441] In some examples, the display surface of the display panel has a diagonal dimension greater than or equal to 39.6 cm. The display surface of the display panel refers to the area of ​​the display panel used to display images, including the first area, the second area, and the third area. For example, the display panel can be a medium or large-sized display panel.

[0442] Figure 48 FIG. 1 is a schematic block diagram of a display device according to another embodiment of the present invention. Figure 48 As shown, an embodiment of the present invention provides a display device including any of the above-mentioned display panels.

[0443] For example, the display panel provided in the embodiment of the present invention may be an organic light emitting diode display panel. For example, the display panel may be provided with a color filter layer or may not be provided with a color filter layer.

[0444] For example, the display device further includes a cover plate located on the light-emitting side of the display substrate.

[0445] In some examples, the display device is a vehicle-mounted display device. For example, the vehicle-mounted display device may be located in a vehicle body facing the driver.

[0446] The display device provided by the present invention optimizes the temperature control of medium and large-sized panels and improves the service life of the display panel by arranging the pixel circuit, the first electrode of the light-emitting element, the isolation structure and the light-emitting functional layer.

[0447] There are a few points to note:

[0448] (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0449] (2) Unless there is a conflict, the features of the same embodiment and different embodiments of the present invention may be combined with each other.

[0450] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of pixel circuits are located on the substrate, each pixel circuit comprising a first capacitor and a second capacitor; The first capacitor includes a first capacitor electrode and a second capacitor electrode, the second capacitor includes a third capacitor electrode and a fourth capacitor electrode, the third capacitor electrode is electrically connected to the second capacitor electrode, and the fourth capacitor electrode is configured to receive a constant voltage signal; The overlapping area between the first capacitor electrode and the second capacitor electrode is different from the overlapping area between the third capacitor electrode and the fourth capacitor electrode.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a driving transistor, which includes a first electrode, a gate electrode, and a second electrode; the first capacitor electrode is electrically connected to the gate electrode of the driving transistor, and the second capacitor electrode is electrically connected to the first electrode of the driving transistor.

3. The display panel according to claim 1, wherein: The capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

4. The display panel according to claim 1, wherein: The capacitance ratio of the second capacitor to the first capacitor is 0.5-1.

5.

5. The display panel according to claim 1, wherein: The plurality of pixel circuits include a first pixel circuit and a second pixel circuit, and the capacitance values ​​of the second capacitors in the first pixel circuit and the second pixel circuit are different.

6. The display panel according to claim 1, wherein: The plurality of pixel circuits include a first pixel circuit and a second pixel circuit, wherein the first pixel circuit and the second pixel circuit have different capacitance ratios between the second capacitor and the first capacitor.

7. The display panel according to claim 1, wherein: The multiple pixel circuits include a first pixel circuit, a second pixel circuit and a third pixel circuit, and the ratio of the capacitance value of the second capacitor in the second pixel circuit and the first pixel circuit is 0.56-1, or the ratio of the capacitance value of the second capacitor in the second pixel circuit and the third pixel circuit is 0.56-1.

8. The display panel according to claim 1, wherein: The plurality of pixel circuits include a first pixel circuit and a second pixel circuit, wherein an area of ​​a first capacitor electrode in the first pixel circuit is larger than an area of ​​the first capacitor electrode in the second pixel circuit.

9. The display panel according to claim 2, wherein: Also includes: A first metal layer is located on the base substrate; a second metal layer, located on a side of the first metal layer away from the substrate; The first metal layer includes at least part of the first capacitor electrode and the fourth capacitor electrode, the second metal layer includes at least part of the second capacitor electrode and at least part of the third capacitor electrode, the second capacitor electrode and the third capacitor electrode are integrated capacitor plates, and the capacitor plates cover the gap between the first capacitor electrode and the fourth capacitor electrode.

10. The display panel according to claim 9, wherein: The first metal layer includes alternating data lines and first power signal lines. The first capacitor electrode and the fourth capacitor electrode in the first metal layer are located between the data lines and the first power signal line, and the fourth capacitor electrode is closer to the first power signal line than the first capacitor electrode.

11. The display panel according to claim 10, wherein: The display panel further includes a plurality of light emitting elements; The pixel circuit further includes a first light-emitting control transistor and a data writing transistor, wherein a first electrode of the first light-emitting control transistor is electrically connected to a first electrode of the driving transistor, a second electrode of the first light-emitting control transistor is electrically connected to the light-emitting element, a first electrode of the data writing transistor is electrically connected to the data line, and a second electrode of the data writing transistor is electrically connected to a gate of the driving transistor; The second metal layer includes a first light emission control signal line and a first scan signal line that are spaced apart, the gate of the data writing transistor is electrically connected to the first scan signal line, and the gate of the first light emission control transistor is electrically connected to the first light emission control signal line; The first capacitor electrode, the second capacitor electrode, the third capacitor electrode, and the fourth capacitor electrode are all located between the first light emitting control signal line and the first scanning signal line.

12. The display panel according to claim 9, wherein: Also includes: a semiconductor layer, located between the first metal layer and the base substrate, the semiconductor layer at least including an active layer pattern of the driving transistor; Wherein, along a direction perpendicular to the substrate, a portion of the semiconductor layer overlapping the first metal layer includes a conductive portion electrically connected to the second metal layer, and the conductive portion faces the first metal layer to form a capacitor.

13. The display panel according to claim 1, wherein A ratio of an area of ​​at least one of the first capacitor electrode and the second capacitor electrode to an area of ​​the pixel circuit where the first capacitor electrode is located is 0.12-0.

19.

14. The display panel according to claim 10, wherein: Also includes: A reference signal line is electrically connected to the fourth capacitor electrode and is configured to transmit the constant voltage signal to the fourth capacitor electrode. At least a portion of the reference signal line extends along the first direction.

15. The display panel according to claim 14, wherein: The reference signal line is configured to transmit one of a pixel driving voltage signal, a low potential power supply voltage signal, a reference voltage signal, and an initialization voltage signal.

16. The display panel according to claim 15, wherein: The reference signal line is located between the second metal layer and the base substrate. The second metal layer includes multiple signal lines arranged along the first direction. Along the direction perpendicular to the base substrate, the reference signal line overlaps with at least three signal lines of the multiple signal lines.

17. The display panel according to claim 15, wherein: The display panel further includes a plurality of light emitting elements; The pixel circuit further includes a first light-emitting control transistor and a first reset transistor; a first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, a second electrode of the first light-emitting control transistor is electrically connected to the light-emitting element, and a first electrode of the first reset transistor is electrically connected to the second electrode of the first light-emitting control transistor; The plurality of signal lines include a first light emission control signal line, a second scan signal line, and an initialization voltage signal line sequentially arranged along the first direction; a gate of the first light emission control transistor is electrically connected to the first light emission control signal line, a gate of the first reset transistor is electrically connected to the second scan signal line, and a second electrode of the first reset transistor is electrically connected to the initialization voltage signal line; Along a direction perpendicular to the base substrate, the first light emitting control signal line, the second scanning signal line and the initialization voltage signal line all overlap with the reference signal line, and the first light emitting control signal line is located between the first capacitor electrode and the initialization voltage signal line.

18. The display panel according to claim 17, wherein: The first metal layer includes a data line, the reference signal line, and a first power signal line arranged in sequence. The reference signal line is located between at least a portion of the fourth capacitor electrode and the first power signal line.

19. The display panel according to claim 18, wherein: The reference signal line is configured to transmit the reference voltage signal.

20. The display panel according to claim 18, wherein The reference signal line and at least a portion of the fourth capacitor electrode are integrated into one structure.

21. The display panel according to claim 18, wherein The reference signal line is configured to transmit the low-potential power supply voltage signal.

22. The display panel according to claim 21, wherein: The second metal layer includes a second power signal line extending along a second direction, the second power signal line is located between adjacent pixel circuits, the reference signal line is electrically connected to the second power signal line to receive the low-potential power voltage signal, and the second direction intersects with the first direction.

23. The display panel according to claim 17, wherein: The reference signal line is configured to transmit the pixel driving voltage signal.

24. The display panel according to claim 23, wherein: The second metal layer includes a third power signal line extending along a second direction, the third power signal line is located on a side of the initialization voltage signal line away from the first light-emitting control signal line, the reference signal line is electrically connected to the third power signal line to receive the pixel driving voltage signal, and the second direction intersects with the first direction.

25. The display panel according to claim 24, wherein: The first metal layer includes a data line and a first power signal line that are spaced apart. The reference signal line is located between at least a portion of the fourth capacitor electrode and the first power signal line. The first power signal line is electrically connected to the third power signal line.

26. The display panel according to claim 24, wherein: The first metal layer includes a data line and a first power signal line that are spaced apart from each other. The reference signal line and the first power signal line are integrated signal lines.

27. The display panel according to claim 23, wherein: Also includes: a semiconductor layer located between the first metal layer and the base substrate, A third metal layer is located between the semiconductor layer and the substrate. Wherein, along a direction perpendicular to the base substrate, the second capacitor electrode and the first power signal line both overlap with the third metal layer, and the third metal layer is configured to receive the pixel driving voltage signal.

28. The display panel according to claim 27, wherein: The third metal layer is electrically connected to the first power signal line.

29. The display panel according to claim 27, wherein: The pixel circuit includes multiple transistors, which include at least the driving transistor, the first light-emitting control transistor and the first reset transistor. Along a direction perpendicular to the substrate, the third metal layer overlaps with the channel region of at least some of the multiple transistors.

30. The display panel according to claim 23, wherein Also includes: a semiconductor layer located between the first metal layer and the base substrate, A third metal layer is located between the semiconductor layer and the substrate. The pixel circuit includes a plurality of transistors, and the plurality of transistors include at least the driving transistor, the first light-emitting control transistor and the first reset transistor. Along a direction perpendicular to the substrate, the third metal layer overlaps with the channel region of at least some of the plurality of transistors.

31. The display panel according to claim 16, wherein Along a direction perpendicular to the substrate, the reference signal line overlaps with the plurality of signal lines.

32. The display panel according to claim 17, wherein: The reference signal line is configured to transmit the initialization voltage signal.

33. The display panel according to claim 32, wherein: Also includes: a semiconductor layer, located between the first metal layer and the base substrate, the semiconductor layer at least including an active layer pattern of the driving transistor; The semiconductor layer includes the reference signal line, and the fourth capacitor electrode is electrically connected to the first electrode of the first reset transistor through the reference signal line.

34. The display panel according to claim 33, wherein: The reference signal line and the first electrode of the first reset transistor are integrally arranged.

35. The display panel according to claim 32, wherein: The first metal layer includes the reference signal line, and the fourth capacitor electrode is electrically connected to the initialization voltage signal line through the reference signal line.

36. The display panel according to claim 35, wherein: The reference signal line and the fourth capacitor electrode are integrated into one structure.

37. The display panel according to claim 17, wherein: The pixel circuit further includes a data writing transistor, a second light emitting control transistor and a second reset transistor; The plurality of signal lines further include a second light emitting control signal line, a reset power signal line, a first scanning signal line and a third scanning signal line; The first metal layer includes a data line and a first power signal line; The first electrode of the data write transistor is electrically connected to the data line, the second electrode of the data write transistor is electrically connected to the gate of the drive transistor, the gate of the data write transistor is electrically connected to the first scan signal line, the first electrode of the second light-emitting control transistor is electrically connected to the first power signal line, the second electrode of the second light-emitting control transistor is electrically connected to the second electrode of the drive transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line, the first electrode of the second reset transistor is electrically connected to the reset power signal line, the second electrode of the second reset transistor is electrically connected to the first capacitor electrode, and the gate of the second reset transistor is electrically connected to the third scan signal line.

38. The display panel according to claim 9, wherein: Also includes: a semiconductor layer located between the first metal layer and the base substrate, The display panel further includes a plurality of light-emitting elements, each of which includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence, wherein the first electrode is located between the light-emitting functional layer and the base substrate, and the first electrode is electrically connected to the pixel circuit; The number of metal layers between the semiconductor layer and the first electrode of the light-emitting element is N1, and N1 is not greater than 2.

39. The display panel according to claim 9, wherein: Also includes: a semiconductor layer located between the first metal layer and the base substrate, The display panel further includes a plurality of light-emitting elements, each of which includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence, wherein the first electrode is located between the light-emitting functional layer and the base substrate, and the first electrode is electrically connected to the pixel circuit; The number of planar layers provided between the semiconductor layer and the first electrode of the light emitting element is N2, and N2 is not greater than 1.

40. The display panel according to claim 38 or 39, wherein: Each pixel circuit includes a plurality of transistors and a plurality of capacitors, the number of the plurality of transistors is greater than or equal to 5, and the number of the capacitors is greater than or equal to 2.

41. The display panel according to claim 1, wherein The multiple pixel circuits are arranged in an array along a first direction and a second direction. The size of the pixel circuit in one of the first direction and the second direction is 90~180 microns, and in the other of the first direction and the second direction, the sum of the sizes of two pixel circuits or three pixel circuits is 90~180 microns.

42. The display panel according to claim 1, wherein The display panel includes a plurality of sub-pixels, each sub-pixel includes the pixel circuit and a light-emitting element electrically connected to the pixel circuit, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked in layers, the first electrode is located between the light-emitting functional layer and the base substrate, and the first electrode is electrically connected to the pixel circuit; The multiple sub-pixels are divided into multiple pixel units, each pixel unit includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, the first color sub-pixel and the second color sub-pixel are arranged along a first direction, the first color sub-pixel and the third color sub-pixel are arranged along a second direction, and the first direction intersects with the second direction.

43. The display panel according to claim 42, wherein: Also includes: An isolation structure is located on the substrate. The isolation structure is configured to separate the light-emitting functional layer and the second electrode of the sub-pixel.

44. The display panel according to claim 43, wherein: A plurality of isolation openings are provided in the isolation structure, and portions of the film layer configured to form the light-emitting functional layer and the second electrode of the sub-pixel, located outside specific isolation openings among the plurality of isolation openings, are removed by a photolithography process, and the specific isolation openings are isolation openings corresponding to the sub-pixel on which the light-emitting functional layer and the second electrode are to be formed.

45. The display panel according to claim 43, wherein: Also includes: A first metal layer is located on the base substrate; a second metal layer, located on a side of the first metal layer away from the substrate; In which, the isolation structure is located on a side of the second metal layer away from the first metal layer, the first metal layer includes the first capacitor electrode, the fourth capacitor electrode and the reference signal line, the second metal layer includes the second capacitor electrode and the third capacitor electrode, and the second capacitor electrode and the third capacitor electrode are integrated capacitor plates, and the capacitor plates cover the gap between the first capacitor electrode and the fourth capacitor electrode, the reference signal line is electrically connected to the fourth capacitor electrode, and is configured to transmit a low-potential power supply voltage signal to the fourth capacitor electrode.

46. ​​The display panel according to claim 45, wherein: The reference signal line extends along the first direction, the second metal layer includes a second power signal line extending along the second direction, the second power signal line is located between the pixel circuits of adjacent sub-pixels, and the reference signal line is electrically connected to the second power signal line to receive the low-potential power voltage signal.

47. The display panel according to claim 46, wherein: The second electrode is electrically connected to the isolation structure, and the isolation structure is electrically connected to the reference signal line.

48. The display panel according to claim 47, wherein: Also includes: a pixel defining pattern located on a side of the second metal layer away from the base substrate, the pixel defining pattern comprising a plurality of pixel openings and a pixel defining portion surrounding the plurality of pixel openings, the plurality of pixel openings being configured to define light-emitting areas of the plurality of sub-pixels; The isolation structure is located on a side of the pixel defining portion away from the base substrate, and the isolation structure is electrically connected to the reference signal line through a via hole in the pixel defining portion.

49. The display panel according to claim 48, wherein Also includes: The auxiliary connection portion is located in at least one of the film layer where the first electrode of the light-emitting element is located, the first metal layer, and the second metal layer. Wherein, the isolation structure is electrically connected to the reference signal line through the auxiliary connection portion.

50. The display panel according to claim 49, wherein: Along a direction perpendicular to the base substrate, the reference signal line includes a first reference signal line portion overlapping with the auxiliary connection portion and a second reference signal line portion not overlapping with the auxiliary connection portion, and the maximum width of the first reference signal line portion is greater than the maximum width of the second reference signal line portion.

51. The display panel according to claim 49, wherein: Along a direction perpendicular to the base substrate, the reference signal line and the second power signal line both overlap with the auxiliary connection portion, and the auxiliary connection portion includes a first auxiliary connection portion overlapping with the reference signal line and a second auxiliary connection portion overlapping with the second power signal line.

52. The display panel according to claim 51, wherein The isolation structure includes a ring-shaped isolation structure surrounding a light-emitting area of ​​at least one sub-pixel, and the ring-shaped isolation structure overlaps the auxiliary connection portion along a direction perpendicular to the base substrate.

53. The display panel according to claim 52, wherein: There are multiple annular isolation structures, each of which surrounds the light-emitting area of ​​a sub-pixel, and intervals are provided between the isolation structures surrounding the light-emitting areas of sub-pixels of different colors.

54. The display panel according to claim 52, wherein: At least one annular isolation structure surrounds the light-emitting areas of a plurality of sub-pixels of the same color.

55. The display panel according to claim 45, wherein: The plurality of sub-pixels include sub-pixels of different colors, and the second electrodes of at least two sub-pixels of different colors are configured to transmit different low-potential power supply voltage signals.

56. The display panel according to claim 45, wherein: The first electrode of the light-emitting element includes a main electrode and a connecting electrode, and the main electrode overlaps with the light-emitting area of ​​the sub-pixel; An insulating layer is provided between the connecting electrode and the second electrode of the first light-emitting control transistor in the pixel circuit, and the connecting electrode is electrically connected to the second electrode of the first light-emitting control transistor through an anode via in the insulating layer; In the same sub-pixel, the orthographic projection of the anode via on the substrate is a first orthographic projection, the orthographic projection of the light-emitting area on the substrate is a second orthographic projection, and the distance between the edges of the first orthographic projection and the second orthographic projection close to each other is a first sub-distance, and the first sub-distance is 1~3 microns.

57. The display panel according to claim 56, wherein: The orthographic projection of the isolation structure on the substrate is a third orthographic projection, the minimum distance between the third orthographic projection and the second orthographic projection is a second sub-distance, and the second sub-distance is 2-5 micrometers.

58. The display panel according to claim 57, wherein: The first sub-distance is smaller than the second sub-distance.

59. The display panel according to any one of claims 43 to 58, wherein: The size of the isolation structure in a direction perpendicular to the substrate is 1.5 to 3 microns.

60. The display panel according to claim 42, wherein: The first electrode includes a main electrode and a connecting electrode, the main electrode overlaps with the light-emitting area of ​​the sub-pixel, and the connecting electrode is electrically connected to the second electrode of the first light-emitting control transistor in the pixel circuit; The length of the connecting electrode of the first color sub-pixel in a preset direction is greater than the size of the light-emitting area of ​​the second color sub-pixel in the preset direction.

61. The display panel according to claim 60, wherein: The preset direction is the first direction.

62. The display panel according to claim 1, wherein: The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; Each sub-pixel includes the pixel circuit and a light-emitting element electrically connected to the pixel circuit, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode that are stacked, and the first electrode is located between the light-emitting functional layer and the base substrate; The light-emitting functional layer includes a first electron blocking layer, a first light-emitting layer, a charge generation layer, a second electron blocking layer and a second light-emitting layer stacked in sequence, wherein the first light-emitting layer is located between the second light-emitting layer and the first electrode; There is a first distance L between the surfaces of the first electrode and the second electrode that are close to each other, a second distance L1 between the surface of the second light-emitting layer facing the substrate and the surface of the second electrode facing the substrate, a third distance L2 between the surface of the first light-emitting layer away from the substrate and the surface of the first electrode away from the substrate, a fourth distance L3 between the surfaces of the first light-emitting layer and the second light-emitting layer that are close to each other, a fifth distance L4 between the surface of the first light-emitting layer away from the substrate and the surface of the first electron blocking layer close to the substrate, the charge generating layer has a first thickness L5, and a sixth distance L6 between the surface of the second light-emitting layer away from the substrate and the surface of the second electron blocking layer close to the substrate.

63. The display panel according to claim 62, wherein: The ratio of the distance between the first light-emitting layer and the surfaces of the first electrode close to each other to the first distance L is 0.2-0.3, and the ratio of the distance between the second light-emitting layer and the surfaces of the first electrode close to each other to the first distance is 0.7-0.

8.

64. The display panel according to claim 62, wherein: In the first color sub-pixel, the third distance L2 and the fifth distance L4 satisfy 0.6≤L4 / L2≤0.9; in the second color sub-pixel, the third distance L2 and the fifth distance L4 satisfy 0.5≤L4 / L2≤0.8; in the third color sub-pixel, the third distance L2 and the fifth distance L4 satisfy 0.3≤L4 / L2≤0.

7.

65. The display panel according to claim 62, wherein: In the first color sub-pixel, the sixth distance L6 and the second distance L1 satisfy 0.8≤L6 / L1≤1.2; in the second color sub-pixel, the sixth distance L6 and the second distance L1 satisfy 0.5≤L6 / L1≤0.9; in the third color sub-pixel, the sixth distance L6 and the second distance L1 satisfy 0.3≤L6 / L1≤0.

6.

66. The display panel according to claim 62, wherein: In the first color sub-pixel, the first thickness L5 and the first distance L satisfy 0.07≤L5 / L≤0.12; in the second color sub-pixel, the first thickness L5 and the first distance L satisfy 0.09≤L5 / L≤0.15; in the third color sub-pixel, the first thickness L5 and the first distance L satisfy 0.12≤L5 / L≤0.

18.

67. The display panel according to claim 62, wherein: The light-emitting functional layer further includes a hole transport layer located between the second electron blocking layer and the charge generating layer, and the hole transport layer has a second thickness L7; In the first color sub-pixel, the second thickness L7 and the fourth distance L3 satisfy 0.1≤L7 / L3≤0.6; in the second color sub-pixel, the second thickness L7 and the fourth distance L3 satisfy 0.2≤L7 / L3≤0.7; in the third color sub-pixel, the second thickness L7 and the fourth distance L3 satisfy 0.25≤L7 / L3≤0.

8.

68. The display panel according to claim 62, wherein: The light-emitting functional layer further includes an electron injection layer located between the second light-emitting layer and the second electrode. The thickness of the electron injection layer is 1 to 10 angstroms or 11 to 19 angstroms.

69. The display panel according to claim 1, wherein: When the display panel is at maximum brightness and maintained for 10 minutes, the temperature of the display panel does not exceed 40 degrees; when the display panel is at maximum brightness and maintained for 10 to 26 minutes, the temperature of the display panel does not exceed 50 degrees.

70. The display panel according to claim 69, wherein: The diagonal size of the display surface of the display panel is greater than or equal to 39.6 cm.

71. The display panel according to claim 70, characterized in that The display panel includes a plurality of sub-pixels, the plurality of sub-pixels are divided into a plurality of pixel units, the plurality of pixel units include a plurality of pixel unit rows arranged along a first direction, and the number of pixel units in each pixel unit row is greater than or equal to 2560; the plurality of pixel units include a plurality of pixel unit columns arranged along a second direction, and the number of pixel units in each pixel unit column is greater than or equal to 1440; The first direction intersects the second direction.

72. The display panel according to claim 71, wherein: Each pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel and the second color sub-pixel are arranged along the first direction, and the first color sub-pixel and the third color sub-pixel are arranged along the second direction.

73. A display device, characterized in that A display panel comprising any one of claims 1-72.

74. The display device according to claim 73, characterized in that The display device is a vehicle-mounted display device.

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