Charging and discharging control protection circuit of farad capacitor
Through the combination of reset chip and self-locking circuit, the problem of automatic power supply of the fala capacitor under abnormal conditions is solved, and the overcharge protection of the fala capacitor is achieved, extending the service life and reducing safety risks.
Patent Information
- Application Number
- CN202422584114.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-10-25
AI Technical Summary
In the prior art, the fala capacitor may automatically restore power supply under abnormal conditions, resulting in overcharge risk and lack of an effective overcharge protection mechanism.
The reset chip and self-locking circuit are adopted, and the control circuit consisting of MOS tubes and resistor capacitors can realize the charging and discharging control of the falap capacitor. The self-locking mechanism disconnects the relay and remains powered off when the voltage reaches the rated upper limit, until it is manually reset or restored by other control signals.
It effectively prevents the overcharge of Farala capacitors, extends the service life, reduces safety hazards, and improves the degree of automation and system reliability.
Smart Images
Figure CN223297394U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of charge and discharge protection, and in particular to a charge and discharge control protection circuit for a farad capacitor. Background Art
[0002] In the existing technology, microcontrollers or timers are usually used to control the charging process of farad capacitors. These methods can temporarily cut off the power supply when the voltage exceeds the standard, but the power supply may be automatically restored before the abnormal condition is effectively resolved, increasing the risk of overcharging.
[0003] Therefore, how to implement overcharge protection for farad capacitors is a problem that needs to be solved. Utility Model Content
[0004] The purpose of the present application is to provide a charge and discharge control protection circuit for a farad capacitor, so as to solve the problem in the prior art that the power supply may be automatically restored under abnormal conditions when the farad capacitor is being charged.
[0005] The technical solution of the present application is: a charge and discharge control protection circuit for a farad capacitor, comprising a reset chip, a control circuit and a self-locking circuit; the control circuit is connected to the reset chip for realizing charging control; the self-locking circuit is connected to the reset chip for realizing switch control; the self-locking circuit comprises a first MOS tube, a second MOS tube, a first resistor and a second resistor; the gate of the first MOS tube is connected to pin 1 of the reset chip, the source is grounded, and the drain is connected to the gate of the second MOS tube; pin 3 of the reset chip is connected to the power supply VBAT; the source of the second MOS tube is connected to the interface VIN, which is the solar panel power charging input interface, and the drain of the second MOS tube is connected to the charge and discharge interface VBAT; the first resistor is connected between the interface VIN and the gate of the first MOS tube, and the second resistor is connected between the drain of the first MOS tube and the source of the second MOS tube to play a voltage-reducing role; the first MOS tube is an N-type MOS tube, and the second MOS tube is a P-type MOS tube.
[0006] Preferably, the control circuit includes a third resistor, a fourth resistor, a fifth resistor and a third capacitor; one end of the third resistor is connected to pin 3 of the reset chip, the other end is connected in series with the fourth resistor, and the other end of the fourth resistor is grounded; one end of the fifth resistor is connected to pin 4 of the reset chip, and the other end is connected between the third resistor and the fourth resistor; the third capacitor and the fourth resistor are connected in parallel, and the two ends of the third capacitor and the fourth resistor are respectively connected to pin 2 and pin 5 of the reset chip.
[0007] Preferably, the control circuit further includes a fourth capacitor and a fifth capacitor, the fourth capacitor and the fifth capacitor are connected in parallel, one end of the fourth capacitor and the fifth capacitor are both connected to the power supply VBAT, and the other end of the fourth capacitor and the fifth capacitor are both grounded.
[0008] Preferably, the self-locking circuit further includes a first capacitor and a second capacitor, one end of the first capacitor and the second capacitor is connected between the drain of the second MOS transistor and the charge and discharge interface VBAT, and the other end is grounded.
[0009] The charge and discharge control protection circuit of the farad capacitor of the present application, through the reset chip and the self-locking circuit, once it is detected that the farad capacitor voltage reaches the rated upper limit, the relay can be controlled to disconnect and remain in the power-off state until it is manually reset or restored by other control signals. This self-locking mechanism effectively prevents the occurrence of overcharging, extends the service life of the farad capacitor, and reduces the safety hazards caused by overcharging. It is not only suitable for scenarios where solar energy charges farad capacitors, but can also be widely used in other electronic devices that require farad capacitors as energy storage elements. This wide applicability makes the present invention have stronger practicality and market prospects. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to more clearly illustrate the technical solutions provided by this application, the following is a brief introduction to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of this application.
[0011] Figure 1 This is a schematic diagram of the overall circuit structure of this application.
[0012] 1. Reset chip; 2. First MOS tube; 3. Second MOS tube; 4. First resistor; 5. Second resistor; 6. First capacitor; 7. Second capacitor; 8. Third resistor; 9. Fourth resistor; 10. Fifth resistor; 11. Third capacitor; 12. Fourth capacitor; 13. Fifth capacitor. DETAILED DESCRIPTION
[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0014] A charging and discharging control protection circuit for a farad capacitor, such as Figure 1 As shown, it includes a reset chip 1, a control circuit and a self-locking circuit.
[0015] Reset chip 1 is a high-precision, low-power, small-package programmable voltage detection chip developed using CMOS technology. Its function is to flip the output logic when the voltage on the detected interface VIN drops to the VDET voltage point. Reset chip 1 is powered by VDD.
[0016] The control circuit is connected to the reset chip 1 for realizing charging control; the self-locking circuit is connected to the reset chip 1 for realizing switch control.
[0017] The self-locking circuit includes a first MOS transistor 2, a second MOS transistor 3, a first resistor 4, and a second resistor 5. The gate of the first MOS transistor 2 is connected to pin 1 of the reset chip 1, the source is grounded, and the drain is connected to the gate of the second MOS transistor 3. Pin 3 of the reset chip 1 is connected to the power supply VBAT. The source of the second MOS transistor 3 is connected to the VIN interface, which is the charging input interface of the solar panel power supply, and the drain of the second MOS transistor 3 is connected to the charge and discharge interface VBAT. The first resistor 4 is connected between the VIN interface and the gate of the first MOS transistor 2, and the second resistor 5 is connected between the drain of the first MOS transistor 2 and the source of the second MOS transistor 3 to provide a voltage reduction function. The first MOS transistor 2 is an N-type MOS transistor, and the second MOS transistor 3 is a P-type MOS transistor.
[0018] Preferably, the self-locking circuit further includes a first capacitor 6 and a second capacitor 7, one end of the first capacitor 6 and the second capacitor 7 are connected between the drain of the second MOS tube 3 and the charge and discharge interface VBAT, and the other end is grounded, for achieving filtering and ensuring signal stability.
[0019] The control circuit includes a third resistor 8, a fourth resistor 9, a fifth resistor 10, and a third capacitor 11. One end of the third resistor 8 is connected to pin 3 of the reset chip 1, and the other end is connected in series with the fourth resistor 9. The other end of the fourth resistor 9 is grounded. One end of the fifth resistor 10 is connected to pin 4 of the reset chip 1, and the other end is connected between the third resistor 8 and the fourth resistor 9. The third capacitor 11 and the fourth resistor 9 are connected in parallel, and the ends of the third capacitor 11 and the fourth resistor 9 are connected to pins 2 and 5 of the reset chip 1, respectively.
[0020] The charge and discharge interface VBAT and the power supply VBAT are connected to a farad capacitor network.
[0021] When powered on for the first time, the voltage of the interface VIN starts to rise slowly from 0V. When the voltage of the interface VIN is less than 4.3V, pin 1 of the reset chip 1 outputs a high level. At this time, the first MOS tube 2 is turned on and grounded, and the gate of the second MOS tube 3 is at a low level. The second MOS tube 3 is turned on, and the power provided by the solar panel is charged to the charge and discharge interface VBAT through the second MOS tube 3.
[0022] At the same time, the pin 4 of the reset chip 1 outputs a low level, pulling down the fifth resistor 10 to achieve the equivalent grounding effect. The equivalent effect is the parallel connection of the fourth resistor 9 and the fifth resistor 10 .
[0023] When the VIN input voltage is greater than 4.3V, pin 1 of the reset chip 1 outputs a low level, the first MOS transistor 2 is not conducting and cannot be grounded, which in turn cannot lower the gate voltage of the second MOS transistor 3. The second MOS transistor 3 is not conducting, thus shutting off the solar power and preventing it from being added to the network charging port VBTA.
[0024] At this time, pin 4 of the reset chip 1 outputs a high level, which pulls up the fifth resistor 10 to achieve the equivalent effect of grounding. The equivalent effect is the parallel connection of the third resistor 8 and the fifth resistor 10 .
[0025] When the farad capacitor network connected to the charge-discharge interface VBAT discharges to other external circuits, the voltage gradually decreases. When it drops to 3.3V, pin 1 of reset chip 1 outputs a high level, the first MOS transistor 2 is turned on and grounded, and the gate of the second MOS transistor 3 is at a low level, turning on the second MOS transistor 3. The power provided by the solar panel charges the charge-discharge interface VBAT through the second MOS transistor 3. The voltage of the interface VIN then increases, thus achieving cyclic charging.
[0026] By using reset chip 1 and a self-locking circuit, once the voltage on the farad capacitor reaches its rated upper limit, the relay is controlled to disconnect and remain de-energized until manually reset or restored via other control signals. This self-locking mechanism effectively prevents overcharging, extends the life of the farad capacitor, and reduces safety hazards caused by overcharging.
[0027] The invention is not only applicable to scenarios where solar energy is used to charge a farad capacitor, but can also be widely used in other electronic devices that require a farad capacitor as an energy storage element. This wide applicability makes the invention more practical and has a greater market prospect.
[0028] The entire protection process requires no human intervention; everything from charging control to self-locking protection and status indication is completed automatically. This increased level of automation significantly improves user experience and system reliability, while reducing maintenance costs.
[0029] Preferably, the control circuit further includes a fourth capacitor 12 and a fifth capacitor 13, which are connected in parallel to each other, and one end of the fourth capacitor 12 and the fifth capacitor 13 are connected to the power supply VBAT and the other end are grounded to achieve a filtering function.
[0030] Finally, it should be noted that the drawings of the embodiments disclosed in this utility model only involve structures related to the embodiments disclosed in this utility model. Other structures can refer to common designs. In the absence of conflicts, the same embodiment and different embodiments of the utility model can be combined with each other.
[0031] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A charge and discharge control protection circuit for a farad capacitor, characterized in that: The invention comprises a reset chip (1), a control circuit and a self-locking circuit; the control circuit is connected to the reset chip (1) for realizing charging control; the self-locking circuit is connected to the reset chip (1) for realizing switch control; the self-locking circuit comprises a first MOS tube (2), a second MOS tube (3), a first resistor (4) and a second resistor (5); the gate of the first MOS tube (2) is connected to pin 1 of the reset chip (1), the source is grounded, and the drain is connected to the gate of the second MOS tube (3); pin 3 of the reset chip (1) is connected to a power supply VBAT; the source of the second MOS tube (3) is connected to an interface VIN, which is a solar panel power supply charging input interface, and the drain of the second MOS tube (3) is connected to a charging and discharging interface VBAT; the first resistor (4) is connected between the interface VIN and the gate of the first MOS tube (2), and the second resistor (5) is connected between the drain of the first MOS tube (2) and the source of the second MOS tube (3), playing a role of reducing voltage; the first MOS tube (2) is an N-type MOS tube, and the second MOS tube (3) is a P-type MOS tube.
2. The charge and discharge control protection circuit for a farad capacitor according to claim 1, wherein: The control circuit comprises a third resistor (8), a fourth resistor (9), a fifth resistor (10) and a third capacitor (11); one end of the third resistor (8) is connected to pin 3 of the reset chip (1), and the other end is connected in series with the fourth resistor (9), and the other end of the fourth resistor (9) is grounded; one end of the fifth resistor (10) is connected to pin 4 of the reset chip (1), and the other end is connected between the third resistor (8) and the fourth resistor (9); the third capacitor (11) and the fourth resistor (9) are connected in parallel, and the two ends of the third capacitor (11) and the fourth resistor (9) are respectively connected to pin 2 and pin 5 of the reset chip (1).
3. The charge and discharge control protection circuit for a farad capacitor according to claim 2, wherein: The control circuit further comprises a fourth capacitor (12) and a fifth capacitor (13), wherein the fourth capacitor (12) and the fifth capacitor (13) are connected in parallel with each other, and one end of each of the fourth capacitor (12) and the fifth capacitor (13) is connected to a power supply VBAT, and the other end of each of the fourth capacitor (12) and the fifth capacitor (13) is grounded.
4. The charge and discharge control protection circuit for a farad capacitor according to claim 1, wherein: The self-locking circuit further comprises a first capacitor (6) and a second capacitor (7), one end of the first capacitor (6) and the second capacitor (7) being connected between the drain of the second MOS tube (3) and the charge-discharge interface VBAT, and the other end being grounded.