Component carrier structure

Abstract

The embodiment of the utility model provides a component bearing piece structure (100). The component carrier structure (100) comprises: a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); a first level identifier structure (108), the first level identifier structure (108) being arranged in the stack (102); and at least one second level identifier structure (110), the at least one second level identifier structure (110) being arranged at least at at least one exposed surface (112) of at least one of the respective layer structures of the stack (102); wherein the first level identifier structure (108) and the at least one second level identifier structure (110) are laterally spaced apart from each other, and both the first level identifier structure (108) and the at least one second level identifier structure (110) can be read only from one side of the stack (102).

Description

Technical Field

[0001] The present application relates to the field of semiconductor device manufacturing, and in particular to a component carrier structure. Background Art

[0002] This section provides background information related to the present application but does not necessarily constitute prior art.

[0003] Against the backdrop of the increasing product functionality of component carriers (such as printed circuit boards) equipped with one or more electronic components, the increasing miniaturization of these electronic components, and the increasing number of electronic components to be mounted on component carriers, increasingly powerful array-shaped components or packages with several electronic components are being used. These array-shaped components or packages have a plurality of contacts or connections, the spacing between which is becoming increasingly smaller. Such component carriers should be mechanically robust and electrically reliable in order to be able to operate even under harsh conditions.

[0004] Effectively controlling batch manufacturing processes for producing component carriers is challenging. It is desirable for component carriers or their preforms to have traceability, i.e., the ability to track and identify component carrier structures or their associated bodies, for example, during manufacture and / or use. Tracking component carrier structures can allow verification of the manufacturing history, location, manufacturing environment (e.g., temperature, humidity), or application of individual component carrier structures. Utility Model Content

[0005] This section provides a general summary of the application, and is not a comprehensive disclosure of its full scope or all of its features.

[0006] According to an exemplary embodiment of the present application, a component carrier structure is provided, which includes: a stack, which includes at least one electrically conductive layer structure and at least one electrically insulating layer structure; a first-level identifier structure, which is arranged in the stack; and at least one second-level identifier structure, which is arranged at least at least one exposed surface of at least one layer structure among the individual layer structures of the stack; wherein the first-level identifier structure and the at least one second-level identifier structure are spaced apart from each other in the laterally, and both the first-level identifier structure and the at least one second-level identifier structure can be read only from one side of the stack.

[0007] In the context of the present application, the term "component-carrier structure" may particularly denote any support structure capable of accommodating one or more components thereon and / or therein to provide mechanical support and / or electrical connection and / or optical connection and / or thermal connection. In other words, the component carrier may be configured as a mechanical and / or electronic support for the components.

[0008] In the context of the present application, the term "stack" may particularly denote an arrangement comprising a plurality of planar layer structures arranged parallel to each other.

[0009] In the context of the present application, the term "layer structure" may particularly denote a continuous layer, a patterned layer or a plurality of non-continuous islands in a common plane.The layer structure may be electrically insulating and / or electrically conductive.

[0010] In the context of the present application, the term "surface" of a layer structure may denote an accessible surface of an electrically conductive layer structure or an accessible surface of an electrically insulating layer structure.

[0011] In some embodiments, the surface of a layer structure may specifically refer to the main surface of the layer structure. The main surface of a layer structure may refer to the planar surface of the layer structure that generally has the largest surface area. The main surface of an electrically conductive layer structure may include pads, conductive traces, and other features for mounting electronic components and electrical connection. The main surface of an electrically insulating layer structure may include features for achieving electrical isolation. In certain embodiments, the main surface of a layer structure may be further defined as a surface with specific functional areas, such as a signal processing area, a power management area, or a user interface area. It will be understood that the definition of the main surface may vary depending on the design and application of the layer structure or even the entire component carrier structure, but the common feature is that it is the main working surface on the layer structure or component carrier structure for mounting electronic components and providing electrical functions and the required electrical isolation functions. The thickness of the layer structure can be defined by the distance between two relative main surfaces.

[0012] In the context of this application, the term "identifier structure" may particularly refer to a physical structure used to identify a component carrier structure or a stacked component layer structure. In the context of this application, the term "stacked component layer structure" or "layer structure" may particularly refer to an electrically conductive layer structure and / or an electrically insulating layer structure of a stacked component. The identifier structure may be an information-carrying structure and may include an identifier (e.g., a recognizable pattern) that can identify the component carrier structure or a layer structure therein. In some embodiments, the identifier structure or a combination thereof may be unique to a particular component carrier structure or stacked component layer structure. In other embodiments, the identifier structure or a combination thereof may be identical for a certain number of component carrier structures, such as for a portion of component carrier structures manufactured within a common batch or lot. The identifier structure may, for example, include a data matrix code or a QR code. The identifier structure may include information such as a link to a specific data set in a database. The identifier structure may, for example, include information regarding the properties of the component carrier structure or its layer structure itself, including, but not limited to, a unique identifier, process parameters, equipment number, batch number, panel serial number, material information, exception records, quality inspection results, and panel production date and time information. Additionally or alternatively, information about a defect state of the component carrier structure including the identifier structure may also be stored in the data set.

[0013] In the context of the present application, "both the first-level identifier structure and the at least one second-level identifier structure are readable only from one side of the stack" may specifically mean that the first-level identifier structure and the at least one second-level identifier structure are readable only from the same side of the stack by an optical reader located outside the stack. In other words, when performing a reading operation on the first-level identifier structure and the second-level identifier structure, respectively, the orientation / position of the optical reader relative to the stack should be substantially the same or similar, for example, the optical reader should always be located on the upper side of the stack.

[0014] In the context of the present application, "transverse" may particularly denote a direction parallel to a planar surface of the stack. Correspondingly, "vertical" may particularly denote a direction perpendicular to a planar surface of the stack.

[0015] In the context of the present application, the term "optically readable pattern" may particularly denote a pattern that can be read by an optical reader device for the purpose of identifying or characterizing a component carrier structure or a portion thereof. Exemplarily, the optically readable pattern may comprise a one-dimensional code, a two-dimensional code, a three-dimensional code, or a data matrix code. For example, a three-dimensional code may be a code comprising different colors and / or depth information. In some embodiments, a data matrix code may be preferred because such a code is still readable even when parts of it are damaged. Due to the harsh conditions that may exist during the manufacture of the component carrier structure, it may be advantageous to use such a fault-robust data matrix code.

[0016] Exemplary embodiments provide a component carrier structure comprising a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure. A first-level identifier structure is disposed within the stack, and at least one second-level identifier structure, laterally spaced apart from the first-level identifier structure, is disposed on at least one exposed surface of at least one of the stack's layer structures (the electrically insulating layer structure and / or the electrically conductive layer structure). The first-level identifier structure and the at least one second-level identifier structure are arranged so as to be optically readable only from one side of the stack or component carrier structure. The first-level and second-level identifier structures encode information such that the component carrier structure, or even individual layer structures thereof (the electrically insulating layer structure or the electrically conductive layer structure), can be identified and / or tracked by optically reading the information from the first-level and / or second-level identifier structures. For example, an optical reader (e.g., a scanner, a camera) can obtain information related to the layer structure associated with the identifier structure or the entire component carrier structure (e.g., identification information and / or manufacturing information) by scanning the optically readable pattern of the identifier structure with an optical reader (e.g., a scanner, a camera). For example, an optical reading device, by scanning the optically readable pattern of the identifier structure, can be linked to a specific data set in a database and can retrieve information of interest from that data set.

[0017] Identifying a component carrier structure or a portion thereof based on optically reading the first-level and / or second-level identifier structure may include determining identity information about the component carrier structure or a portion thereof to distinguish it from other or even all other component carrier structures or portions. Tracking the component carrier structure based on the information optically read from the first-level and / or second-level identifier structure may allow tracing back each individual component carrier structure or even individual layer structures within the component carrier structure within a specific time interval, for example, during its entire manufacturing process or during its lifetime.

[0018] In the following, further exemplary embodiments of the component carrier structure will be explained.

[0019] In some optional embodiments, the component carrier structure includes multiple second-level identifier structures, the vertically projected areas of the multiple second-level identifier structures at least partially overlapping. The multiple second-level identifier structures can be arranged on different layers of the stack. The multiple second-level identifier structures can be spaced apart vertically and at most partially spaced apart laterally, such that when the stack is viewed vertically from outside, the second-level identifier structures in the stack at least partially overlap. In some embodiments, the vertically projected areas of the multiple second-level identifier structures substantially completely overlap. The multiple overlapping identifier structures can provide self-positioning, thereby improving manufacturing accuracy.

[0020] In some optional embodiments, a portion of the stack vertically positioned above the first-level identifier structure is configured to allow the first-level identifier structure to be read through the portion. An optical reader can read the first-level identifier structure through the portion of the layer structure even if the first-level identifier structure is located deep within the stack.

[0021] In some optional embodiments, the portion of at least one layer of the stack vertically positioned above the first-level identifier structure includes at least one opening formed in the at least one layer. In embodiments, the opening may be referred to as an optical inspection opening, as it allows for optical inspection of the first-level identifier structure that is laterally aligned with the opening and disposed deeper within the stack. The optical inspection opening allows an optical reader to directly observe the first-level identifier structure deeper within the stack, thereby improving the precision and accuracy of inspection. Direct inspection helps reduce errors caused by obstructions or indirect measurement.

[0022] In some optional embodiments, the plurality of openings are laterally aligned with one another, or more precisely, the plurality of openings are vertically aligned and not laterally offset from one another, thereby collectively forming a channel extending from the exposed surface of the stack to the first-level identifier structure; or, at least some of the plurality of openings are laterally offset relative to one another but partially overlap, thereby collectively forming a channel extending from the exposed surface of the stack to the first-level identifier structure. The plurality of optical detection openings are vertically adjacent and at least partially overlap laterally, forming an optical detection channel from the outermost surface of the stack to the first-level identifier structure. An optical reader can optically detect, in particular directly detect, the first-level identifier structure through the optical detection channel.

[0023] In some optional embodiments, the openings and / or channels may be at least partially filled with an electrically insulating block that enables the first-level identifier structure to be read from the outside of the stack through the corresponding openings and / or channels. The electrically insulating block may be, for example, a resin block. Arranging the electrically insulating block in the openings and / or channels allows for the possibility of optically detecting the first-level identifier structure located deeper in the stack through the openings and / or channels without losing the electrical reliability of the component carrier structure. In addition, it is well known that in the manufacturing process of the component carrier, it is inevitable to laminate electrically insulating materials (such as resins) on the surface of the stack. However, the inventors of the present application were surprised to find that, according to the technical solution provided in the embodiments of the present application, the electrically insulating block filled in the openings and / or channels above the first identifier structure after lamination does not need to be removed, and the optical reading device can still accurately identify the first identifier structure below the electrically insulating block. Therefore, the openings and / or channels are at least partially filled with an electrically insulating block that enables the first-level identifier structure to be read from the outside of the stack through the corresponding openings and / or channels, thereby achieving efficient and accurate optical detection while simplifying the manufacturing process.

[0024] In some optional embodiments, the lateral coverage of the openings matches the lateral coverage of the first-level identifier structure. The lateral coverage of the openings matching the first-level identifier structure can mean that each opening in the layer structure above the first-level identifier structure can have the same or similar size and the same lateral position as the first-level identifier structure. In particular, the geometric parameters of the openings (such as length and width) can be selected so that in a top view from outside the stack (and therefore in the viewing direction of the optical reader), the shape of the openings corresponds to the shape of the first-level identifier structure. In other words, the first-level identifier structure is vertically displaced relative to the openings and laterally aligned.

[0025] In some optional embodiments, the first-level identifier structure and / or the second-level identifier structure are integrally formed with the stack. In such embodiments, the electrically conductive layer structure and the electrically insulating layer structure forming the (preferably laminated) layer stack may include portions forming the identifier structure. Thus, the same layer structure may be used to form both the stack and at least one identifier structure.

[0026] In some optional embodiments, the optically readable patterns of the first-level identifier structure and / or the at least one second-level identifier structure are different from each other. In some embodiments, the optically readable pattern of the first-level identifier structure can be different from the optically readable pattern of any of the at least one second-level identifier structures. In some embodiments, the optically readable patterns of at least one second-level identifier structure are different from each other. This facilitates tracing differentiating features or manufacturing information in different layer structures, for example, facilitating accurate and rapid tracing of material information, abnormal conditions, process parameters, production time, etc., of a specific layer structure.

[0027] In some alternative embodiments, the optically readable pattern of the identifier structure disposed in one of the stack layers is different from the optically readable pattern of the identifier structure disposed in another layer of the stack. In some embodiments, for ease of description, the first-level identifier structure and the second-level identifier structure may be collectively referred to as an identifier structure.

[0028] Two or more identifier structures in a stack that differ from each other make it possible to trace manufacturing information at the layer level. More specifically, this allows for the creation of layer-specific identifier structures, allowing the manufacturing process of individual layers of a component carrier structure to be reflected in the layer-specific identifier structures. This enables the traceability of the characteristics of each individual layer of the stack during the manufacturing process.

[0029] In some optional embodiments, each component carrier structure includes a unique identifier structure. The first-level identifier structure and / or the second-level identifier structure included in each component carrier structure are different from other first-level identifier structures and / or other second-level identifier structures included in other component carrier structures.

[0030] In some optional embodiments, the optically readable pattern formed by the first-level identifier structure is identical to the optically readable pattern formed by each of the second-level identifier structures. In some embodiments, the first-level identifier structure is positioned deeper within the stack relative to the second-level identifier structure, and the first-level identifier structure can be directly read from outside the stack by an optical reader. Thus, during the manufacturing process of the stack, when a new layer structure is stacked, e.g., laminated, above the location of the first-level identifier structure, the second-level identifier structure can be easily manufactured on the new layer structure based on the optically readable pattern read by directly reading the first-level identifier structure using an optical reader.

[0031] In some optional embodiments, at least two of the at least one second-level identifier structure and the first-level identifier structure are formed with the same optically readable pattern. Advantageously, when some identifier structures with the same optical pattern become unreadable due to damage or other reasons, sufficient information can be obtained by reading other identifier structures with the same optical pattern, thereby avoiding the possibility of untraceability.

[0032] In some optional embodiments, the electrically conductive layer structure at least partially forms an optically readable pattern of the first-level identifier structure and / or the second-level identifier structure. In embodiments, the first-level identifier structure and / or the second-level identifier structure can be a patterned portion of at least one electrically conductive layer structure of the stack. This makes it easier and more reliable to construct identifier structures in a stack-type component carrier structure comprising an electrically conductive layer structure. Advantageously, the identifier structure can be formed during the process of manufacturing the component carrier structure based on the stack, in particular by correspondingly processing one or more electrically conductive layer structures of the stack so that the patterned at least one electrically conductive layer structure includes information or a link to said information (e.g. a link to a data set in a database, which link and data set are assigned to the component carrier structure or a part thereof). For example, the copper foil of the stack can be patterned in the surface area of ​​the panel to form a data matrix code or a QR code.

[0033] In some optional embodiments, the first-level identifier structure and at least one second-level identifier structure are both located in an area of ​​the component carrier structure other than the functional area. The functional area of ​​the component carrier structure can specifically refer to an area of ​​the component carrier structure associated with the functions of mounting electronic components, electrically connecting them, and isolating them. Placing the identifier structures in non-functional areas of the component carrier structure avoids potential adverse effects of the identifier structures on the electrical characteristics of the component carrier structure.

[0034] In some optional embodiments, the first-level identifier structure and at least one second-level identifier structure are arranged on the same side of the stack. The first-level identifier structure and each second-level identifier structure being arranged on the same side of the stack can specifically mean that the first-level identifier structure and each second-level identifier structure are arranged in a portion of the stack that is closer to the same side of the stack. For example, in an embodiment, the first-level identifier structure and each second-level identifier structure can be arranged in an upper portion of the stack that is closer to the upper side of the stack. Because each opening in the layer structure above the first-level identifier structure has the same or similar size and the same lateral position as the first-level identifier structure, the vertical projection areas of the plurality of second-level identifier structures at least partially overlap (or even substantially completely overlap) with each other. This arrangement allows the optical reading device and the identifier generating device to be arranged in relatively fixed positions on the same side of the stack. This eliminates the need for significant displacement when reading the first-level identifier structures on different stacks or different layers of the stack and generating the second-level identifier structures, making it easier and faster to read the first-level and second-level identifier structures from the same side of the stack.

[0035] In some optional embodiments, at least one of the at least one second-level identifier structures is arranged in the same layer structure of the stack as the first-level identifier structure, and the other of the at least one second-level identifier structure is arranged in an upper layer structure of the stack than the layer structure where the first-level identifier structure is located.

[0036] In some optional embodiments, the first-level identifier structure is formed by a photolithography etching process; and / or the second-level identifier structure is formed by a laser drilling process. In an embodiment, the first-level identifier structure can be formed by photolithography etching of the stacked material. Since the component carrier products all need to undergo core exposure and etching processes, generating the first-level identifier structure by etching can ensure that all products are formed with optically readable patterns that can be used for traceability. The second-level identifier structure can be formed by forming vias, especially blind holes, in the layer structure using a laser drilling process. In the production process of component carrier structures such as PCB boards, laser drilling exists after the lamination process of each layer structure, and there are many other processes between the lamination process and the etching process. Therefore, using laser drilling to generate the second identifier structure can advantageously achieve traceability from the lamination process to the etching process.

[0037] In some optional embodiments, the vias formed by laser drilling in the second-level identifier structure have sloped sidewalls. The sloped sidewall design can increase the mechanical strength and stability of the material surrounding the vias. The sloped sidewalls also facilitate more uniform filling during manufacturing, particularly during electroplating. This helps improve adhesion between the filling material and the layer structure, thereby enhancing structural reliability.

[0038] In some optional embodiments, at least one major surface of the first-level identifier structure and / or the second-level identifier structure is defined by a stacked layer structure vertically adjacent to the corresponding first-level identifier structure and / or the second-level identifier structure, such that no portion of the corresponding first-level identifier structure and / or the second-level identifier structure extends into the adjacent stacked layer structure. This clear separation between the different identifier structures avoids potential optical and physical interference between the identifier structures, thereby improving the mechanical stability and independence of each.

[0039] In some optional embodiments, the first-level identifier structure and at least one second-level identifier structure are only arranged in at least one electrically conductive layer structure, and at least one main surface of the first-level identifier structure and / or the second-level identifier structure is defined by an electrically insulating layer structure vertically adjacent to the corresponding first-level identifier structure and / or the second-level identifier structure, so that no part of the corresponding first-level identifier structure and / or the second-level identifier structure extends into the adjacent electrically insulating layer structure.

[0040] In some optional embodiments, at least one electrically conductive layer structure disposed below each of the at least one second-level identifier structure and the first-level identifier structure is configured as a continuous metal layer.

[0041] In some optional embodiments, the plurality of electrically conductive layer structures disposed beneath each of the at least one second-level identifier structure and the first-level identifier structure are configured as a continuous metal layer.

[0042] The continuous metal layer can increase the metal content of the laminate and reduce the void volume within the laminate. This can have a positive impact on the mechanical stability and integrity of the component carrier structure, in particular, it can suppress undesirable phenomena such as warping and / or delamination.

[0043] In an embodiment, the component carrier structure includes a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier can be a laminate of the aforementioned electrically insulating layer structure and the electrically conductive layer structure, in particular a laminate formed by applying mechanical pressure and / or thermal energy. The aforementioned stack can provide a plate-like component carrier that can provide a large mounting surface for additional components while still being very thin and compact.

[0044] In one embodiment, the component carrier structure is shaped as a plate. This facilitates a compact design, wherein the component carrier still provides a large base for mounting components thereon. Furthermore, bare wafers, particularly as an example of embedded electronic components, can be easily embedded in thin plate elements such as printed circuit boards due to their small thickness.

[0045] In an embodiment, the component carrier structure or a preform thereof is configured as one of a printed circuit board, a substrate (particularly an IC substrate) and an interposer.

[0046] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and / or providing heat. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may comprise resin and / or glass fibres, so-called prepregs or FR4 materials. The various electrically conductive layer structures may be connected to one another in the desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling, and by partially or completely filling the holes with electrically conductive material, in particular copper, thereby forming vias such as through-hole connections. In addition to being able to embed one or more components in the printed circuit board, the printed circuit board is typically configured to accommodate one or more components on one or two opposite surfaces of the plate-like printed circuit board. They may be connected to the respective main surfaces by soldering. The dielectric part of the PCB may consist of a resin with reinforcing fibres, such as glass fibres.

[0047] In the context of this application, the term "substrate" can particularly refer to a small component carrier. A substrate can be a relatively small component carrier associated with a PCB, on which one or more components can be mounted, and can serve as a connecting medium between one or more chips and another PCB. For example, a substrate can have substantially the same size as the components (particularly electronic components) to be mounted thereon (for example in the case of a chip-scale package (CSP)). More particularly, a substrate can be understood as a carrier for electrical connections or electrical networks and a component carrier comparable to a printed circuit board (PCB), but with a relatively high density of horizontal and / or vertically arranged connectors. Horizontal connectors are, for example, electrically conductive paths, while vertical connectors can be, for example, drilled holes. These horizontal connectors and / or vertical connectors are arranged within the substrate and can be used to provide electrical, thermal and / or mechanical connections between a housing component or a housingless component (such as a bare wafer), in particular, of an IC chip and a printed circuit board or an intermediate printed circuit board. Therefore, the term "substrate" also includes "IC substrates". The dielectric portion of the substrate may consist of a resin with reinforcing particles such as reinforcing spheres, particularly glass spheres.

[0048] The substrate or interposer may include or consist of at least a layer of the following substances: glass; silicon and / or a photosensitive or dry-etchable organic material, such as an epoxy-based laminate material (e.g., an epoxy-based laminate film); or a polymer compound (the polymer compound may or may not include photosensitive and / or heat-sensitive molecules).

[0049] In an embodiment, at least one electrically insulating layer structure comprises at least one of the following: a resin (e.g., a reinforced or non-reinforced resin, such as an epoxy resin or a bismaleimide-triazine resin), a cyanate resin, a polyphenylene derivative, a glass (in particular, glass fiber, multilayer glass, a glass-like material), a prepreg material (e.g., FR-4 or FR-5), a polyimide, a polyamide, a liquid crystal polymer (LCP), an epoxy-based laminate film, polytetrafluoroethylene (PTFE, Teflon), a ceramic, and a metal oxide. Reinforcement structures such as meshes, fibers, or spheres made of, for example, glass (multilayer glass) may also be used. Although prepregs, in particular FR4, are generally preferred for rigid PCBs, other materials, in particular epoxy-based laminate films or photoimageable dielectric materials may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins, low-temperature co-fired ceramics (LTCC), or other low, very low, or ultra-low DK materials may be applied in the component carrier as the electrically insulating layer structure.

[0050] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following substances: copper, aluminum, nickel, silver, gold, palladium and tungsten. Although copper is generally preferred, other materials or coated versions thereof are also possible, in particular coated with superconducting materials such as graphene.

[0051] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The features and advantages of the embodiments of the present application will become more readily understood through the following description with reference to the accompanying drawings, which are not drawn to scale and in which some features are exaggerated or minimized to show details of particular components.

[0053] Figure 1 A schematic perspective structural diagram of a component carrier structure 100 according to an exemplary embodiment of the present application is provided.

[0054] Figure 2 A schematic cross-sectional view of a component carrier structure 100 according to an exemplary embodiment of the present application is provided.

[0055] Figure 3 Provided Figure 2 : This is an enlarged schematic cross-sectional view of part A shown in FIG. DETAILED DESCRIPTION

[0056] The present application will be described in detail below with reference to the accompanying drawings by way of exemplary embodiments of the present application. It should be noted that the following detailed description of the present application is for illustrative purposes only and is not intended to limit the present application. In addition, the same reference numerals are used throughout the various drawings to represent the same components.

[0057] It should also be pointed out that, for the sake of clarity, not all features of an actual specific embodiment are described and shown in the specification and drawings. In addition, in order to avoid unnecessary details that obscure the technical solutions focused on by this application, only the arrangement structures closely related to the technical content of this application are described and shown in the specification and drawings, while other details that are not closely related to the technical content of this application and are known to those skilled in the art are omitted.

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] In this application document, terms such as "upper," "lower," "outer," and "inner" used to describe directions are for descriptive purposes only and should not be construed as limiting. Furthermore, although this application has been described with reference to exemplary embodiments, it should be understood that this application is not limited to the specific embodiments described and illustrated in detail herein. Those skilled in the art may make various modifications to the exemplary embodiments without departing from the scope of the claims of this application.

[0061] Figure 1 A schematic perspective structural diagram of a component carrier structure 100 according to an exemplary embodiment of the present application is provided. Figure 2 A schematic cross-sectional view of a component carrier structure 100 according to an exemplary embodiment of the present application is provided. Figure 3 Provided Figure 2 : is an enlarged schematic cross-sectional view of part A shown in .

[0062] Reference Figure 1, a component carrier structure 100 according to an embodiment of the present application comprises a stack 102 having at least one electrically conductive layer structure 104 and at least one electrically insulating layer structure 106. Figure 1 In the embodiment, “104 / 106” means that the layer structure indicated with the identifier structure may be the electrically conductive layer structure 104 or the electrically insulating layer structure 106, or may include both the electrically conductive layer structure 104 and the electrically insulating layer structure 106, and in the actual construction of the stack 102, Figure 1 Additional electrically conductive and / or electrically insulating layer structures may be disposed between any two adjacent layer structures shown in FIG. A first-level identifier structure 108 is disposed within stack 102, particularly deeper within stack 102. At least one second-level identifier structure 110 is disposed on at least one exposed surface of at least one layer structure in stack 102 (electrically conductive layer structure 104 and / or electrically insulating layer structure 106). For example, in some embodiments, second-level identifier structure 110 may be formed only on the exposed surface of the topmost layer structure of stack 102. In other embodiments, second-level identifier structure 110 may be present not only on the exposed surface of the topmost layer structure of stack 102 but also on the surface of at least one layer structure in other layers of stack 102 (e.g., those located within the stack). First-level identifier structure 108 is laterally spaced apart from all second-level identifier structures 110. The placement of the first level identifier structure 108 deeper within the stack 102 may specifically mean that the first level identifier structure 108 is placed at a greater distance from the topmost major surface of the stack within the interior of the stack relative to at least a portion of the second level identifier structure 110. Both the first level identifier structure 108 and the second level identifier structure 110 are only accessible from one side of the stack 102 (e.g., Figure 1 and Figure 2 Those shown in FIG can only be read from the upper side of the stack 102).

[0063] In an embodiment, the first-level identifier structure 108 and the second-level identifier structure 110 carry coded information, for example, an optically readable pattern of the identifier structures, in particular a data matrix code. Optically reading the coded information from the first-level identifier structure 108 and / or the second-level identifier structure 110 enables identification and / or tracking of the component-carrier structure 100 or its individual layer structures (the electrically insulating layer structure 106 and / or the electrically conductive layer structure 104). For example, by scanning the optically readable pattern of the identifier structures, an optical reading device can link to a specific data set in a database and retrieve information of interest from this data set.

[0064] Tracking the component carrier structure 110 based on the information optically read from the first-level identifier structure 108 and / or the second-level identifier structure 110 allows tracing back each individual component carrier structure 100 or its individual layer structures within specific time intervals, for example during the entire manufacturing process of each individual component carrier structure 100 or during its life cycle.

[0065] In an embodiment of the present application, the first-level identifier structure 108 and / or the second-level identifier structure 110 may be formed integrally with the stack 102. For example, forming the identifier structure in and / or on the stack 102 may be by patterning one or more electrically conductive layers (e.g., copper foil) and / or one or more electrically insulating layers (e.g., resin sheets, optionally including reinforcing particles) to obtain an overall electrically conductive-insulating pattern constituting the identifier structure. For another example, the first-level identifier structure 108 may be formed by photolithographically etching the stack material, and the second-level identifier structure 110 may be formed by forming vias 117 in the stack layer structure (e.g., by laser drilling or mechanical drilling processes, such as Figure 3 For another example, the second-level identifier structure 110 formed by laser or mechanical drilling may also be partially formed in the electrically insulating layer structure, that is, the lower surface of the second identifier structure 110 may exist in the electrically insulating layer structure, but the second identifier structure 110 does not completely penetrate the electrically insulating layer structure. The first-level identifier structure 108 formed by the photolithography etching process and the second-level identifier structure 110 formed by the drilling process both constitute part of the corresponding stack layer structure.

[0066] Additionally or alternatively, the electrically conductive layer structure 104 and / or the electrically insulating layer structure 106 may partially form an optically readable pattern of the identifier structure. For example, the identifier structure may be formed by a via formed in the layer structure and a filler block filled in the via. In particular, when the size (e.g., longitudinal height, in particular, the height protruding from the layer structure) and / or the color of the filler block form part of the optically readable pattern of the identifier structure, the layer structure itself only exists as part of the optically readable pattern of the identifier structure.

[0067] However, it is understood that the first-level identifier structure 108 and / or the second-level identifier structure 110 may also be separate identifier structures (such as inlays) that are assembled or inserted into the stack 102 .

[0068] In some embodiments, the component carrier structure 100 includes a plurality of second-level identifier structures 110. The plurality of second-level identifier structures 110 are arranged on different layer structures of the stack 102. In particular, each second-level identifier structure 110 is arranged on a different layer structure. The vertical projection areas of the plurality of second-level identifier structures 110 may at least partially overlap. For example, in some embodiments, Figure 1 As shown, multiple second-level identifier structures 110 are arranged on the corresponding multiple layer structures, with the multiple second-level identifier structures 110 being vertically spaced apart from each other and substantially aligned with each other in the transverse direction. In this case, when the stack 102 is viewed vertically (perpendicular to the planar surface of the stack) from the exterior of the stack 102, the second-level identifier structures 110 of the stack 102 will substantially completely overlap. In other embodiments, the multiple second-level identifier structures 110 are arranged on the corresponding multiple layer structures, with the multiple second-level identifier structures 110 being vertically spaced apart from each other and laterally offset from each other (not shown). In this case, when the stack 102 is viewed vertically from the exterior of the stack 102, the second-level identifier structures 110 of the stack 102 will partially overlap. It will be appreciated that in other embodiments, the vertically projected areas of the multiple second-level identifier structures 110 arranged on the multiple layer structures may not overlap at all, i.e., any two of the multiple second-level identifier structures 110 may be spaced apart laterally by a significant distance.

[0069] In the stack 102, a portion 114 of the layer structure (particularly a plurality of layer structures) located vertically above the first-level identifier structure 108 may be configured to allow the first-level identifier structure 108 to be directly optically read through the portion 114. An optical reading device (such as an X-ray camera 132) can directly access the first-level identifier structure 108 through the portion 114 of the layer structure, even if the first-level identifier structure 108 is located deep inside the stack 102.

[0070] The portion 114 may include at least one opening 116 (also referred to as an optical detection opening) formed in at least one layer structure. The lateral coverage of the opening 116 matches the lateral coverage of the first-level identifier structure 108. For example, the opening 116 may have substantially the same size and substantially the same lateral position as the first-level identifier structure 108, so that the shape of the opening 116 substantially completely corresponds to the shape of the first-level identifier structure 108 in the viewing direction of the optical reading device. Figure 2As shown in the example, the lateral dimension of the first-level identifier structure 103 may be, for example, 4.45 mm, and the lateral dimension of the opening 116 may be, for example, 4.8 mm. The lateral dimension of the second-level identifier structure 110 may be substantially the same as that of the first-level identifier structure 108. However, it is understood that the opening 116 may also be larger than the first-level identifier structure 108 and have a vertical projection area that completely covers the first-level identifier structure 108.

[0071] In some embodiments, only some of the layer structures included in the portion 114 are provided with openings 116 (not shown). In some applications, a partial provision of openings 116 in the portion 114 is sufficient to enable reading of the first-level identifier structure 108 .

[0072] In other embodiments, all the layer structures included in the portion 114 are provided with openings 116 (e.g., Figure 2 (as shown). Two or more openings 116 can be laterally aligned with one another, or more precisely, two or more openings 116 can be vertically aligned and not laterally offset from one another, so as to collectively form a channel 118 extending from the exposed surface of the stack 102 to the first-level identifier structure 108. Channel 118 can also be referred to as an optical inspection channel because channel 118 allows optical inspection of the first-level identifier structure 108, which is at least partially laterally aligned with the channel and vertically located deeper within the stack 102. It will be appreciated that at least some of the two or more openings 116 can also be laterally offset relative to one another but partially overlap, so that the two or more openings 116 collectively form a channel 118 extending from the exposed surface of the stack 102 to the first-level identifier structure 108. The optical inspection channel can allow an optical reader to directly access the first-level identifier structure 108 located deeper within the stack 102, thereby obtaining information about the layer structure or component-carrier structure 100 associated with the first-level identifier structure 108.

[0073] The opening 116 and / or the channel 118 may be at least partially filled with a filler block, such as an electrically insulating block, in particular a resin block. In some embodiments, the sidewalls defining the opening 116 and / or the channel 118 may be inclined sidewalls. The opening 116 and / or the channel 118, at least partially filled with a filler block, still allows an optical reader to access the first-level identifier structure 108, preferably directly. The arrangement of the electrically insulating block in the opening 116 and / or the channel 118 may allow optical detection of the first-level identifier structure 108 located deeper in the stack 102 through the opening 116 and / or the channel 118, without compromising the electrical reliability of the component carrier structure 100.

[0074] In the embodiments of the present application, the consistency / inconsistency between the optically readable patterns of the first-level identifier structure 108 and each second-level identifier structure 110 can be flexibly determined as required.

[0075] In some embodiments, the optically readable pattern of the first-level identifier structure 110 is identical to the optically readable pattern of each second-level identifier structure 110. In one embodiment, the first-level identifier structure 108 is disposed relatively deep within the stack 102 and can be directly read by an optical reader from outside the stack 102. Thus, during the manufacturing process of the stack 102, when a new layer structure is stacked above the location of the first-level identifier structure 108, the first-level identifier structure 108 can be directly read by an optical reader (e.g., an X-ray camera 132). The read information can then be transmitted to a device (e.g., a laser drilling device) to be used to form the second-level identifier structure 110 on the newly exposed layer structure, allowing the latter to easily manufacture the second-level identifier structure 110 on the newly exposed layer structure based on the received information. The second-level identifier structure 110 can be optically detected without the need for an X-ray recognition device. For example, the second-level identifier structure 110 can be recognized by an optical scanner 131.

[0076] In some embodiments, the optically readable pattern of the first-level identifier structure 108 is different from the optically readable pattern of any of the second-level identifier structures 110, while at least a portion of the optically readable pattern of each of the second-level identifier structures 110 may be the same. In some embodiments, the optically readable pattern of the first-level identifier structure 108 is different from the optically readable pattern of any of the second-level identifier structures 110, and the optically readable pattern of each of the second-level identifier structures 110 is also different. In some embodiments, the optically readable pattern of the first-level identifier structure 108 is the same as a portion of the optically readable pattern of the second-level identifier structure 110.

[0077] In some embodiments, the optically readable pattern of the identifier structure varies according to the layer structure. In other words, the optically readable pattern of the identifier structure provided in one of the stack layers is different from the optically readable pattern of the identifier structure provided in the other stack layer structure.

[0078] The optically readable pattern of at least part of the identifier structure varies depending on the layer structure, enabling information tracing back to the individual layer structure of interest. In particular, a specific identifier structure can be provided on the layer structure of interest as needed, so that information about the corresponding layer structure, particularly information about the manufacturing process of the layer structure, is reflected in the optically readable pattern of the corresponding identifier structure.

[0079] In an embodiment, the first level identifier structure 108 and each second level identifier structure 110 may be arranged on a portion of the stack 102 closer to the same side thereof. Figure 2 As shown, the first level identifier structure 108 and the plurality of second level identifier structures 110 are both arranged in a portion of the stack 102 closer to the upper side of the stack 102 (which may also be referred to as the upper portion). This arrangement makes it easier to identify the stack 102 from the same side (e.g., Figure 2 The first-level identifier structure 108 and the second-level identifier structure 110 are read (the upper side in FIG).

[0080] In an embodiment, at least one of the two or more second-level identifier structures 110 may be arranged in the same layer structure of the stack 102 as the first-level identifier structure 108, while the other second-level identifier structures 110 may be arranged in an upper layer structure of the stack 102 than the layer structure where the first-level identifier structure 108 is located. Figure 2 One of the plurality of second-level identifier structures 110 is arranged in the same layer structure as the first-level identifier structure 108 , while the other second-level identifier structures 110 are arranged in a layer structure that is higher up.

[0081] In an embodiment, at least one major surface 122 of the first level identifier structure 108 and / or the second level identifier structure 110 is defined by a stack layer structure vertically adjacent to the corresponding first level identifier structure 108 and / or the second level identifier structure 110, such that no portion of the corresponding first level identifier structure 108 and / or the second level identifier structure 110 extends into the adjacent stack layer structure. Figure 2 As shown, a first-level identifier structure 108 and a plurality of second-level identifier structures 110 are arranged in a corresponding plurality of electrically conductive layer structures 104. The major surfaces 122 of the first-level identifier structure 108 and the second-level identifier structure 110 are bounded by the electrically insulating layer structures 106 vertically adjacent to the corresponding identifier structure, such that no portion of the corresponding identifier structure extends into the adjacent electrically insulating layer structure 106.

[0082] In an embodiment, the first level identifier structure 108 and each second level identifier structure 110 are located in an area of ​​the component carrier structure 110 other than the functional area to avoid adversely affecting the electrical characteristics of the component carrier structure 110 .

[0083] In an embodiment, Figure 2 As shown, at least one electrically conductive layer structure 104 disposed below each of the second-level identifier structure 110 and the first-level identifier structure 108 may be configured as a continuous metal layer. Alternatively, a plurality of electrically conductive layer structures 104 disposed below each of the second-level identifier structure 110 and the first-level identifier structure 108 may be configured as a continuous metal layer (e.g., Figure 2 The area indicated by 130 in FIG. 1 includes a plurality of continuous electrically conductive layer structures).

[0084] Although the present application has been described with reference to exemplary embodiments, it should be understood that the present application is not limited to the specific embodiments described and illustrated in detail herein. Those skilled in the art may make various changes to the exemplary embodiments without departing from the scope defined by the claims of the present application.

[0085] The features mentioned and / or illustrated in the above description of the exemplary embodiments of the present application may be incorporated into one or more other embodiments in the same or similar manner, combined with features in other embodiments, or substituted for corresponding features in other embodiments. The technical solutions obtained by such combination or substitution shall also be deemed to be included in the scope of protection of the present application.

Claims

1. A component carrier structure (100), characterized in that The component carrier structure (100) comprises: a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); a first level identifier structure (108) disposed in the stack (102); and at least one second-level identifier structure (110) disposed at least at least one exposed surface (112) of at least one of the layer structures of the stack (102); The first-level identifier structure (108) and the at least one second-level identifier structure (110) are laterally spaced apart from each other, and both the first-level identifier structure (108) and the at least one second-level identifier structure (110) are readable only from one side of the stack (102).

2. The component carrier structure (100) according to claim 1, characterized in that The component carrier structure (100) comprises a plurality of second-level identifier structures (110), the projection areas of the plurality of second-level identifier structures (110) in the vertical direction at least partially overlapping with each other.

3. The component carrier structure (100) according to claim 1, characterized in that The portion (114) of the layer structure of the stack (102) vertically positioned above the first-level identifier structure (108) is configured to allow the first-level identifier structure (108) to be read through the portion (114).

4. The component carrier structure (100) according to claim 3, characterized in that The portion (114) of the at least one layer structure of the stack (102) vertically positioned above the first-level identifier structure (108) includes at least one opening (116) formed in the at least one layer structure.

5. The component carrier structure (100) according to claim 4, characterized in that A plurality of the openings (116) are laterally aligned with one another to collectively form a channel (118) extending from the exposed surface of the stack (102) to the first level identifier structure (108); or At least some of the plurality of openings (116) are laterally offset relative to one another but partially overlap such that the plurality of openings (116) collectively form a channel (118) extending from the exposed surface of the stack (102) to the first level identifier structure (108).

6. The component carrier structure (100) according to claim 5, characterized in that The passage (118) is at least partially filled with an electrically insulating block that enables the first-level identifier structure (108) to be read from outside the stack (102) through the passage (118).

7. The component carrier structure (100) according to claim 4, characterized in that The opening (116) is at least partially filled with an electrically insulating block that enables the first-level identifier structure (108) to be read from outside the stack (102) through the opening (116).

8. The component carrier structure (100) according to claim 6 or 7, characterized in that The electrical insulating block is a resin block.

9. The component carrier structure (100) according to claim 4, characterized in that The lateral coverage of the opening (116) matches the lateral coverage of the first-level identifier structure (108).

10. The component carrier structure (100) according to claim 1, characterized in that The first-level identifier structure (108) and / or the second-level identifier structure (110) are integrally formed with the stack (102).

11. The component carrier structure (100) according to claim 1, characterized in that The optically readable patterns of the first-level identifier structure (108) and the at least one second-level identifier structure (110) are different from each other; and / or The optically readable patterns of the second-level identifier structures (110) are different from each other.

12. The component carrier structure (100) according to claim 1, characterized in that The optically readable pattern of the first level identifier structure (108) and / or the second level identifier structure (110) disposed in one of the stack layer structures is different from the optically readable pattern of the first level identifier structure (108) and / or the second level identifier structure (110) disposed in the other stack layer structure.

13. The component carrier structure (100) according to claim 1, characterized in that The component carrier structure (100) comprises a first-level identifier structure (108) and / or a second-level identifier structure (110) that is different from another first-level identifier structure (108) and / or another second-level identifier structure (110) comprised by another component carrier structure (100).

14. The component carrier structure (100) according to claim 1, characterized in that The optically readable pattern formed by the first-level identifier structure (108) is identical to the optically readable pattern formed by each of the second-level identifier structures (110).

15. The component carrier structure (100) according to claim 1, characterized in that At least two of the at least one second-level identifier structure (110) and the first-level identifier structure (108) are formed with the same optically readable pattern.

16. The component carrier structure (100) according to claim 1, characterized in that The electrically conductive layer structure (104) at least partially forms an optically readable pattern of the first-level identifier structure (108) and / or the second-level identifier structure (110).

17. The component carrier structure (100) according to claim 1, characterized in that The first-level identifier structure (108) and at least one second-level identifier structure (110) are both located in an area of ​​the component-carrier structure (100) other than the functional area.

18. The component carrier structure (100) according to claim 1, characterized in that The first-level identifier structure (108) and at least one second-level identifier structure (110) are arranged on a same side of the stack (102).

19. The component carrier structure (100) according to claim 1, characterized in that At least one of the at least one second-level identifier structure (110) is arranged in the same layer structure of the stack (102) as the first-level identifier structure (108), and the other of the at least one second-level identifier structure (110) is arranged in an upper layer structure of the stack (102) than the layer structure where the first-level identifier structure (108) is located.

20. The component carrier structure (100) according to claim 1, characterized in that The first level identifier structure (108) is formed by a photolithographic etching process; and / or The second level identifier structure (110) is formed by a laser drilling process.

21. The component carrier structure (100) according to claim 20, characterized in that The vias in the second-level identifier structure (110) formed by a laser drilling process have inclined sidewalls.

22. The component carrier structure (100) according to claim 1, characterized in that At least one major surface (122) of the first-level identifier structure (108) and / or the second-level identifier structure (110) is defined by a stack layer structure vertically adjacent to the corresponding first-level identifier structure (108) and / or the second-level identifier structure (110), such that no portion of the corresponding first-level identifier structure (108) and / or the second-level identifier structure (110) extends into the adjacent stack layer structure.

23. The component carrier structure (100) according to claim 22, characterized in that The first-level identifier structure (108) and at least one second-level identifier structure (110) are arranged only in at least one of the electrically conductive layer structures (104), at least one main surface (122) of the first-level identifier structure (108) and / or the second-level identifier structure (110) being delimited by the electrically insulating layer structure (106) vertically adjacent to the respective first-level identifier structure (108) and / or the second-level identifier structure (110), such that no part of the respective first-level identifier structure (108) and / or the second-level identifier structure (110) extends into the adjacent electrically insulating layer structure (106).

24. The component carrier structure (100) according to claim 1, characterized in that At least one electrically conductive layer structure (104) arranged below each of the at least one second-level identifier structure (110) and the first-level identifier structure (108) is configured as a continuous metal layer.

25. The component carrier structure (100) according to claim 1, characterized in that A plurality of electrically conductive layer structures (104) arranged below each of the at least one second-level identifier structure (110) and the first-level identifier structure (108) are configured as a continuous metal layer.

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