Power MOS device

Abstract

The utility model discloses a power MOS (Metal Oxide Semiconductor) device, which is characterized in that a first deep groove, a second deep groove and a shallow groove extend into an N-type epitaxial layer from the upper surface of a P-type well region, the shallow groove is positioned between the first deep groove and the second deep groove, and the depths of the first deep groove and the second deep groove are greater than the depth of the shallow groove; the inner walls of the first deep trench and the second deep trench are respectively provided with a gate silicon oxide layer; first conductive polycrystalline silicon and second conductive polycrystalline silicon are respectively positioned in the first deep trench and the second deep trench; a first N-type source region is arranged on the upper portion of the P-type well region and located on the periphery of the first deep groove, a second N-type source region is arranged on the upper portion of the P-type well region and located on the periphery of the second deep groove, the shallow groove is located between the first N-type source region and the second N-type source region, and a metal cylinder is arranged in the shallow groove. According to the power MOS device, the turn-on voltage of the device is effectively reduced, the reverse recovery time of the device is shortened, and the power loss of the device in a high-frequency use state is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of MOSFET devices, in particular to a power MOS device. Background Art

[0002] Power MOS devices feature high integration, low on-resistance, fast switching speeds, and minimal switching losses, making them widely used in various power management and switching applications. With industrial development, demands for the power consumption and conversion efficiency of power MOS devices are becoming increasingly stringent. However, existing power MOS devices suffer from high turn-on voltages, long reverse recovery times, and significant power losses. Summary of the Invention

[0003] The purpose of the utility model is to provide a power MOS device, which effectively reduces the device turn-on voltage, shortens the reverse recovery time of the device, and reduces the power loss of the device under high-frequency use.

[0004] To achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: a power MOS device, comprising a silicon substrate having an N-type epitaxial layer and an N-type heavily doped layer, wherein the N-type heavily doped layer is located at the bottom of the silicon substrate, and an N-type epitaxial layer located above the N-type heavily doped layer is located in the middle and upper parts of the silicon substrate, and a P-type well region is provided in the upper part of the N-type epitaxial layer;

[0005] A first deep trench, a second deep trench, and a shallow trench extend from the upper surface of the P-type well region into the N-type epitaxial layer, the shallow trench being located between the first deep trench and the second deep trench, the depths of the first deep trench and the second deep trench being greater than the depth of the shallow trench; a gate silicon oxide layer is provided on the inner wall of each of the first deep trench and the second deep trench, and a first conductive polysilicon and a second conductive polysilicon are located in the first deep trench and the second deep trench, respectively;

[0006] A first N-type source region is provided above the P-type well region and around the first deep trench, a second N-type source region is provided above the P-type well region and around the second deep trench, the shallow trench is located between the first N-type source region and the second N-type source region, and a metal column is provided in the shallow trench;

[0007] A first insulating dielectric layer and a second insulating dielectric layer are respectively covered on the first conductive polysilicon and the second conductive polysilicon, an upper metal electrode layer is located on the first insulating dielectric layer, the second insulating dielectric layer, the first N-type source region, the second N-type source region and the metal pillar, and the surface of the N-type heavily doped layer opposite to the N-type epitaxial layer has a lower metal electrode layer.

[0008] The further improved scheme in the above technical scheme is as follows:

[0009] 1. In the above solution, the width of the shallow trench is smaller than the width of the first deep trench and the second deep trench.

[0010] 2. In the above solution, the depth ratio of the first deep trench, the second deep trench and the shallow trench is 10:6-8.

[0011] 3. In the above solution, the first insulating dielectric layer extends in the planar direction to above the inner edge of the first N-type source region.

[0012] 4. In the above solution, the second insulating dielectric layer extends in the planar direction to above the inner edge of the second N-type source region.

[0013] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0014] The utility model discloses a power MOS device, wherein a first deep trench, a second deep trench, and a shallow trench extend from the upper surface of the P-type well region into the N-type epitaxial layer. The shallow trench is located between the first deep trench and the second deep trench. The depths of the first deep trench and the second deep trench are greater than the depth of the shallow trench. The shallow trench is located between the first N-type source region and the second N-type source region. A metal pillar is provided in the shallow trench. An upper metal electrode layer is located on the first N-type source region, the second N-type source region, and the metal pillar. The metal pillar is connected in parallel with the first N-type source region and the second N-type source region. The metal pillar forms a Schottky contact with the N-type epitaxial layer, thereby effectively reducing the device turn-on voltage, shortening the reverse recovery time of the device, and reducing the power loss of the device under high-frequency use. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Attachment Figure 1 This is a schematic structural diagram of the power MOS device of the utility model.

[0016] In the above figures: 1. N-type epitaxial layer; 2. N-type heavily doped layer; 3. Silicon substrate; 4. P-type well region; 51. First deep trench; 52. Second deep trench; 6. Shallow trench; 7. Gate silicon oxide layer; 81. First conductive polysilicon; 82. Second conductive polysilicon; 91. First N-type source region; 92. First N-type source region; 10. Metal pillar; 111. First insulating dielectric layer; 112. Second insulating dielectric layer; 12. Upper metal electrode layer; 13. Lower metal electrode layer. DETAILED DESCRIPTION

[0017] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.

[0018] Embodiment 1: A power MOS device includes a silicon substrate 3 having an N-type epitaxial layer 1 and an N-type heavily doped layer 2, wherein the N-type heavily doped layer 2 is located at the bottom of the silicon substrate 3, and the N-type epitaxial layer 1 located above the N-type heavily doped layer 2 is located in the middle and upper portions of the silicon substrate 3, and a P-type well region 4 is formed in the upper portion of the N-type epitaxial layer 1;

[0019] A first deep trench 51, a second deep trench 52, and a shallow trench 6 extend from the upper surface of the P-type well region 4 into the N-type epitaxial layer 1. The shallow trench 6 is located between the first deep trench 51 and the second deep trench 52. The depths of the first deep trench 51 and the second deep trench 52 are greater than the depth of the shallow trench 6. The inner walls of each of the first deep trench 51 and the second deep trench 52 are provided with a gate silicon oxide layer 7. A first conductive polysilicon 81 and a second conductive polysilicon 82 are located in the first deep trench 51 and the second deep trench 52, respectively.

[0020] A first N-type source region 91 is provided above the P-type well region 4 and around the first deep trench 51. A second N-type source region 92 is provided above the P-type well region 4 and around the second deep trench 52. The shallow trench 6 is located between the first N-type source region 91 and the second N-type source region 92. A metal pillar 10 is provided in the shallow trench 6.

[0021] A first insulating dielectric layer 111 and a second insulating dielectric layer 112 are respectively covered on the first conductive polysilicon 81 and the second conductive polysilicon 82. An upper metal electrode layer 12 is located on the first insulating dielectric layer 111, the second insulating dielectric layer 112, the first N-type source region 91, the second N-type source region 92 and the metal pillar 10. The surface of the N-type heavily doped layer 2 opposite to the N-type epitaxial layer 1 has a lower metal electrode layer 13.

[0022] The depth ratio of the first deep trench 51 , the second deep trench 52 and the shallow trench 6 is 10:6.4.

[0023] The first insulating dielectric layer 111 extends in a planar direction to above the inner edge of the first N-type source region 91 .

[0024] The second insulating dielectric layer 112 extends in the planar direction to above the inner edge of the second N-type source region 92 .

[0025] Embodiment 2: A power MOS device includes a silicon substrate 3 having an N-type epitaxial layer 1 and an N-type heavily doped layer 2, wherein the N-type heavily doped layer 2 is located at the bottom of the silicon substrate 3, and the N-type epitaxial layer 1 located above the N-type heavily doped layer 2 is located in the middle and upper portions of the silicon substrate 3, wherein the upper portion of the N-type epitaxial layer 1 has a P-type well region 4;

[0026] A first deep trench 51, a second deep trench 52, and a shallow trench 6 extend from the upper surface of the P-type well region 4 into the N-type epitaxial layer 1. The shallow trench 6 is located between the first deep trench 51 and the second deep trench 52. The depths of the first deep trench 51 and the second deep trench 52 are greater than the depth of the shallow trench 6. The inner walls of each of the first deep trench 51 and the second deep trench 52 are provided with a gate silicon oxide layer 7. A first conductive polysilicon 81 and a second conductive polysilicon 82 are located in the first deep trench 51 and the second deep trench 52, respectively.

[0027] A first N-type source region 91 is provided above the P-type well region 4 and around the first deep trench 51. A second N-type source region 92 is provided above the P-type well region 4 and around the second deep trench 52. The shallow trench 6 is located between the first N-type source region 91 and the second N-type source region 92. A metal pillar 10 is provided in the shallow trench 6.

[0028] A first insulating dielectric layer 111 and a second insulating dielectric layer 112 are respectively covered on the first conductive polysilicon 81 and the second conductive polysilicon 82. An upper metal electrode layer 12 is located on the first insulating dielectric layer 111, the second insulating dielectric layer 112, the first N-type source region 91, the second N-type source region 92 and the metal pillar 10. The surface of the N-type heavily doped layer 2 opposite to the N-type epitaxial layer 1 has a lower metal electrode layer 13.

[0029] The width of the shallow trench 6 is smaller than the width of the first deep trench 51 and the second deep trench 52 .

[0030] The depth ratio of the first deep trench 51 , the second deep trench 52 and the shallow trench 6 is 10:7.2.

[0031] The first insulating dielectric layer 111 extends in a planar direction to above the inner edge of the first N-type source region 91 .

[0032] The second insulating dielectric layer 112 extends in the planar direction to above the inner edge of the second N-type source region 92 .

[0033] When using the above-mentioned power MOS device, its first deep trench, second deep trench, and shallow trench extend from the upper surface of the P-type well region into the N-type epitaxial layer. The shallow trench is located between the first deep trench and the second deep trench. The depths of the first deep trench and the second deep trench are greater than the depth of the shallow trench. The shallow trench is located between the first N-type source region and the second N-type source region. A metal pillar is provided in the shallow trench. The upper metal electrode layer is located on the first N-type source region, the second N-type source region, and the metal pillar. The metal pillar is connected in parallel with the first N-type source region and the second N-type source region. The metal pillar forms a Schottky contact with the N-type epitaxial layer, effectively reducing the device turn-on voltage, shortening the reverse recovery time of the device, and reducing the power loss of the device under high-frequency use.

[0034] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.

Claims

1. A power MOS device, characterized in that: The invention comprises a silicon substrate (3) having an N-type epitaxial layer (1) and an N-type heavily doped layer (2), wherein the N-type heavily doped layer (2) is located at the bottom of the silicon substrate (3), the N-type epitaxial layer (1) located above the N-type heavily doped layer (2) is located in the middle and upper parts of the silicon substrate (3), and the upper part of the N-type epitaxial layer (1) has a P-type well region (4); A first deep trench (51), a second deep trench (52) and a shallow trench (6) extend from the upper surface of the P-type well region (4) to the N-type epitaxial layer (1); the shallow trench (6) is located between the first deep trench (51) and the second deep trench (52); the depths of the first deep trench (51) and the second deep trench (52) are greater than the depth of the shallow trench (6); the inner walls of each of the first deep trench (51) and the second deep trench (52) are provided with a gate silicon oxide layer (7); a first conductive polysilicon (81) and a second conductive polysilicon (82) are located in the first deep trench (51) and the second deep trench (52), respectively; A first N-type source region (91) is provided on the upper portion of the P-type well region (4) and located around the first deep trench (51); a second N-type source region (92) is provided on the upper portion of the P-type well region (4) and located around the second deep trench (52); the shallow trench (6) is located between the first N-type source region (91) and the second N-type source region (92); and a metal column (10) is provided in the shallow trench (6); A first insulating dielectric layer (111) and a second insulating dielectric layer (112) are respectively covered on the first conductive polysilicon (81) and the second conductive polysilicon (82); an upper metal electrode layer (12) is located on the first insulating dielectric layer (111), the second insulating dielectric layer (112), the first N-type source region (91), the second N-type source region (92) and the metal column (10); and a lower metal electrode layer (13) is provided on the surface of the N-type heavily doped layer (2) opposite to the N-type epitaxial layer (1).

2. The power MOS device according to claim 1, wherein: The width of the shallow groove (6) is smaller than the width of the first deep groove (51) and the second deep groove (52).

3. The power MOS device according to claim 1, wherein: The depth ratio of the first deep groove (51), the second deep groove (52) and the shallow groove (6) is 10:6-8.

4. The power MOS device according to claim 1, wherein: The first insulating dielectric layer (111) extends in a planar direction to above the inner edge of the first N-type source region (91).

5. The power MOS device according to claim 1, wherein: The second insulating dielectric layer (112) extends in a planar direction to above the inner edge of the second N-type source region (92).

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