Semiconductor device structure and image sensor
By introducing a detection protection structure surrounding the chip area into the semiconductor device structure, the problem of mechanical loss and cutting yield during the cutting process is solved, and higher cutting yield and imaging quality are achieved.
Patent Information
- Application Number
- CN202422029845.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-08-20
AI Technical Summary
During the manufacturing process of semiconductor devices, cutting operations can easily lead to mechanical losses in the effective area of the chip and the cutting yield decrease, and cutting debris may be misjudged as unqualified products, affecting the cutting yield.
The detection protection structure is introduced into the semiconductor device structure, and is arranged around the chip area to detect and prevent cutting debris from entering the protection area. The detection protection structure reduces the extension of cutting cracks and reduces the risk of mechanical damage and water vapor intrusion.
It effectively reduces the loss of cutting yield, reduces the risk of mechanical damage and water vapor invasion, and improves the yield and imaging quality of cutting.
Smart Images
Figure CN223297968U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device structure and an image sensor. Background Art
[0002] With the development of semiconductor technology, image sensors have been widely used in various fields requiring digital imaging. Based on their operating principles and physical architecture, image sensors can generally be divided into two categories: charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors (CIS). CMOS image sensors are increasingly widely used due to their low power consumption, low cost, and compatibility with CMOS processes.
[0003] The primary component of a CMOS image sensor is the sensor chip. During manufacturing, multiple sensor chips are cut from a single substrate. Cutting and other mechanical operations can easily cause mechanical damage to the chip's active area. Furthermore, any chip debris that lands on the chip's edges or functional areas will be visually inspected as defective, resulting in a decrease in cutting yield. Utility Model Content
[0004] In view of this, the present invention provides a semiconductor device structure and an image sensor, which can reduce cutting yield loss and reduce the extension of cutting-induced cracks into the device area.
[0005] A semiconductor device structure includes a chip area and a scribe area arranged around the chip area, wherein the chip area includes a device area and a protection area arranged around the device area, the protection area is provided with at least one detection protection structure, the detection protection structure is arranged correspondingly around the device area, and the semiconductor device structure includes a stacked substrate layer and an interconnection layer, and the detection protection structure is arranged at least on a side of the substrate layer away from the interconnection layer.
[0006] In an embodiment of the present invention, the substrate layer includes a first surface and a second surface that are opposite to each other, the interconnection layer is disposed on the first surface, and the detection protection structure is disposed on the second surface.
[0007] In an embodiment of the present invention, the detection protection structure includes a continuous and uninterrupted annular structure, or the detection protection structure includes a plurality of sub-detection protection structures that are intermittently and annularly arranged.
[0008] In an embodiment of the present invention, the detection protection structure has a bent corner, and the corner is provided with an inner-corner compensation buffer structure.
[0009] In an embodiment of the present invention, the semiconductor device structure includes a guard ring, which is arranged around the device area, is arranged in the interconnect layer of the protection area, and is arranged corresponding to the detection protection structure.
[0010] In an embodiment of the present invention, the semiconductor device structure further includes a connecting line, which is arranged in the substrate layer of the protection zone and connected between the guard ring and the detection protection structure.
[0011] In an embodiment of the present invention, the protection zone is provided with a plurality of the detection and protection structures, and the plurality of the detection and protection structures are spaced apart from each other.
[0012] In an embodiment of the present invention, a first blocking groove is provided in the substrate layer of the protection zone, and at least one first blocking groove is provided between two adjacent detection protection structures.
[0013] In an embodiment of the present invention, at least one second blocking groove is provided in the substrate layer of the protection zone, and the second blocking groove is provided around the detection protection structure.
[0014] In an embodiment of the present invention, the semiconductor device structure further includes a test structure, and the test structure is arranged in the interconnect layer of the scribe area.
[0015] In an embodiment of the present invention, the semiconductor device structure includes a plurality of chip regions arranged in a matrix, and the area outside each chip region is the dicing region.
[0016] In an embodiment of the present invention, the above-mentioned semiconductor device structure also includes a color filter array, which is arranged on the surface of the substrate layer in the device area; and / or, the semiconductor device structure also includes a lens array, which is arranged on the light incident side of the color filter array in the device area.
[0017] In an embodiment of the present invention, the substrate layer of the above-mentioned device area is formed with a photoelectric conversion element, a transfer transistor and a floating diffusion area, a reset transistor and a source follower transistor, the photoelectric conversion element is used to convert the light signal containing image information into an electrical signal during the exposure process; the transfer transistor connects the photoelectric conversion element and the floating diffusion area, and is used to transfer the electrical signal of the photoelectric conversion element to the floating diffusion area; the source follower transistor is used to output the electrical signal of the floating diffusion area; the reset transistor is used to reset the floating diffusion area; and / or, the substrate layer of the device area is also formed with a selection transistor, and the selection transistor is used to select and output the electrical signal output by the source follower transistor to the column line.
[0018] In an embodiment of the present invention, the semiconductor device structure further includes a signal interconnection line, which is arranged in the interconnection layer of the device region and is used to transmit electrical signals.
[0019] In an embodiment of the present invention, the signal interconnection line includes at least a first metal interconnection layer close to the substrate layer, the first metal interconnection layer has a first chamfer, and at least one side of the detection protection structure close to the device area has a second chamfer, wherein the second chamfer is arranged correspondingly above and below the first chamfer.
[0020] In an embodiment of the present invention, the semiconductor device structure further includes a pad, and the substrate layer has a pad opening, wherein the pad is arranged on the interconnection layer based on the pad opening and is electrically connected to the interconnection layer, and there is a spacing between the pad opening and the orthographic projection of the detection protection structure on the surface of the substrate layer; and / or there is a spacing between the pad and the orthographic projection of the detection protection structure on the surface of the substrate layer.
[0021] In an embodiment of the present utility model, the semiconductor device structure also includes a shielding connector, the detection protection structure is electrically connected to the interconnection layer based on the shielding connector, and a potential is applied to the detection protection structure based on the interconnection layer, or the detection protection structure is electrically connected to the shading portion based on the shielding connector.
[0022] In an embodiment of the present invention, the detection protection structure is made of a conductive material.
[0023] In an embodiment of the present invention, the detection protection structure is made of metal material.
[0024] In an embodiment of the present invention, a light shielding portion is provided at the edge of the device area, the light shielding portion is provided on the substrate layer, and the light shielding portion is spaced apart from the detection protection structure.
[0025] In an embodiment of the present invention, the device area is provided with a light-shielding grid, which is arranged on the substrate layer. A plurality of pixel holes are formed on the light-shielding grid, and an edge of the light-shielding grid is connected to the light-shielding portion.
[0026] In an embodiment of the present invention, when the device area is provided with at least one of a light shielding grid and the light shielding portion, the detection protection structure and the corresponding light shielding portion and the light shielding grid are manufactured in the same process.
[0027] The utility model also provides an image sensor, which is applicable to the semiconductor device structure described in any one of the above solutions.
[0028] The chip area of the semiconductor device structure of the present invention is provided with a protection zone, and the detection protection structure in the protection zone can protect the device area. For example, after cutting based on the dicing area, or during the cutting process, the detection protection structure can cooperate with the detection equipment to detect whether there are target particles falling into the protection zone. If the presence of target particles in the protection zone is detected, the target particles can be prevented from being mistakenly detected as existing in the device area and being judged as defective products, which can reduce the loss of cutting yield caused by visual inspection errors. It can be understood that the target particles here can be particles commonly used in the prior art that are suitable for identification. For example, during the cutting process of the dicing area, cutting debris splashes onto the detection protection structure to form target particles. Debris detection is achieved based on the identification of the target particles. Therefore, the detection protection structure set in the present application can avoid the problem of target particles only falling into the protection zone and judging the chip area as a defective product, which can reduce the loss of cutting yield. Moreover, the detection protection structure of the present application is set around the device area, which can reduce the extension of cracks caused by cutting to the device area and reduce the risk of damage to the device area. In addition, the detection protection structure of the present application is similar to the Great Wall of the chip, surrounding the device area from all sides. It can not only prevent mechanical damage to the chip area when cutting the chip area, but also prevent water vapor, free ions, etc. from invading the chip area from the cutting incision and affecting the chip function. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a schematic diagram of a partial top view of the semiconductor device structure of the first embodiment of the present application.
[0030] Figure 2 yes Figure 1 The schematic cross-sectional view of the semiconductor device structure at position 1-1 is shown.
[0031] Figure 3 Schematic diagram of the pixel circuit structure of the device area of this application.
[0032] Figure 4 It is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to the second embodiment of the present application.
[0033] Figure 5 It is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to the third embodiment of the present application.
[0034] Figure 6 It is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to the fourth embodiment of the present application.
[0035] Figure 7 It is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to the fifth embodiment of the present application.
[0036] Figure 8 It is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to the sixth embodiment of the present application. DETAILED DESCRIPTION
[0037] The following describes the implementation of the present application through specific embodiments. People familiar with this technology can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0038] In the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the present application. It should be understood that other embodiments may be used, and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered limiting, and the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present application.
[0039] Although the terms "first", "second", etc. are used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
[0040] Furthermore, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprise", "include" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition occur only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.
[0041] First embodiment
[0042] Figure 1 is a partial top view of the semiconductor device structure according to the first embodiment of the present application. Figure 2 yes Figure 1 The schematic cross-sectional view of the semiconductor device structure at position 1-1 is shown.
[0043] like Figure 1 and Figure 2As shown, semiconductor device structure 10 includes a chip region and a scribe region 103 surrounding the chip region. Subsequent cutting based on scribe region 103 enables chip acquisition. The chip region includes a device region 101 and a protection region 102 surrounding device region 101. Protection region 102 is provided with at least one detection protection structure 19, which surrounds device region 101. Semiconductor device structure 10 includes a stacked substrate layer 11 and an interconnect layer 12. Detection protection structure 19 is disposed on substrate layer 11. Detection protection structure 19 may be disposed at least on a side of substrate layer 11 away from interconnect layer 12. In this embodiment, semiconductor device structure 10 is suitable for image sensors (CMOS). For example, after cutting based on scribe region 103, a chip including the chip region is obtained, and the chip is used in an image sensor.
[0044] The chip area of the semiconductor device structure 10 of the present application is provided with a protection zone 102. The detection protection structure 19 in the protection zone 102 can protect the device area 101. For example, after cutting based on the scribing area 103, or during the cutting process, the detection protection structure 19 can cooperate with the detection equipment to detect whether there are target particles falling into the protection zone 102. If the presence of target particles in the protection zone 102 is detected, the target particles can be prevented from being mistakenly detected as being present in the device area 101 and being judged as defective products, thereby reducing the loss of cutting yield caused by visual inspection errors. It can be understood that the target particles here can be particles commonly used in the prior art for identification. For example, during the cutting process of the scribing area 103, cutting debris splashes onto the detection protection structure 19 to form target particles. Based on the identification of the target particles, debris detection is realized. Therefore, the detection protection structure 19 set in the present application can avoid the problem of target particles only falling into the protection zone 102 and judging the chip area as a defective product, thereby reducing the loss of cutting yield. Moreover, the detection protection structure 19 of the present application is set around the device area 101, which can reduce the extension of cracks caused by cutting to the device area 101 and reduce the risk of damage to the device area 101. In addition, the detection protection structure 19 of the present application is similar to the Great Wall of the chip, surrounding the device area 101 from all sides, which can not only prevent mechanical damage to the chip area when cutting the chip area, but also prevent water vapor, free ions, etc. from invading the chip area from the cutting incision and affecting the chip function.
[0045] Alternatively, as Figure 1 and Figure 2 As shown, the detection protection structure 19 is annular, which can be a continuous and uninterrupted annular structure; the detection protection structure 19 can also be a discontinuous structure similar to a discontinuous line, for example, the detection protection structure 19 is composed of at least two detection segments combined into a ring shape, that is, the detection protection structure 19 includes a plurality of sub-detection protection structures that are discontinuous and arranged in an annular shape. In an optional embodiment, the size and material of each sub-detection protection structure are the same, and the spacing between adjacent sub-detection protection structures is equal.
[0046] Optionally, the substrate layer 11, serving as the base of the image sensor, may be a structure composed of a single material layer, including but not limited to a silicon substrate. The material may be single crystal silicon, single crystal germanium, polycrystalline silicon, amorphous silicon, a silicon-germanium compound, silicon-on-insulator (SOI), or the like. The substrate layer 11 may also include N- or P-type doped regions to meet practical needs. Furthermore, the substrate layer 11 may also be a multi-layer structure, such as including a semiconductor substrate (e.g., a Si substrate) and an epitaxial layer (e.g., a P-type epitaxial layer p-ep i) formed on the surface of the semiconductor substrate. In this case, the epitaxial layer serves as a device functional layer, enabling the fabrication of the image sensor device.
[0047] Optionally, the interconnection layer 12 includes a dielectric layer and a connecting line arranged in the dielectric layer, wherein the material of the dielectric layer can be a low-K dielectric material or an ultra-low-K dielectric material, such as silicon dioxide (SiO2), SiOH, SiOCH, fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), boron-phosphorus-doped silicon dioxide (BPSG), hydrogenated silsesquioxane or methyl silsesquioxane; the connecting line includes the following guard ring 13, connecting line 14, test structure 15, and signal interconnection line 18, and its material is, for example, titanium, tungsten, aluminum or copper, but is not limited thereto.
[0048] Alternatively, as Figure 2 As shown, the substrate layer 11 includes a first surface 11 a and a second surface 11 b that are opposite to each other, the interconnection layer 12 is provided on the first surface 11 a , and the detection protection structure 19 is provided on the second surface 11 b .
[0049] Alternatively, as Figure 2 As shown, the semiconductor device structure 10 further includes a test structure 15, which is disposed in the interconnect layer 12 corresponding to the scribe area 103. In this embodiment, the test structure 15 may be a test key for performing performance testing on the chip area.
[0050] Alternatively, as Figure 2 As shown, the semiconductor device structure 10 further includes a color filter array 16, which is disposed on the substrate layer 11 corresponding to the device region 101. In this embodiment, the color filter array 16 includes a plurality of color filter portions arranged in a matrix, each color filter portion being disposed corresponding to a pixel in the device region 101. The plurality of color filter portions include a plurality of red filters R for generating red light, a plurality of green filters G for generating green light, and a plurality of blue filters B for generating blue light, thereby forming a Bayer or quad-Bayer arrangement.
[0051] Alternatively, as Figure 2As shown, the semiconductor device structure 10 further includes a lens array 17, which is disposed on the light-entering side of the color filter array 16 in the device region 101. In this embodiment, the lens array 17 includes a plurality of convex lenses arranged in a matrix, each convex lens being disposed corresponding to a pixel in the device region 101. One lens can correspond to one or more pixels, and each convex lens is used to converge light.
[0052] Optionally, Figure 3 A schematic diagram of a pixel circuit of the device area of the present application is shown, such as Figure 3 As shown, the substrate layer 11 corresponding to the device region 101 is formed with a photoelectric conversion element PD, a transfer transistor TX, a floating diffusion region FD, a reset transistor RST, and a source follower transistor SF. The photoelectric conversion element PD is used to convert an optical signal containing image information into an electrical signal during the exposure process. The transfer transistor TX connects the photoelectric conversion element PD and the floating diffusion region FD and is used to transfer the electrical signal from the photoelectric conversion element PD to the floating diffusion region FD. The source follower transistor SF is used to output the electrical signal from the floating diffusion region FD. The reset transistor RST is used to at least reset the floating diffusion region FD. The substrate layer 11 is doped, such as by plasma implantation, to form the photoelectric conversion element PD, the floating diffusion region FD, and the source and drain electrodes of the transfer transistor TX, the source follower transistor SF, the reset transistor RST, and the select transistor RS within the substrate layer 11.
[0053] Alternatively, as Figure 3 As shown, the substrate layer 11 of the device region 101 may further be formed with a selection transistor RS, which is used to select and output the electrical signal output by the source follower transistor SF to a column line (Pixel out). Of course, in other examples, the pixel circuit is designed according to requirements.
[0054] Alternatively, as Figure 2 As shown, the semiconductor device structure 10 further includes a signal interconnection line 18, which is arranged in the interconnection layer 12 corresponding to the device region 101. The signal interconnection line 18 is used to realize electrical interconnection between pixel circuit transistors and signal input and electrical extraction.
[0055] Optionally, the signal interconnection line 18 includes at least a first metal interconnection layer (not shown) close to the substrate layer 11, the first metal layer has a first chamfer, and at least one side of the detection protection structure 19 close to the device area has a second chamfer, see Figure 1As shown, in the illustrated example, the detection protection structure 19 has a second chamfer, and the corner is not set to a right-angle structure, but the two sides are transitioned through two obtuse angles, wherein the second chamfer is set correspondingly to the first chamfer up and down, which is helpful to prevent the slices from sticking. In addition, it should be noted that the signal interconnection line 18 can further include a plurality of metal layers set from the first metal layer away from the substrate layer 11, which can also have corresponding chamfers and be set correspondingly up and down. It should be noted that, in addition to interconnecting the transistors at the corresponding positions in the device area, each metal layer can also be further extended laterally to realize the rewiring and transmission between signals; the corresponding setting can be a setting in a manner that the structure is the same and the orthographic projections overlap, and of course it can also be other ways that do not affect the function realization.
[0056] Optionally, the detection protection structure 19 has a bent corner, which is provided with an in-corner compensation buffer structure. In this example, the in-corner compensation buffer structure can be set on the inner side of the corner of the detection protection structure 19 (the side facing the device area), and can be connected to the detection protection structure 19 or not. The material can be the same as that of the detection protection structure 19, and the two can be formed based on the same process. The in-corner compensation buffer structure can be a trapezoidal structure with the oblique side of the corner as the upper base and the adjacent two side edges of the corresponding detection protection structure 19 as the side edges, which is beneficial to improving the corner performance and further beneficial to the realization of detection and protection functions.
[0057] Alternatively, as Figure 1 As shown, the semiconductor device structure 10 includes a plurality of chip regions arranged in a matrix, and the area outside each chip region is a dicing region 103 .
[0058] Optionally, the detection protection structure 19 is made of a conductive material. Further, the detection protection structure 19 is made of a metal material, for example, tungsten, copper, aluminum, gold, or silver, but not limited thereto.
[0059] Alternatively, as Figure 2 As shown, a light shielding portion 21 is provided at the edge of the device region 101. The light shielding portion 21 is disposed on the substrate layer 11 and is spaced apart from the detection protection structure 19. In this embodiment, the light shielding portion 21 is made of a conductive material, such as copper, aluminum, gold, or silver, but is not limited thereto. The light shielding portion 21 can be a black shielding area for peripheral circuits in a CMOS image sensor or a black level detection (BLC) area. Furthermore, a potential (such as GND) can be applied to the light shielding portion 21.
[0060] Alternatively, as Figure 1 As shown, the device area 101 is provided with a light shielding grid 22, which is provided on the substrate layer 11. A plurality of pixel holes are formed on the light shielding grid 22. In an optional example, the edge of the light shielding grid 22 is connected to the light shielding portion 21 (eg, Figure 1(See the example shown), with each filter portion disposed in each pixel aperture. In this embodiment, the light shielding grid 22 is made of a conductive material, such as, but not limited to, copper, aluminum, gold, or silver. The light shielding grid 22 can prevent crosstalk between pixels. For example, the color filter array 16 is disposed in the pixel apertures defined by the light shielding grid 22 to enable image acquisition.
[0061] Optionally, when the device area is provided with at least one of a light shielding grid 22 and a light shielding portion 21 , the detection protection structure 19 , the light shielding portion 21 and the light shielding grid 22 are all manufactured in the same process.
[0062] Optionally, the semiconductor device structure further includes a pad, and the substrate layer 11 has a pad opening. The pad is arranged on the interconnection layer 12 based on the pad opening and is electrically connected to the interconnection layer 12, for example, connected to the first metal layer in the interconnection layer 12, wherein there is a spacing between the pad opening and the orthographic projection of the detection protection structure 19 on the surface of the substrate layer 11 and / or there is a spacing between the pad and the orthographic projection of the detection protection structure 19 on the surface of the substrate layer 11. It should be noted that the pad can be arranged in the peripheral circuit area, or it can be the arrangement area of the pad in the existing image sensor, and the pad can realize the extraction and application of electrical signals, etc. There is a spacing between the detection protection structure 19 and the adjacent pad opening and the adjacent pad edge, which is conducive to protecting the structure within the detection protection structure 19 and preventing crosstalk between signals.
[0063] Optionally, the semiconductor device structure further includes a shielding connector. The detection protection structure 19 is electrically connected to the interconnect layer 12 based on the shielding connector, for example, connected to the first metal layer in the interconnect layer 12, and a potential is applied to the detection protection structure 19 based on the interconnect layer 12. Alternatively, the detection protection structure 19 is electrically connected to the light shielding portion 21 based on the shielding connector. Through the above two methods, a potential can be applied to the detection protection structure 19 based on the shielding connector. The potential can be applied according to actual needs, such as applying a ground potential GND. The potential is conducive to shielding the structure protected by the detection protection structure 19. The shielding connector can be formed by forming a through hole that penetrates the substrate layer 11 and is filled with metal material, such as by further electrically connecting the shielding connector to the metal layer in the interconnect layer 12. The shielding connector can also be formed by laterally connecting the detection protection structure 19 to the light shielding portion 21. For example, the detection protection structure 19, the light shielding portion 21, and the shielding connector are formed based on the same process and electrically connected. The detection protection structure 19 can be shielded by applying a potential to the light shielding portion 21.
[0064] Second embodiment
[0065] Figure 4 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor device according to a second embodiment of the present application. Figure 4 As shown, the semiconductor device structure 10 of this embodiment is substantially the same as the semiconductor device structure 10 of the first embodiment, except that at least one second blocking groove 202 is provided on the substrate layer 11 of the protection area 102. The second blocking groove 202 is disposed around the detection protection structure 19. In this embodiment, the second blocking groove 202 can alleviate the extension of the cutting crack into the chip area, thereby reducing cutting stress.
[0066] Optionally, the second blocking groove 202 is formed by etching the second surface of the substrate layer 11 toward the first surface. The depth of the second blocking groove 202 is less than or equal to the thickness of the substrate layer 11. In one implementation, the second blocking groove 202 is completed simultaneously with the conventional image sensor pad opening process, forming a through-hole second blocking groove 202 that penetrates the substrate layer 11, thereby simplifying the process and relieving stress. Of course, the second blocking groove 202 can also be further filled with a subsequent material layer, such as silicon oxide.
[0067] Optionally, the second blocking groove 202 is annular, which may be a continuous and uninterrupted ring or a discontinuous structure similar to a discontinuous line. For example, the second blocking groove 202 is formed into an annular shape by combining at least two groove sections.
[0068] Third embodiment
[0069] Figure 5 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to a third embodiment of the present application. Figure 5 As shown, the semiconductor device structure 10 of this embodiment is substantially the same as the semiconductor device structure 10 of the first embodiment, except that a plurality of detection protection structures 19 are provided in the protection area 102, and the plurality of detection protection structures 19 are spaced apart from each other. In this embodiment, the plurality of detection protection structures 19 are sequentially spaced apart in a direction away from the device area 101. The provision of the plurality of detection protection structures 19 further prevents cutting cracks from extending into the chip area, thereby improving the yield rate.
[0070] Fourth embodiment
[0071] Figure 6 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to a fourth embodiment of the present application. Figure 6 As shown, the semiconductor device structure 10 of this embodiment is substantially the same as the semiconductor device structure 10 of the third embodiment, except that a first blocking groove 201 is provided on the substrate layer 11 of the protection area 102, and at least one first blocking groove 201 is provided between two adjacent detection protection structures 19. In this embodiment, the first blocking groove 201 can reduce the extension of cutting cracks into the device area 101, thereby reducing cutting stress. In particular, providing multiple first blocking grooves 201 can further prevent crack extension.
[0072] Optionally, the first blocking groove 201 is formed by etching the second surface of the substrate layer 11 toward the first surface. The depth of the first blocking groove 201 is less than or equal to the thickness of the substrate layer 11. In one implementation, an additional mask can be used to form the first blocking groove 201. Of course, in other implementations, the mask can also be formed during the process of forming the backside isolation structure BDT1 in the device area. Of course, the first blocking groove 201 can also be further filled with a subsequent material layer, such as silicon oxide.
[0073] Optionally, the depth of each first barrier groove 201 may be the same, or the depth of at least one first barrier groove 201 may be different from the depths of the other first barrier grooves 201 , which can be freely designed according to actual needs.
[0074] Optionally, each first blocking groove 201 is annular, and may be a continuous uninterrupted ring, or a discontinuous structure similar to a discontinuous line. For example, the first blocking groove 201 is formed into an annular shape by combining at least two groove sections.
[0075] Fifth embodiment
[0076] Figure 7 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure according to a fifth embodiment of the present application. Figure 7 As shown, the semiconductor device structure 10 of this embodiment is substantially the same as the semiconductor device structure 10 of the above embodiment, except that the semiconductor device structure 10 includes a guard ring 13. The guard ring 13 is disposed around the device region 101 and is disposed in the interconnect layer 12 of the protection region 102. The guard ring 13 is disposed corresponding to the detection protection structure 19. Optionally, when there are multiple detection protection structures 19, there are also multiple guard rings 13, and the two are disposed in correspondence with each other (e.g., the centers of the paired detection protection structures 19 and the guard rings 13 are disposed opposite each other). In this embodiment, the guard ring 13 can be used to prevent the extension of cutting cracks, reduce cutting stress, and can also be used to prevent electrical interference and signal radiation effects.
[0077] Sixth embodiment
[0078] Figure 8 FIG. 1 is a partial cross-sectional view of a semiconductor device structure according to a sixth embodiment of the present application. Figure 8As shown, the semiconductor device structure 10 of this embodiment is substantially the same as the semiconductor device structure 10 of the fifth embodiment, except that the semiconductor device structure 10 further includes a connecting wire 14. The connecting wire 14 is disposed in the substrate layer 11 corresponding to the protection zone 102, and the connecting wire 14 is connected between the guard ring 13 and the detection protection structure 19. The connecting wire 14 can be made of a conductive material and electrically connected between the guard ring 13 and the detection protection structure 19. Of course, the connecting wire 14 can also be made of an insulating material and physically connected between the guard ring 13 and the detection protection structure 19. Connecting the connecting wire 14 between the guard ring 13 and the detection protection structure 19 in this application can further prevent electrical interference and signal radiation.
[0079] Seventh embodiment
[0080] The present application also provides an image sensor, which can be a CMOS image sensor. The chip including the device area obtained after cutting the above-mentioned semiconductor device structure can be used in the image sensor to realize image acquisition. The chip obtained by cutting based on the method of the present application can prevent mechanical damage to the chip when cutting the chip; in addition, it can also prevent water vapor, free ions, etc. from invading the chip from the side fracture and affecting the chip function, and by grounding the packaging strip, it can also shield interference outside the chip; similar to the Great Wall of the chip, surrounding the chip from all sides can not only alleviate the impact of dicing on the internal circuit of the chip; in addition, it can also prevent external water vapor, dust, etc. from invading the interior of the chip; further, it can reduce the loss of cutting yield caused by visual inspection errors, and at the same time reduce the impact of stress on the inside of the chip during cutting, reduce the possibility of damage to the inside of the chip, and help improve imaging quality.
[0081] In addition, the image sensor described in any of the above schemes can also be applied to electronic devices. For example, the electronic device can be security monitoring, vehicle-mounted electronics, mobile phone cameras, machine vision and other equipment. The image sensor based on the utility model can obtain high-quality image information and can also be used in infrared utilization equipment.
[0082] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.
Claims
1. A semiconductor device structure, characterized in that: It includes a chip area and a dicing area arranged around the chip area, wherein the chip area includes a device area and a protection area arranged around the device area, the protection area is provided with at least one detection protection structure, the detection protection structure is arranged correspondingly around the device area, and the semiconductor device structure includes a stacked substrate layer and an interconnection layer, and the detection protection structure is arranged at least on the side of the substrate layer away from the interconnection layer.
2. The semiconductor device structure according to claim 1, wherein: The substrate layer includes a first surface and a second surface relative to each other, the interconnection layer is arranged on the first surface, and the detection protection structure is arranged on the second surface; and / or, the detection protection structure includes a continuous and uninterrupted annular structure or the detection protection structure includes a plurality of sub-detection protection structures that are intermittent and arranged in a ring shape; and / or, the detection protection structure has a bent corner, and the corner is provided with an in-corner compensation buffer structure.
3. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure further includes a guard ring, which is arranged around the device area, is arranged in the interconnect layer corresponding to the protection area, and is arranged corresponding to the detection protection structure.
4. The semiconductor device structure according to claim 3, wherein: The semiconductor device structure further includes a connecting line, which is arranged in the substrate layer corresponding to the protection zone, and is connected between the guard ring and the detection protection structure.
5. The semiconductor device structure according to claim 1, wherein: The protection zone is provided with a plurality of detection and protection structures, and the plurality of detection and protection structures are arranged at intervals from each other.
6. The semiconductor device structure according to claim 5, wherein: A first blocking groove is provided in the substrate layer corresponding to the protection zone, and at least one first blocking groove is provided between two adjacent detection protection structures.
7. The semiconductor device structure according to claim 1, wherein: At least one second blocking groove is provided in the substrate layer corresponding to the protection zone, and the second blocking groove is arranged around the detection protection structure.
8. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure further includes a test structure, wherein the test structure is arranged in the interconnect layer of the scribe area; And / or, the semiconductor device structure includes a plurality of chip areas arranged in a matrix, and the area outside each chip area is the dicing area.
9. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure further includes a color filter array, which is arranged on the substrate layer corresponding to the device area; and / or the semiconductor device structure further includes a lens array, which is arranged on the light incident side of the substrate layer corresponding to the device area.
10. The semiconductor device structure according to claim 9, wherein: The substrate layer corresponding to the device area is formed with a photoelectric conversion element, a transfer transistor, a floating diffusion area, a reset transistor and a source follower transistor. The photoelectric conversion element is used to convert the optical signal containing image information into an electrical signal during the exposure process; the transfer transistor connects the photoelectric conversion element and the floating diffusion area, and is used to transfer the electrical signal of the photoelectric conversion element to the floating diffusion area; the source follower transistor is used to output the electrical signal of the floating diffusion area; the reset transistor is used to reset at least the floating diffusion area; and / or, the substrate layer corresponding to the device area is also formed with a selection transistor, which is used to select and output the electrical signal output by the source follower transistor to the column line.
11. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure further includes a signal interconnection line, which is arranged in the interconnection layer corresponding to the device area and is used to transmit electrical signals.
12. The semiconductor device structure according to claim 11, wherein: The signal interconnection line includes at least a first metal interconnection layer close to the substrate layer, the first metal interconnection layer has a first chamfer, and at least one side of the detection protection structure close to the device area has a second chamfer, wherein the second chamfer is arranged correspondingly to the first chamfer above and below.
13. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure also includes a pad, and the substrate layer has a pad opening, wherein the pad is arranged on the interconnection layer based on the pad opening and is electrically connected to the interconnection layer, and there is a distance between the pad opening and the orthographic projection of the detection protection structure on the surface of the substrate layer; and / or there is a distance between the pad and the orthographic projection of the detection protection structure on the surface of the substrate layer.
14. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure also includes a shielding connector, the detection protection structure is electrically connected to the interconnection layer based on the shielding connector, and a potential is applied to the detection protection structure based on the interconnection layer, or the detection protection structure is electrically connected to the shading portion based on the shielding connector.
15. The semiconductor device structure according to any one of claims 1 to 14, wherein: Include at least one of the following: The detection protection structure is made of metal material; The device area is provided with a light shielding portion, the light shielding portion is arranged on the substrate layer, and the light shielding portion is spaced apart from the detection protection structure; The device area is provided with a light-shielding grid, the light-shielding grid is provided on the substrate layer, a plurality of pixel holes are formed on the light-shielding grid, and the edge of the light-shielding grid is connected to the light-shielding portion; When the device area is provided with at least one of a light shielding grid and the light shielding portion, the detection protection structure and the corresponding light shielding portion and the light shielding grid are manufactured by the same process.
16. An image sensor, characterized in that: The semiconductor device structure according to any one of claims 1 to 15 is applicable.