Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a substrate which comprises a display area and a peripheral area surrounding the display area; the multiple sub-pixels are located on one side of the substrate and located in the display area; the shading part is positioned on one side, close to the substrate, of the plurality of sub-pixels and is positioned in the display area; and the at least one electrostatic absorption unit is arranged on the same layer as the shading part, is connected with the shading part and is positioned in the peripheral area.

Description

Technical Field

[0001] The utility model relates to but is not limited to display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, displays using OLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] However, the display product has a problem of growing dark spots (GDS). Utility Model Content

[0004] On the one hand, an embodiment of the present invention provides a display substrate, comprising: a base substrate, comprising a display area and a peripheral area surrounding the display area; a plurality of sub-pixels, located on one side of the base substrate and located in the display area; a light-shielding portion, located on a side of the plurality of sub-pixels close to the base substrate and located in the display area; and at least one electrostatic absorption unit, arranged on the same layer as the light-shielding portion and connected to the light-shielding portion, located in the peripheral area.

[0005] In an exemplary embodiment, in a direction away from the base substrate, the display substrate includes a circuit structure layer and a light-emitting structure layer arranged in sequence, the circuit structure layer includes a bottom shading metal layer; the shading portion and the electrostatic absorption unit are located in the bottom shading metal layer; the circuit structure layer includes a pixel driving circuit, the light-emitting structure layer includes a light-emitting element, and the pixel driving circuit is connected to the light-emitting element; the circuit structure layer includes a plurality of vias perpendicular to the base substrate; within the plane of the base substrate, the distance between the electrostatic absorption unit and the nearest via is greater than or equal to 5.4 microns, and the distance between the electrostatic absorption unit and the nearest via is the minimum distance between the edge of the electrostatic absorption unit and the edge of the via.

[0006] In an exemplary embodiment, the bottom light-shielding metal layer further includes a connecting line, and the electrostatic absorption unit is connected to the light-shielding portion via the connecting line.

[0007] In an exemplary embodiment, the shading portion includes a shading line extending along the second direction, and the electrostatic absorption unit is connected to the shading portion through the connecting line, including: the first end of the connecting line is connected to the shading line, and the second end of the connecting line is connected to the electrostatic absorption unit.

[0008] In an exemplary embodiment, the distance between the connecting line and the nearest via hole is greater than or equal to 5.4 micrometers, and the distance between the connecting line and the nearest via hole is the minimum distance between an edge of the connecting line and an edge of the via hole.

[0009] In an exemplary embodiment, the peripheral area includes a driving circuit area, the driving circuit area is located on at least one side of the display area along the first direction, and at least one electrostatic absorption unit is located between the display area and the driving circuit area.

[0010] In an exemplary embodiment, the peripheral area includes a left frame and a right frame located on both sides of the display area along a first direction, and an upper frame and a lower frame located on both sides of the display area along a second direction, the left frame, the right frame, the upper frame and the lower frame intersect with each other to form four corners; the first direction and the second direction intersect; and at least one electrostatic absorption unit is provided at at least one of the corners.

[0011] In an exemplary embodiment, the orthographic projection shape of the electrostatic absorption unit on the base substrate is circular or elliptical; or, any inner angle of the orthographic projection shape of the electrostatic absorption unit on the base substrate is greater than or equal to 120 degrees.

[0012] In an exemplary embodiment, the orthographic projection shape of the electrostatic absorption unit on the base substrate is a circle, and the diameter of the circle is greater than or equal to 5.4 micrometers and less than or equal to 6.6 micrometers.

[0013] In an exemplary embodiment, on the side of the electrostatic absorption unit away from the base substrate, the circuit structure layer includes a first buffer layer, a first gate insulation layer, a second gate insulation layer, a first interlayer insulation layer, a second buffer layer, a third gate insulation layer, a second interlayer insulation layer, a passivation layer and a first flat layer arranged in sequence.

[0014] In an exemplary embodiment, the thickness of the first interlayer insulating layer is greater than or equal to 500 nm, and the thickness of the first interlayer insulating layer is the distance between a surface of the first interlayer insulating layer close to the base substrate and a surface of the first interlayer insulating layer away from the base substrate.

[0015] In an exemplary embodiment, the thickness of the second interlayer insulating layer is greater than or equal to 500 nm, and the thickness of the second interlayer insulating layer is the distance between the surface of the second interlayer insulating layer close to the base substrate and the surface of the second interlayer insulating layer away from the base substrate.

[0016] In an exemplary embodiment, the thickness of the passivation layer is greater than or equal to 300 nm, and the thickness of the passivation layer is the distance between a surface of the passivation layer close to the substrate and a surface of the passivation layer away from the substrate.

[0017] An embodiment of the present invention further provides a display device, comprising the display substrate as described above.

[0018] The display substrate provided by the present invention has at least one electrostatic absorption unit disposed in the peripheral region. The electrostatic absorption unit is on the same layer as and interconnected with the light-shielding portion. After static electricity from the display substrate is transmitted to the bottom light-shielding metal layer, it is promptly absorbed by the electrostatic absorption unit, thereby avoiding damage to the film layer of the display substrate and preventing water vapor from invading the display substrate through damaged film layers. This effectively prevents poor GDS of the display substrate and solves the GDS problem of display products.

[0019] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be achieved and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0021] Figure 1 It is a structural schematic diagram of a display substrate;

[0022] Figure 2 This is a schematic diagram of the planar structure of a display area in a display substrate;

[0023] Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0024] Figure 4 A schematic diagram showing a GDS defect on a substrate;

[0025] Figure 5 is a cross-sectional view of a display substrate in a display area in an exemplary embodiment;

[0026] Figure 6 is a top view showing a substrate in an exemplary embodiment;

[0027] Figure 7 In an exemplary embodiment Figure 6 Cross-sectional view along CC direction. DETAILED DESCRIPTION

[0028] The present invention describes a plurality of embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present invention. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0029] The present invention includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present invention may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present invention may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0030] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present invention.

[0031] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present invention is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings may not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0032] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion among constituent elements, and are not intended to limit the quantity. The "plurality" in this utility model means two or more.

[0033] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of this specification and simplifying the description. They are not intended to indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. The positional relationships of the components may be appropriately modified depending on the orientation of the components being described. Therefore, the present invention is not limited to the words and phrases described in the specification and may be appropriately modified depending on the circumstances.

[0034] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this utility model based on the specific circumstances.

[0035] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0036] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0037] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1 Schematic diagram of the structure of a display substrate. Figure 1 As shown, a display substrate may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, scan driver, and light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals and scan start signals suitable for the specifications of the scan driver to the scan driver, and clock signals and emission stop signals suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0039] Figure 2 FIG. 1 is a schematic diagram of the planar structure of a display area in a display substrate. Figure 2 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting element in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel. The light-emitting element is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0040] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this is not a limitation in the present invention.

[0041] In an exemplary embodiment, a pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel that emits white (W) light. In another example, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged horizontally, vertically, in a square, or in a diamond shape, etc., which is not limited in this invention.

[0042] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 3 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C, and the pixel driving circuit is respectively connected to 6 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT and first power line VDD).

[0043] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the second end of the capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0044] In an exemplary embodiment, a first end of the capacitor C is connected to the first power line VDD, and a second end of the capacitor C is connected to the second node N2 , ie, the second end of the capacitor C is connected to the gate electrode of the third transistor T3 .

[0045] The gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initial voltage to the gate electrode of the third transistor T3, so that the charge amount of the gate electrode of the third transistor T3 is initialized.

[0046] The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0047] The gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second end of the capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the gate electrode and the first electrode of the third transistor T3.

[0048] A gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0049] The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, thereby causing the light-emitting element EL to emit light.

[0050] A gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element EL. When an on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits an initial voltage to the first electrode of the light-emitting element EL, thereby initializing or releasing the charge accumulated in the first electrode of the light-emitting element EL.

[0051] In an exemplary embodiment, the light-emitting element EL can be an OLED, including a stacked first electrode, an organic light-emitting layer and a second electrode, or can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer and a second electrode. In this embodiment, the first electrode can be an anode and the second electrode can be a cathode, and the present invention does not limit this.

[0052] In an exemplary embodiment, the second electrode of the light emitting element EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0053] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0054] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistors is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistors is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0055] Taking the case where all seven transistors are P-type transistors as an example, the operation process of the pixel driving circuit may include:

[0056] The first phase A1, known as the reset phase, involves a low-level signal on the second scan signal line S2, while high-level signals on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1 and the seventh transistor T7. Turning on the first transistor T1 allows the initial voltage on the initial signal line INIT to be supplied to the second node N2, initializing the capacitor C and clearing the existing data voltage in the capacitor. Turning on the seventh transistor T7 allows the initial voltage on the initial signal line INIT to be supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing initialization. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this phase, the OLED does not emit light.

[0057] In the second phase A2, known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is low, the signals on the second scan signal line S2 and the light-emitting signal line E are high, and the data signal line D outputs a data voltage. During this phase, since the second terminal of capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2 and the fourth transistor T4. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into capacitor C. The voltage at the second terminal of capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The high signal on the second scan signal line S2 turns off the first transistor T1 and the seventh transistor T7. The signal of the light emitting signal line E is a high level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0058] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is low, while the signals on the first scan signal line S1 and the second scan signal line S2 are high. The low signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. Because the voltage Vd-|Vth| was written to the second terminal of the capacitor C in the previous phase, the third transistor T3 remains on during this phase. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0059] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0060] I=K*(Vgs-Vth) 2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*(Vdd-Vd)2

[0061] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0062] With the development of display technology, display substrates have evolved through various display formats, including notch screens, waterdrop notches, curved screens, and foldable screens. Flexible displays have become the current trend in display substrates. To improve flexibility, some technologies are replacing glass in display substrates with plastic materials, such as the substrate material and subsequent screen protector. However, plastic substrates are more susceptible to static electricity than glass. OLEDs fabricated on these substrates are susceptible to static damage, which can lead to moisture intrusion and cause GDS defects.

[0063] Figure 4 This is a schematic diagram showing a GDS defect on a substrate. Figure 4 As shown, the display substrate includes a display area AA and a peripheral area PA surrounding the display area AA. Studies have found that GDS defects are prone to occur at the corners of the display substrate, especially for the display substrate of a folding screen. The probability of GDS defects occurring at the corners of the display substrate is even greater. Figure 4 In the figure, black spots G with GDS defects formed at four corners of the display substrate are used as an example for illustration.

[0064] In an exemplary embodiment, the shape of the display area 100 can be a quadrilateral, a circle, an ellipse, another polygonal shape, or an irregular shape. The corners of the display area 100 can be rounded, but this is not a limitation of the present invention. In an exemplary embodiment, the edge shapes of the display area at different borders vary depending on the shape of the display area, and can be, for example, straight lines, curves, broken lines, or other different shapes, but this is not a limitation of the present invention.

[0065] Figure 5 FIG is a cross-sectional view of a display substrate in a display area in an exemplary embodiment, illustrating the structure of a single sub-pixel. Figure 5 As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a base substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially arranged on the base substrate. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0066] In some examples, Figure 5 In the figure, each sub-pixel includes a first transistor 21, a second transistor 22, and a capacitor 23. The first transistor 21 and the second transistor 22 can be of different transistor types. The first transistor 21 can be a low-temperature polysilicon thin-film transistor, and the second transistor 22 can be an oxide thin-film transistor.

[0067] In some examples, the circuit structure layer 12 in the display area may include: a bottom shielding metal (BSM) layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on the base substrate 10. The multiple metal layers of the circuit structure layer 12 in this example may include: a bottom shielding metal layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer. The bottom shielding metal layer may include multiple shielding portions configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor, and the multiple shielding portions may be interconnected. A first buffer layer 110 may be provided between the bottom light-shielding metal layer and the first semiconductor layer. The first buffer layer 110 may prevent harmful substances in the base substrate from invading the interior of the display substrate and may also increase the adhesion of the film layer in the display substrate to the base substrate. A first gate insulating (GI) layer 101 may be provided between the first semiconductor layer and the first gate metal layer. A second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer. A first interlayer insulating (ILD) layer 103 and a second buffer layer 104 may be provided between the second gate metal layer and the second semiconductor layer. The second buffer layer 104 may be located on the side of the first interlayer insulating layer 103 away from the base substrate 10; a third gate insulating layer 105 may be provided between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 106 may be provided between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 107 and a first planarization (PLN) layer 108 may be provided between the first source / drain metal layer and the second source / drain metal layer. The first planarization layer 108 may be located on the side of the passivation layer 107 away from the base substrate 10; and a second planarization layer 109 may be provided on the side of the second source / drain metal layer away from the base substrate 10. The first buffer layer 110, the first gate insulating layer 101, the second gate insulating layer 102, the first interlayer insulating layer 103, the second buffer layer 104, the third gate insulating layer 105, the second interlayer insulating layer 106, and the passivation layer 107 may be inorganic insulating layers, and the first planarization layer 108 and the second planarization layer 109 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer. In other examples, the second buffer layer can be omitted between the second gate metal layer and the second semiconductor layer, and only the first interlayer insulating layer 103 can be provided.

[0068] In some examples, such as Figure 5As shown, the first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate electrode 213 of the first transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate electrode 213 of the first transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate electrode 224 of the second transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second transistor 22. The third gate metal layer may include at least a second gate 223 of the second transistor 22. The orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second transistor 22, and the second gate 223 may be the top gate of the second transistor 22.

[0069] In some examples, such as Figure 5As shown, the first source / drain metal layer may include at least a first source 211 and a first drain 212 of the first transistor 21, and a second source 221 and a second drain 222 of the second transistor 22. The second interlayer insulating layer 106 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The second interlayer insulating layer 106 and the third gate insulating layer 105 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined through the passivation layer 107 and the first planarization layer 108. In this example, the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0070] In some examples, such as Figure 5As shown, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 109 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the second planar layer 109. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 109. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0071] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more layers selected from the group consisting of a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage applied by the first electrode 131 and the second electrode 133, the organic material's luminescence properties can be utilized to produce light of desired grayscale.

[0072] In some examples, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce processing complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be a common layer, while the electron injection layer and electron transport layer on the other side can be a common layer. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated using a single process (single evaporation process or single inkjet printing process), and can be isolated by surface step differences or surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or open mask, or by inkjet printing.

[0073] In some examples, such as Figure 5 As shown, the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic.

[0074] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0075] In some examples, such as Figure 5As shown, in a direction perpendicular to the display substrate, the touch structure layer 15 in the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulation layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154, arranged in sequence. The touch buffer layer 150 and the touch interlayer insulation layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be interconnected and integrally formed. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be connected to adjacent second touch electrodes through vias provided in the touch interlayer insulation layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: multiple first touch electrodes, multiple second touch electrodes, and multiple second connecting portions. The second touch electrodes and the second connecting portions may be interconnected as an integral structure. The second touch conductive layer may include multiple first connecting portions, each of which may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0076] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present invention.

[0077] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0078] In an exemplary embodiment, different signal lines are also provided in the multiple metal layers of the circuit structure layer 12, for example Figure 3Multiple signal lines of the pixel driving circuit in the display area 100 are provided to facilitate driving the light-emitting elements to emit light. The extension directions of these signal lines can be staggered, and the layers can be interconnected through vias. The inventors of this application have discovered that static electricity can be transmitted from the first source and drain metal layer to the bottom light-shielding metal layer 100 through the interlayer connection vias and diffuse and propagate within the bottom light-shielding metal layer 100. The first gate metal layer overlapping the bottom light-shielding metal layer 100 will generate induced charges. The induced charges are easily released at the weak points of the film between the first semiconductor layer and the first gate metal layer, causing damage to the film. The weak points of the film are generally near the vias. In addition, near the connection vias around the display area 100, the static electricity discharge can easily cause a micro-short circuit between the first gate metal layer and the second gate metal layer. For example, the voltage signal transmitted by the reset signal line set in the first gate metal layer is about 15V, and the voltage signal transmitted by the initial signal line set in the second gate metal layer is about -20V. If a micro-short circuit occurs between the two, the film near the short circuit location will be damaged. When the film layer is damaged, water vapor from one side of the substrate 10 can easily invade the light-emitting element through the via holes near the damage. Since static electricity is easily generated at the corners of the display area 100, GDS defects are easily caused at the corners of the display area 100.

[0079] An embodiment of the present invention provides a display substrate, comprising: a base substrate, comprising a display area and a peripheral area surrounding the display area;

[0080] A plurality of sub-pixels are located on one side of the base substrate and in the display area;

[0081] a light shielding portion, located on a side of the plurality of sub-pixels close to the base substrate and located in the display area;

[0082] At least one electrostatic absorption unit is provided in the same layer as the light shielding portion and is connected to the light shielding portion, and is located in the peripheral area.

[0083] The display substrate provided by the embodiment of the present invention has at least one electrostatic absorption unit arranged in the peripheral area. The electrostatic absorption unit is on the same layer as the light-shielding portion and is interconnected with the light-shielding portion. After the static electricity of the display substrate is transmitted to the bottom light-shielding metal layer, it can be absorbed by the electrostatic absorption unit in time, avoiding damage to the film layer of the display substrate, thereby preventing water vapor from invading the display substrate from the damaged part of the film layer, and effectively preventing GDS defects of the display substrate.

[0084] In an exemplary embodiment, the peripheral area includes a driving circuit region, the driving circuit region is located on at least one side of the display area along the first direction, and at least one electrostatic absorption unit is located between the display area and the driving circuit region.

[0085] In an exemplary embodiment, the display substrate includes a circuit structure layer and a light-emitting structure layer arranged sequentially in a direction away from the base substrate. The circuit structure layer includes a bottom light-shielding metal layer; the light-shielding portion and the electrostatic absorption unit are located in the bottom light-shielding metal layer; the circuit structure layer includes a pixel driving circuit; the light-emitting structure layer includes a light-emitting element, and the pixel driving circuit is connected to the light-emitting element; the circuit structure layer includes a plurality of vias perpendicular to the base substrate. In this embodiment, different layers of the driving circuit layer can be connected by vias, or the vias can be dummy holes and do not serve a connecting function.

[0086] In an exemplary embodiment, within the plane of the substrate, the distance between the electrostatic absorption unit and the nearest via is greater than or equal to 5.4 microns. The distance between the electrostatic absorption unit and the nearest via is the minimum distance between the edge of the electrostatic absorption unit and the edge of the via. In this embodiment, by setting the distance between the electrostatic absorption unit and the nearest via to be greater than or equal to 5.4 microns, the electrostatic absorption unit is further away from the surrounding vias. During the static discharge process, the electrostatic absorption unit avoids weak points in the film layer, making it less likely to damage the film layer of the display substrate. Furthermore, even if the electrostatic absorption unit damages the film layer during static discharge, the distance between the electrostatic absorption unit and the surrounding vias prevents moisture from invading, effectively protecting the display substrate.

[0087] In an exemplary embodiment, the orthographic projection of the electrostatic absorption unit on the substrate is circular or elliptical, or any internal angle of the orthographic projection of the electrostatic absorption unit on the substrate is greater than or equal to 120 degrees. For example, any internal angle of the orthographic projection of the electrostatic absorption unit on the substrate is greater than or equal to 135 degrees. In this embodiment, by setting the orthographic projection of the electrostatic absorption unit without sharp corners, sharp discharge is avoided, the destructive force of the electrostatic absorption unit during the static discharge process is reduced, and the film layer is less likely to be damaged.

[0088] Figure 6 FIG. 1 is a top view of a display substrate in an exemplary embodiment, illustrating the positions of the bottom light-shielding metal layer and the electrostatic absorption unit, and omitting other structures of the display substrate. Figure 6As shown, the peripheral area PA surrounds the display area AA. A first driver circuit area B1 and a second driver circuit area B2 are provided on either side of the display area AA along a first direction X. Gate driver circuits may be provided within the first driver circuit area B1 and the second driver circuit area B2 to control the light emission of the sub-pixels Pxij in the display area AA. The multiple sub-pixels Pxij in the display area AA may be arranged in an array along a first direction X and a second direction Y. The first direction X and the second direction Y may intersect, for example, they may be perpendicular to each other. A bottom light-shielding metal layer 110 is located on the side of the multiple sub-pixels Pxij that is closest to the base substrate. The bottom light-shielding metal layer 100 may include multiple interconnected light-shielding portions 1001. These multiple interconnected light-shielding portions 1001 can provide light shielding for transistors on the display substrate and can also be used to transmit signals. For example, these multiple interconnected light-shielding portions 1001 can be used to transmit voltage signals from a first power line, helping to reduce voltage drop and improve the display quality of the display substrate. The shape, shielding position, size, and signal transmission characteristics of the light-shielding portions 1001 can be configured as needed, and the present invention is not limited thereto.

[0089] like Figure 6 As shown, at least one electrostatic absorption unit 191 is provided in the peripheral area PA. The electrostatic absorption unit 191 is provided in the same layer as the light shielding portion 1001 and is connected to the light shielding portion 1001. The peripheral area PA includes left and right frames located on both sides of the display area AA along the first direction X, and upper and lower frames located on both sides of the display area AA along the second direction Y. The intersection of these four frames forms the four corners of the display substrate. Figure 6 In the example, an electrostatic absorption unit 191 is provided at each of the four corners of the peripheral area PA. Since the four corners of the peripheral area PA are high-electrostatic areas, the electrostatic absorption units 191 are provided there so that static electricity can be absorbed by the electrostatic absorption units 191 immediately after being conducted to the light shielding portion 1001, thereby avoiding damage to the film layer of the display substrate. In other embodiments, the number and distribution of the electrostatic absorption units 191 can be set as needed. For example, an electrostatic absorption unit 191 can be provided in the peripheral area PA at both ends of each row of sub-pixels Pxij arranged along the first direction X, or an electrostatic absorption unit 191 can be provided in the peripheral area PA at both ends of each column of sub-pixels Pxij arranged along the second direction Y, or one or more electrostatic absorption units 191 can be provided every few rows or columns of sub-pixels Pxij. The present invention is not limited to this. The term "A and B are provided in the same layer" in the present invention means that A and B are formed simultaneously through the same patterning process when the display substrate is prepared.

[0090] In an exemplary embodiment, the electrostatic absorption unit 191 may be located between the display area AA and the driving circuit area, the light shielding portion 1001 may include a plurality of light shielding lines 1101, the bottom light shielding metal layer 100 may include a connecting line 1102, the light shielding line 1101 may extend along the second direction Y, the first end of the connecting line 1102 is connected to the corresponding light shielding line 1101, and the second end of the connecting line 1102 is connected to the corresponding electrostatic absorption unit 191. Figure 6 As shown, the four electrostatic absorption units 191 can be connected to the shielding lines 1101 below the sub-pixels located at the corners of the display substrate, thereby providing good protection for the sub-pixels located at the corners and preventing GDS defects from occurring at the corners of the display substrate. The line width of the connecting line 1102 can be equal to the line width of the shielding line 1101. For example, the difference between the line width of the connecting line 1102 and the line width of the shielding line 1101 can be less than or equal to 10%. The line width can be the dimension of the shielding line 1101 or the connecting line 1102 in a direction perpendicular to its own extension direction within the plane of the substrate.

[0091] In an exemplary embodiment, Figure 6 As shown, the circuit structure layer may include multiple vias K, and the multiple vias K may realize connections between different layers, or may not realize connections, such as dummy holes. The distance between the electrostatic absorption unit 191 and the nearest via K is a first distance L1, and the first distance L1 may be greater than or equal to 5.4 microns. For example, the first distance L1 may be greater than or equal to 6 microns. The first distance L1 may be the minimum distance between the edge of the electrostatic absorption unit 191 and the edge of the via K. The distance between the connecting line 1102 and the nearest via K is a second distance L2, and the second distance L2 may be greater than or equal to 5.4 microns. For example, the second distance L2 may be greater than or equal to 6 microns. The second distance L2 may be the minimum distance between the edge of the connecting line 1102 and the edge of the via K. The sizes of the first distance L1 and the second distance L2 can be set as needed, so that there are no vias within a certain distance near the electrostatic absorption unit 191 and the connecting line 1102, and there are no weak locations in the film layer above and near the electrostatic absorption unit 191 and the connecting line 1102, thereby avoiding damage to the film layer near the electrostatic absorption unit 191 and the connecting line 1102 by static electricity. Figure 6 In the description, the via K closest to the electrostatic absorption unit 191 and the connecting line 1102 is taken as the same via hole. The via K closest to the electrostatic absorption unit 191 and the connecting line 1102 can be different via holes, and the present invention does not limit this.

[0092] In an exemplary embodiment, Figure 6As shown, the orthographic projection shape of the electrostatic absorption unit 191 on the substrate can be a circle, and the diameter of the circle can be greater than or equal to 5.4 microns and less than or equal to 6.6 microns. For example, the diameter of the circle can be approximately 6 microns. In other embodiments, the orthographic projection shape of the electrostatic absorption unit 191 on the substrate can be an ellipse, or any internal angle of the orthographic projection shape of the electrostatic absorption unit 191 on the substrate can be greater than or equal to 120 degrees. The electrostatic absorption unit 191 does not have a sharp point, which can reduce damage to the film layer during the static electricity release process. The shape and size of the electrostatic absorption unit 191 can be set as needed, and the present invention does not impose any restrictions on this.

[0093] Figure 7 In an exemplary embodiment Figure 6 The cross-sectional view taken along the CC axis omits the film layer of the display substrate. Figure 7 and Figure 5 The difference is that the structure of the peripheral area PA is added, and the remaining film layers of the display substrate, the circuit structure layer 12 and the light emitting structure layer 13 are omitted. Figure 5 The same as in , no further description is given here.

[0094] like Figure 7 As shown, the electrostatic absorption unit 191 is located in the peripheral area PA and is connected to the shielding line 1101 via a connecting line 1102. A first buffer layer 110, a first gate insulating layer 101, a second gate insulating layer 102, a first interlayer insulating layer 103, a second buffer layer 104, a third gate insulating layer 105, a second interlayer insulating layer 106, a passivation layer 107, and a first planarization layer 108 can be sequentially provided on the side of the electrostatic absorption unit 191 and the connecting line 1102 away from the base substrate 10. Except for the first planarization layer 108, the remaining film layers are inorganic insulating layers that can effectively block the intrusion of water and oxygen. A metal layer may not be provided on the side of the electrostatic absorption unit 191 and the connecting line 1102 away from the base substrate 10 to avoid generating induced charges with the electrostatic absorption unit 191 and the connecting line 1102. Alternatively, a metal layer may be provided on the side of the electrostatic absorption unit 191 and the connecting line 1102 away from the base substrate 10 if no induced charges are generated. This is not a limitation of the present invention. There is no via on the side of the electrostatic absorption unit 191 and the connecting line 1102 away from the base substrate 10. The via K closest to the electrostatic absorption unit 191 can be a dummy hole and does not serve as a connection. The minimum distance between the edge of the electrostatic absorption unit 191 and the edge of the closest via K, i.e., the first distance L1, can be greater than or equal to 5.4 microns. The edge of the via K can be the edge of the orthographic projection of the via K on the base substrate 10. Figure 7In the embodiment, the via K closest to the electrostatic absorption unit 191 passes through the first gate insulation layer 101, the second gate insulation layer 102, the first interlayer insulation layer 103, the second buffer layer 104, the third gate insulation layer 105, and the second interlayer insulation layer 106 in sequence, and extends to the interior of the first buffer layer 110. In other embodiments, the via K closest to the electrostatic absorption unit 191 can pass through different film layer thicknesses. The present invention does not limit the parameters such as the film layer, shape and size through which the via K passes.

[0095] In an exemplary embodiment, the thickness of the first interlayer insulating layer 103 can be greater than or equal to 500 nm, and the thickness of the second interlayer insulating layer 106 can be greater than or equal to 500 nm. In an exemplary embodiment, the thickness of the passivation layer 107 can be greater than or equal to 300 nm. This film thickness setting helps ensure that the film thickness on the side of the electrostatic absorption unit 191 and the connecting line 1102 away from the base substrate 10 is greater, improving the film's water vapor resistance and resistance to electrostatic damage. The thickness of each film layer can be set as needed, and this is not limited by the present invention.

[0096] The present invention also provides a display device comprising the display substrate described in any of the above embodiments. The display device can be any product or component with a display function, such as an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, etc., but the present invention is not limited thereto.

[0097] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are illustrative and cannot be understood as limitations on the present invention. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A display substrate, characterized in that: include: A base substrate, comprising a display area and a peripheral area surrounding the display area; A plurality of sub-pixels are located on one side of the base substrate and in the display area; a light shielding portion, located on a side of the plurality of sub-pixels close to the base substrate and located in the display area; At least one electrostatic absorption unit is provided in the same layer as the light shielding portion and is connected to the light shielding portion, and is located in the peripheral area.

2. The display substrate according to claim 1, wherein: In a direction away from the base substrate, the display substrate includes a circuit structure layer and a light-emitting structure layer arranged in sequence, the circuit structure layer includes a bottom light-shielding metal layer; the light-shielding portion and the electrostatic absorption unit are located in the bottom light-shielding metal layer; the circuit structure layer includes a pixel driving circuit, the light-emitting structure layer includes a light-emitting element, and the pixel driving circuit is connected to the light-emitting element; The circuit structure layer includes a plurality of vias perpendicular to the base substrate; In the plane of the base substrate, the distance between the electrostatic absorption unit and the nearest via is greater than or equal to 5.4 microns, and the distance between the electrostatic absorption unit and the nearest via is the minimum distance between the edge of the electrostatic absorption unit and the edge of the via.

3. The display substrate according to claim 2, wherein: The bottom light-shielding metal layer further includes a connecting line, and the electrostatic absorption unit is connected to the light-shielding portion via the connecting line.

4. The display substrate according to claim 3, wherein: The shading portion includes a shading line extending along the second direction, and the electrostatic absorption unit is connected to the shading portion through the connecting line, including: a first end of the connecting line is connected to the shading line, and a second end of the connecting line is connected to the electrostatic absorption unit.

5. The display substrate according to claim 4, wherein: The distance between the connecting line and the nearest via hole is greater than or equal to 5.4 micrometers, and the distance between the connecting line and the nearest via hole is the minimum distance between an edge of the connecting line and an edge of the via hole.

6. The display substrate according to claim 2, wherein: The peripheral area includes a driving circuit area, the driving circuit area is located on at least one side of the display area along the first direction, and at least one electrostatic absorption unit is located between the display area and the driving circuit area.

7. The display substrate according to claim 6, wherein: The peripheral area includes a left frame and a right frame located on both sides of the display area along the first direction, and an upper frame and a lower frame located on both sides of the display area along the second direction, the left frame, the right frame, the upper frame and the lower frame intersect with each other to form four corners; the first direction and the second direction intersect; at least one electrostatic absorption unit is provided at at least one of the corners.

8. The display substrate according to claim 2, wherein: The orthographic projection shape of the electrostatic absorption unit on the base substrate is circular or elliptical; or, any inner angle of the orthographic projection shape of the electrostatic absorption unit on the base substrate is greater than or equal to 120 degrees.

9. The display substrate according to claim 8, wherein: The orthographic projection shape of the electrostatic absorption unit on the base substrate is a circle, and the diameter of the circle is greater than or equal to 5.4 micrometers and less than or equal to 6.6 micrometers.

10. The display substrate according to claim 8, wherein On the side of the electrostatic absorption unit away from the base substrate, the circuit structure layer includes a first buffer layer, a first gate insulation layer, a second gate insulation layer, a first interlayer insulation layer, a second buffer layer, a third gate insulation layer, a second interlayer insulation layer, a passivation layer and a first flat layer arranged in sequence.

11. The display substrate according to claim 10, wherein: The thickness of the first interlayer insulating layer is greater than or equal to 500 nm. The thickness of the first interlayer insulating layer is the distance between a surface of the first interlayer insulating layer close to the base substrate and a surface of the first interlayer insulating layer away from the base substrate.

12. The display substrate according to claim 10, wherein: The thickness of the second interlayer insulating layer is greater than or equal to 500 nm. The thickness of the second interlayer insulating layer is the distance between a surface of the second interlayer insulating layer close to the base substrate and a surface of the second interlayer insulating layer away from the base substrate.

13. The display substrate according to claim 10, wherein: The thickness of the passivation layer is greater than or equal to 300 nm, and the thickness of the passivation layer is the distance between a surface of the passivation layer close to the substrate and a surface of the passivation layer away from the substrate.

14. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 13.

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