Staggered series buck-boost switching power supply converter

Abstract

The utility model discloses a staggered series buck-boost switching power supply converter. Comprising a first switch module, a second switch module, a third switch module, a fourth switch module, a first inductor module, a second inductor module, a first capacitor module, a second capacitor module, a third capacitor module, a fourth capacitor module, a first one-way conduction module, a second one-way conduction module, a third one-way conduction module and a fourth one-way conduction module. The control end of the first switch module and the control end of the second switch module receive the same first control signal, the control end of the third switch module and the control end of the fourth switch module receive the same second control signal, and the first control signal and the second control signal are different in phase. According to the technical scheme, the voltage stress of components in the circuit can be reduced, components with low withstand voltage are allowed to be used, and the cost of the whole circuit is remarkably reduced.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and in particular relates to an interleaved series buck-boost switching power supply converter. Background Art

[0002] In the existing technology, in DC / DC application scenarios with wide range of DC input and DC output, Buck-Boost switching power converter is generally selected as the main circuit topology, such as Figure 1 As shown, the conventional buck-boost switching power converter includes a control module 10, a drive module 20, a transistor Q1, a transistor Q2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, an inductor L1, a diode D1, and a diode D2. Transistor Q1 and transistor Q2 are N-channel field-effect transistors, and transistor Q1 and transistor Q2 are turned on or off at the same time. It can be seen that there are the following two operating modes:

[0003] Operating Mode 1: The output voltage U (voltage at point VD) of control module 10 is high, and transistors Q1 and Q2 are simultaneously on. This high voltage persists within a switching cycle T for the duration of the on-time period Ton. At this point, the maximum voltage across inductor L1 is equal to the input voltage U(V1).

[0004] Working mode 2: the output voltage U of the control module 10 is at a low level, and the two transistors Q1 and Q2 are turned off at the same time. The duration of this low level within a switching cycle T is the turn-off period Toff.

[0005] At this time, the maximum voltage value across the inductor L1 is the output voltage value U(VO).

[0006] Based on the aforementioned operating principle of the buck-boost switching power converter, the inductor L1 is designed to have a continuous current waveform at a certain load current. Based on the volt-second flux balance principle of the inductor L1 magnetic flux, circuit analysis shows that the input and output voltage RMS relationship of the switching power converter is as follows:

[0007] U RMS (VO)=U RMS (VI)*D*η / (1-D) Formula 1

[0008] Meaning of symbols in formula 1: U RMS (VI) is the effective value of the input voltage of the switching power converter, U RMS(VO) is the effective value of the output voltage of the switching power converter, D is the waveform duty cycle of the square wave voltage U output by the control module 10, D=Ton / (Ton+Toff)=Ton / T, and η is the conversion efficiency of the switching power converter.

[0009] From formula 1, we can see that assuming the conversion efficiency of the power converter is η=1, when the duty cycle D>0.5, U RMS (VO)>U RMS (VI), the power converter is in the boost state. When the duty cycle D<0.5, U RMS (VO) RMS (VI), the power converter is in the step-down state. Therefore, the Buck-Boost switching power converter is suitable for applications with a wide input voltage range.

[0010] pass Figure 1 The circuit and the above two working mode analysis show the following characteristics:

[0011] The maximum voltage that transistor Q1 needs to withstand between the drain D and source S when it is turned off, the maximum voltage that diode D1 needs to withstand when it is reverse-cut off, and the maximum voltage across inductor L1 are as follows:

[0012] U MAX (DS-Q1)≈U MAX (D1)≈U MAX (L)≈U MAX (VI).

[0013] The maximum voltage value that transistor Q2 needs to withstand between the drain D and the source S when it is turned off and the maximum voltage value that diode D2 needs to withstand when it is reverse-cut off are as follows:

[0014] U MAX (DS-Q2)≈U MAX (D2)≈U MAX (VO).

[0015] When transistors Q1 and Q2 are turned on, the maximum current flowing between their drain D and source S is:

[0016] I MAX (DS-Q1)=I MAX (DS-Q2)=I MAX (VI)=I MAX (L).

[0017] In order to meet the requirements of being applicable in multiple scenarios such as new energy power generation equipment such as wind power and solar power, as well as in new energy storage equipment and electric vehicle drive equipment, some DC / DC switching power converters have an input operating voltage range of approximately DC 200V to 1700V.​

[0018] As analyzed above, when the above Figure 1 The Buck-Boost switching power converter shown in the figure is used in scenarios where the input voltage U(VI) is high (for example, 1700V). Therefore, NMOSFET transistors with higher withstand voltage specifications (for example, a drain D and source S withstand voltage greater than 1700V) are required. For example: Figure 1 Transistor Q1 in the circuit. However, the currently available, low-cost, general-purpose NMOSFETs manufactured on a large scale do not meet this withstand voltage requirement. If a custom-made, high-voltage NMOSFET (e.g., greater than 2000V) produced in very small quantities were used, its cost would be far beyond the acceptable price range for market users, making it unsuitable for large-scale deployment. Therefore, this approach is not economically viable.

[0019] In summary, with the development of social, economic and technological development, especially the rapid popularization of clean energy power generation equipment such as wind power and solar energy and new electrical equipment such as new energy vehicles, it is necessary to select new DC / DC switching power converters with general-purpose, low-cost, low-voltage (for example, less than 1000V) NMOSFET transistors to adapt to the high voltage input requirements in the above application scenarios, so as to achieve the goal of further reducing costs and promote better and faster development of social and economic aspects such as clean energy and low carbon. Utility Model Content

[0020] The embodiment of the present invention provides a staggered series buck-boost switching power converter to solve the above technical problems.

[0021] A first aspect of an embodiment of the present invention provides a staggered series buck-boost switching power converter, the staggered series buck-boost switching power converter comprising a first switch module, a second switch module, a third switch module, a fourth switch module, a first inductor module, a second inductor module, a first capacitor module, a second capacitor module, a third capacitor module, a fourth capacitor module, a first unidirectional conduction module, a second unidirectional conduction module, a third unidirectional conduction module, and a fourth unidirectional conduction module;

[0022] A first end of the first capacitor module is connected to a first end of the first switch module; a second end of the first capacitor module is respectively connected to a first end of the second capacitor module, an input end of the first unidirectional conduction module, an output end of the fourth unidirectional conduction module, a second end of the second switch module, a first end of the third switch module, a second end of the third capacitor module, and a first end of the fourth capacitor module; a second end of the first switch module is respectively connected to a first end of the first inductor module and an output end of the first unidirectional conduction module; a second end of the first inductor module is respectively connected to an input end of the second unidirectional conduction module and a first end of the second switch module; an output end of the second unidirectional conduction module is connected to a first end of the third capacitor module; a second end of the second capacitor module is connected to a second end of the fourth switch module; a first end of the fourth switch module is respectively connected to an input end of the fourth unidirectional conduction module and a first end of the second inductor module; a second end of the second inductor module is respectively connected to a second end of the third switch module and an output end of the third unidirectional conduction module; and an input end of the third unidirectional conduction module is connected to a second end of the fourth capacitor module;

[0023] The control end of the first switch module and the control end of the second switch module receive the same first control signal, the control end of the third switch module and the control end of the fourth switch module receive the same second control signal, and the phases of the first control signal and the second control signal are different.

[0024] A second aspect of an embodiment of the present invention provides a staggered series buck-boost switching power converter, the staggered series buck-boost switching power converter comprising a first switch module, a second switch module, a third switch module, a fourth switch module, a first inductor module, a second inductor module, a first capacitor module, a second capacitor module, a third capacitor module, a fourth capacitor module, a ninth switch module, a tenth switch module, an eleventh switch module, and a twelfth switch module;

[0025] The first end of the first capacitor module is connected to the first end of the first switch module. The second end of the first capacitor module is respectively connected to the first end of the second capacitor module, the input end of the ninth switch module, the output end of the twelfth switch module, the second end of the second switch module, the first end of the third switch module, the second end of the third capacitor module, and the first end of the fourth capacitor module. The second end of the first switch module is respectively connected to the first end of the first inductor module and the output end of the ninth switch module. The second end of the first inductor module is respectively connected to the input end of the tenth switch module and the first end of the second switch module. The output end of the tenth switch module is connected to the first end of the third capacitor module. The second end of the second capacitor module is connected to the second end of the fourth switch module. The first end of the fourth switch module is respectively connected to the input end of the twelfth switch module and the first end of the second inductor module. The second end of the second inductor module is respectively connected to the second end of the third switch module and the output end of the eleventh switch module. The input end of the eleventh switch module is connected to the second end of the fourth capacitor module.

[0026] The control end of the first switch module and the control end of the second switch module receive the same first control signal, the control end of the third switch module and the control end of the fourth switch module receive the same second control signal, and the first control signal and the second control signal have different phases;

[0027] The on-off state of the ninth switch module and the tenth switch module is opposite to the on-off state of the first switch module and the second switch module;

[0028] The on-off state of the eleventh switch module and the twelfth switch module is opposite to the on-off state of the third switch module and the fourth switch module.

[0029] The technical effects of the embodiments of the present utility model are as follows: the present technical solution can reduce the voltage stress of components. In the present embodiment, the maximum voltage values ​​borne by the switch module, the unidirectional conduction module and the inductor module at both ends are greatly reduced compared with the prior art, allowing the use of components with lower withstand voltages. Since the voltage that the components need to withstand is reduced, the present embodiment can use general-purpose, low-cost transistors, diodes and inductors without relying on special components with high withstand voltages, significantly reducing the cost of the overall circuit. Since there is a phase difference between the two control signals of the present embodiment, the output voltage noise can be greatly reduced compared with the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 This is a circuit diagram of a switching power converter provided by the prior art of the utility model;

[0032] Figure 2 This is a schematic structural diagram of a staggered series buck-boost switching power converter provided by the first embodiment of the present invention;

[0033] Figure 3 This is a current flow diagram of the first current loop during the operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0034] Figure 4 This is a current flow diagram of the second current loop during the operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0035] Figure 5 This is a current flow diagram of the third current loop during the operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0036] Figure 6 This is a current flow diagram of the fourth current loop during operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0037] Figure 7 This is a current flow diagram of the fourth current loop during operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0038] Figure 8 This is a current flow diagram of the eighth current loop during operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present utility model;

[0039] Figure 9 This is a current flow diagram of the ninth current loop during operation of an interleaved series buck-boost switching power converter provided by the first embodiment of the present utility model;

[0040] Figure 10 This is another structural diagram of an interleaved series buck-boost switching power converter provided by the first embodiment of the present utility model;

[0041] Figure 11This is a structural diagram of a first driving module in a staggered series buck-boost switching power converter provided by the first embodiment of the present invention;

[0042] Figure 12 This is a circuit diagram of a first driving module in a staggered series buck-boost switching power converter provided by the first embodiment of the present invention;

[0043] Figure 13 This is a structural diagram of a second driving module in a staggered series buck-boost switching power converter provided by the first embodiment of the present invention;

[0044] Figure 14 This is a circuit diagram of a second driving module in a staggered series buck-boost switching power converter provided by the first embodiment of the present invention;

[0045] Figure 15 This is another structural diagram of an interleaved series buck-boost switching power converter provided by the first embodiment of the present utility model;

[0046] Figure 16 This is a structural diagram of an isolated current signal sampling module in an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0047] Figure 17 This is a circuit diagram of an isolated current signal sampling module in an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0048] Figure 18 This is a circuit diagram of an interleaved series buck-boost switching power converter provided by the first embodiment of the present invention;

[0049] Figure 19 yes Figure 18 The waveform diagram of the drive signals VD1 and VD2 output by the control module in FIG.

[0050] Figure 20 yes Figure 18 A waveform diagram of the driving signals output by the first driving module and the second driving module;

[0051] Figure 21 yes Figure 18 Voltage waveforms of transistors Q1 to Q4, diodes D1 and D2, and input voltage;

[0052] Figure 22 yes Figure 18 The current waveforms of capacitors C1 to C4 and inductors L1 and L2 in FIG.

[0053] Figure 23 yes Figure 18The voltage waveforms of capacitors C1 to C4, inductors L1 and L2, and the output voltage;

[0054] Figure 24 This is a schematic structural diagram of a staggered series buck-boost switching power converter provided by the second embodiment of the present utility model;

[0055] In the figure: 10, control module; 20, first drive module; 30, second drive module; 40, isolated current signal sampling module; 101, first switch module; 102, second switch module; 103, third switch module; 104, fourth switch module; 105, first inductor module; 106, second inductor module; 107, first capacitor module; 108, second capacitor module; 109, third capacitor module; 110, fourth capacitor module; 111, first unidirectional conduction module; 112 , second unidirectional conduction module; 113, third unidirectional conduction module; 114, fourth unidirectional conduction module; 121, ninth switch module; 122, tenth switch module; 123, eleventh switch module; 124, twelfth switch module; 201, fifth switch module; 202, sixth switch module; 203, first voltage transformation and isolation module; 301, seventh switch module; 302, eighth switch module; 303, second voltage transformation and isolation module; 401, current transformer; 402, sampling resistor. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0057] Example 1

[0058] The first embodiment of the present invention provides a staggered series buck-boost switching power supply converter, such as Figure 2 As shown, it includes a first switch module 101, a second switch module 102, a third switch module 103, a fourth switch module 104, a first inductor module 105, a second inductor module 106, a first capacitor module 107, a second capacitor module 108, a third capacitor module 109, a fourth capacitor module 110, a first unidirectional conduction module 111, a second unidirectional conduction module 112, a third unidirectional conduction module 113 and a fourth unidirectional conduction module 114;

[0059] The first end of the first capacitor module 107 is connected to the first end of the first switch module 101, the second end of the first capacitor module 107 is respectively connected to the first end of the second capacitor module 108, the input end of the first unidirectional conduction module 111, the output end of the fourth unidirectional conduction module 114, the second end of the second switch module 102, the first end of the third switch module 103, the second end of the third capacitor module 109 and the first end of the fourth capacitor module 110, the second end of the first switch module 101 is respectively connected to the first end of the first inductor module 105 and the output end of the first unidirectional conduction module 111, the second end of the first inductor module 105 is respectively connected to the first end of the second inductor module 105 ... The input end of the second unidirectional conduction module 112 is connected to the first end of the second switch module 102, and the output end of the second unidirectional conduction module 112 is connected to the first end of the third capacitor module 109. The second end of the second capacitor module 108 is connected to the second end of the fourth switch module 104. The first end of the fourth switch module 104 is respectively connected to the input end of the fourth unidirectional conduction module 114 and the first end of the second inductor module 106. The second end of the second inductor module 106 is respectively connected to the second end of the third switch module 103 and the output end of the third unidirectional conduction module 113. The input end of the third unidirectional conduction module 113 is connected to the second end of the fourth capacitor module 110.

[0060] The control end of the first switch module 101 and the control end of the second switch module 102 receive the same first control signal, the control end of the third switch module 103 and the control end of the fourth switch module 104 receive the same second control signal, and the first control signal and the second control signal have different phases.

[0061] Among them, the first switch module 101, the second switch module 102, the third switch module 103, and the fourth switch module 104 are generally composed of MOSFET transistors, triodes or IGBT tubes, and are used to turn on or off under the drive of the control signal, thereby controlling the energy storage and release in the inductor module. The first inductor module 105 and the second inductor module 106 are used to store and release energy during the switching cycle and smooth the current. The inductor module stores and releases energy in each switching cycle to help achieve voltage rise and fall conversion, while reducing current ripple and protecting the load equipment. The first capacitor module 107, the second capacitor module 108, the third capacitor module 109, and the fourth capacitor module 110 are used to store energy and provide voltage support. These capacitors can also filter out high-frequency noise and voltage ripple, ensure stable input and output voltages, and improve the overall performance of the circuit. The first unidirectional conduction module 111, the second unidirectional conduction module 112, the third unidirectional conduction module 113, and the fourth unidirectional conduction module 114 are usually composed of diodes, which are used to conduct current in a specific direction of flow to prevent reverse current. The unidirectional conduction modules ensure that the current flows in the intended path to prevent reverse current from damaging the circuit, so that the converter can correctly implement specific functions in different time periods in different working modes.

[0062] The working principle of the first embodiment is described by taking the first capacitor module 107 as capacitor C1, the second capacitor module 108 as capacitor C2, the third capacitor module 109 as capacitor C3, the fourth capacitor module 110 as C4, the first inductor module 105 as inductor L1, the second inductor module 106 as inductor L2, the first unidirectional conduction module 111 as diode D1, the second unidirectional conduction module 112 as diode D2, the third unidirectional conduction module 113 as diode D3, the fourth unidirectional conduction module 114 as diode D4, the first switch module 101 as transistor Q1, the second switch module 102 as transistor Q2, the third switch module 103 as transistor Q3, and the fourth switch module 104 as transistor Q4 as an example. The capacitance of the capacitor C1 and the capacitance of the capacitor C2 are selected to be equal, and the capacitance of the third capacitor module 109 and the capacitance of the fourth capacitor module 110 are selected to be equal.

[0063] According to the circuit principle, the relationship between the effective values ​​of the voltages across capacitors C1, C2, C3, and C4 and the input voltage VI and output voltage VO, respectively, can be seen in Formula 2 and Formula 3:

[0064] U RMS (C1)≈U RMS (C2)≈U RMS (VI) / 2 Formula 2

[0065] U RMS (C3)≈U RMS (C4)≈U RMS (VO) / 2 Formula 3

[0066] For ease of understanding, a simplified analysis is performed, selecting capacitors C1 = C2 and C3 = C4, and selecting the parameters of inductors L1 and L2 so that when the output current is greater than a preset value, the currents in inductors L1 and L2 are continuous waveforms. Based on formulas 1, 2, and 3, circuit analysis shows that the voltage RMS conversion relationship calculation process in this embodiment is as shown in formula 4:

[0067] U RMS (VO)=U RMS (C 3)+U RMS (C 4) = 2*U RMS (C 3)

[0068] =2*U RMS (C 1)*D*η / (1-D)=2*[U RMS (VI) / 2]*D*η / (1-D)

[0069] =U RMS (VI)*D*η / (1-D) Formula 4

[0070] It can be seen that the voltage effective value conversion relationship calculation formula 4 of this embodiment is consistent with the prior art Figure 1 The voltage conversion relationship calculation formula in the circuit is the same as 1. Therefore, this embodiment 1 can achieve the same Figure 1 The circuit functions exactly the same way.

[0071] When the capacitance values ​​C1 = C2 and C3 = C4, and based on the general power converter specifications that require the ratio of the ripple voltage on the input and output capacitors to their effective voltage values ​​to be extremely small (generally less than 1%), the ripple voltage can be ignored when calculating the maximum voltage on the capacitors. Circuit analysis reveals that this embodiment also has the following features:

[0072] The relationship between the maximum voltage that transistors Q1 and Q4 need to withstand between their drains D and sources S, the maximum voltage that diodes D1 and D4 need to withstand when they are reverse-blocked, and the maximum voltage across inductors L1 and L2 is as follows:

[0073] U MAX (DS-Q1)≈U MAX (DS-Q4)≈U MAX (D1)≈U MAX (D4)

[0074] ≈U MAX (L1)≈U MAX (L2)≈U MAX (C1)≈U MAX (C2)≈U MAX (VI) / 2

[0075] The relationship between the maximum voltage that transistors Q2 and Q3 need to withstand between their drains D and sources S and the maximum voltage that diodes D2 and D3 need to withstand when they are reverse-blocked is as follows:

[0076] U MAX (DS-Q2)≈U MAX (DS-Q3)≈U MAX (D2)

[0077] ≈U MAX (D3)≈U MAX (C3)≈U MAX (C4)≈U MAX (VO) / 2

[0078] The maximum current values ​​flowing between the drain D and source S of transistors Q1, Q2, Q3, and Q4 are as follows:

[0079] I MAX(DS-Q1)≈I MAX (DS-Q2)≈I MAX (DS-Q3)≈I MAX (DS-Q4)

[0080] ≈I MAX (L1)≈I MAX (L2)≈I MAX (VI)

[0081] In summary, the voltage between the drain D and the source S of the transistor Q1 and the transistor Q4 in the first embodiment is reduced to the voltage of the prior art. Figure 1 The voltage between the drain D and source S of the transistor Q1 in the circuit is half of the voltage value; and the voltage between the drain D and source S of the transistor Q2 and the transistor Q3 in the first embodiment is reduced to the voltage of the prior art. Figure 1 Half the voltage between the drain D and source S of transistor Q2 in the circuit.

[0082] When parameters C1=C2, C3=C4, and L1=L2 are selected, and the current in inductors L1 and L2 is continuous, circuit analysis shows that the current waveform I(DS, Q*) flowing through the drain D and source S of transistors Q1-Q4 is a sawtooth wave. Within one period T, this sawtooth wave has a width of Ton.

[0083] According to the above formulas, equations, parameter conditions, and the law of conservation of energy, the relationship between the voltage and current values ​​of the first embodiment when the currents of the inductor L1 and the inductor L2 are continuous and steady is as shown in Formula 5:

[0084] ∵{U RMS (C 1)*[I MIN (DS-Q 1)+I MAX (DS-Q 1)] / 2}*η*Ton

[0085] +{U RMS (C 2)*[I MIN (DS-Q 4)+I MAX (DS-Q 4)] / 2}*η*Ton

[0086] ={U RMS (C 1)*[I MIN (L 1)+I MAX (L 1)] / 2}*η*Ton

[0087] +{U RMS (C 2)*[I MIN (L 2)+I MAX (L 2)] / 2}*η*Ton

[0088] ={URMS (C 1)*[I MIN (L 1)+I MAX (L 1)]}*η*Ton

[0089] ={U RMS (C 2)*[I MIN (L 2)+I MAX (L 2)]}*η*Ton

[0090] =U RMS (VI)*I AVG (L 1)*η*Ton=U RMS (VO)*I RMS (O)*T

[0091] ∴I RMS (O)=U RMS (VI)*I AVG (L 1)*η*Ton / T / U RMS (VO)

[0092] =I AVG (L 1)*(1-D)=I AVG (L 2)*(1-D)

[0093] From formula 5, we can know that under the above conditions, the output current effective value I of this embodiment is RMS (O) are the average current I flowing through the inductor L1 AVG (L1) and the average current I flowing through the inductor L2 AVG (1-D) times of (L2).

[0094] As described above, when the input voltage, output voltage and output current parameters of the switching power converter are the same, the maximum current flowing between the drain D and source S of the transistors Q1-Q4 in this embodiment is the same as Figure 1 In the prior art, the maximum current values ​​flowing between the drain D and the source S of the transistors Q1-Q2 are substantially the same.

[0095] Therefore, when the input voltage of the switching power converter is high, the transistors Q1-Q4 of the circuit of the embodiment are larger than those of the prior art. Figure 1 The maximum withstand voltage value Umax(DS-Q*) of the transistors Q1-Q2 is reduced to one half, while the maximum allowable current value Imax(DS-Q*) remains unchanged.

[0096] Therefore, this embodiment 1 can use a general-purpose, low-cost NMOSFET transistor. Compared with the prior art, this embodiment 1 has a significantly reduced cost and a significantly improved reliability.

[0097] As mentioned above, in the first embodiment, the maximum voltage value that the diode D1 and the diode D4 need to withstand when they are reverse cut off is reduced to the existing technology. Figure 1 The maximum voltage that diode D1 in the circuit needs to withstand when it is reverse cutoff is half of the maximum voltage value. The maximum voltage that diode D2 and diode D3 need to withstand when they are reverse cutoff is reduced to the existing technology. Figure 1 When the diode D2 in the circuit is reverse-blocked, it needs to withstand half of the maximum voltage. Therefore, when the input voltage of the switching power converter is high, this embodiment can use a general-purpose, low-cost diode with a low withstand voltage.

[0098] As mentioned above, in the first embodiment, the maximum voltage value borne by the inductor L1 and the inductor L2 is reduced to the existing technology. Figure 1 Therefore, when the input voltage of the switching power converter is high, a general-purpose, low-voltage, low-cost inductor with a mature manufacturing process can be selected in this embodiment.

[0099] The first control signal and the second control signal have different phases. Within a working cycle, the working process of this embodiment can be divided into the following different working modes:

[0100] The first working mode: The first control signal is an on control signal, and the second control signal is an off control signal. At this time, the first switch module 101 and the second switch module 102 are on, and the third switch module 103 and the fourth switch module 104 are off, including the following current loop:

[0101] like Figure 3 As shown, the first capacitor module 107, the first switch module 101, the first inductor module 105, and the second switch module 102 form a first current loop. When the first current loop is in operation, the two ends of the coil of the first inductor module 105 are subjected to a positive voltage, the current flowing through the first inductor module 105 begins to increase, and the first inductor module 105 is in an energy storage increasing state.

[0102] like Figure 4 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the third capacitor module 109, the load module 120, and the third unidirectional conduction module 113 form a second current loop. When the second current loop is in operation, the second inductor module 106 and the third capacitor module 109 together supply power to the load module 120.

[0103] like Figure 5 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the fourth capacitor module 110, and the third unidirectional conduction module 113 form a third current loop. When the third current loop is in operation, the second inductor module 106 charges the fourth capacitor module 110.

[0104] Second working mode: The first control signal is a shutdown control signal, and the second control signal is a shutdown control signal. In this case, the first switch module 101 and the second switch module 102 are turned off, and the third switch module 103 and the fourth switch module 104 are turned off. According to the energy state of the second inductor module 106, there are two cases:

[0105] The first situation: the energy of the second inductor module 106 has not been completely released.

[0106] like Figure 6 As shown, the first inductor module 105, the second unidirectional conduction module 112, the third capacitor module 109, and the first unidirectional conduction module 111 form a fourth current loop. When the fourth current loop is in operation, the first inductor module 105 charges the third capacitor module 109.

[0107] like Figure 7 As shown, the first inductor module 105, the second unidirectional conduction module 112, the load module 120, the third unidirectional conduction module 113, the second inductor module 106, the fourth unidirectional conduction module 114, and the first unidirectional conduction module 111 form a fifth current loop. When the fifth current loop is in operation, the first inductor module 105 and the second inductor module 106 supply power to the load module.

[0108] like Figure 5 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the fourth capacitor module 110, and the third unidirectional conduction module 113 form a sixth current loop. When the sixth current loop is in operation, the second inductor module 106 charges the fourth capacitor module 110.

[0109] The second situation: the energy of the second inductor module 106 is completely released.

[0110] like Figure 6 As shown, the first inductor module 105, the second unidirectional conduction module 112, the third capacitor module 109, and the first unidirectional conduction module 111 form a seventh current loop. When the seventh current loop is in operation, the first inductor module 105 charges the third capacitor module 109.

[0111] like Figure 8 As shown, the first inductor module 105, the second unidirectional conduction module 112, the load module 120, the fourth capacitor module 110, and the first unidirectional conduction module 111 form an eighth current loop. When the eighth current loop is in operation, the first inductor module 105 and the fourth capacitor module 110 together supply power to the load module.

[0112] The third working mode: the first control signal is a shut-off control signal, and the second control signal is a conduction control signal. In this case, the first switch module 101 and the second switch module 102 are shut off, and the third switch module 103 and the fourth switch module 104 are conducted.

[0113] like Figure 9 As shown, the second capacitor module 108, the third switch module 103, the second inductor module 106, and the fourth switch module 104 form a ninth current loop. When the ninth current loop is operating, the current flowing through the second inductor module 106 begins to increase, and the second inductor module 106 is in an energy storage increasing state.

[0114] like Figure 4 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the third capacitor module 109, the load module 120, and the third unidirectional conduction module 113 form a tenth current loop. When the tenth current loop is working, the second inductor module 106 and the third capacitor module 109 together supply power to the load module.

[0115] like Figure 6 As shown, the first inductor module 105, the second unidirectional conduction module 112, the third capacitor module 109, and the first unidirectional conduction module 111 form an eleventh current loop. When the eleventh current loop is in operation, the first inductor module 105 charges the third capacitor module 109.

[0116] Fourth working mode: When the first control signal is a shutdown control signal and the second control signal is a shutdown control signal, the first switch module 101 and the second switch module 102 are turned off, and the third switch module 103 and the fourth switch module 104 are turned off. There are two cases according to the energy state of the first inductor module 105:

[0117] The first situation: the energy of the first inductor module 105 has not been completely released.

[0118] like Figure 5 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the fourth capacitor module 110, and the third unidirectional conduction module 113 form a twelfth current loop. When the twelfth current loop is in operation, the second inductor module 106 charges the fourth capacitor module 110.

[0119] like Figure 7 As shown, the first inductor module 105, the second unidirectional conduction module 112, the load module 120, the third unidirectional conduction module 113, the second inductor module 106, the fourth unidirectional conduction module 114, and the first unidirectional conduction module 111 form a thirteenth current loop. When the thirteenth current loop is in operation, the first inductor module 105 and the second inductor module 106 supply power to the load module 120.

[0120] like Figure 6 As shown, the first inductor module 105, the second unidirectional conduction module 112, the third capacitor module 109, and the first unidirectional conduction module 111 form a fourteenth current loop. When the fourteenth current loop is in operation, the first inductor module 105 charges the third capacitor module 109.

[0121] The second situation: the energy of the first inductor module 105 is completely released.

[0122] like Figure 5 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the fourth capacitor module 110, and the fourth unidirectional conduction module 114 form a fifteenth current loop. When the fifteenth current loop is in operation, the second inductor module 106 charges the fourth capacitor module 110.

[0123] like Figure 4 As shown, the second inductor module 106, the fourth unidirectional conduction module 114, the third capacitor module 109, the load module 120, and the third unidirectional conduction module 113 form a sixteenth current loop. When the sixteenth current loop is in operation, the second inductor module 106 supplies power to the load module 120.

[0124] The technical effects of this embodiment are:

[0125] 1. Reducing the voltage stress of components. In this embodiment, the maximum voltage across transistors Q1-Q4, diodes D1-D4, and inductors L1 and L2 is reduced to half of the maximum voltage of the corresponding components in the prior art circuit. This effect of reducing voltage stress allows the use of components with lower withstand voltage.

[0126] 2. Use low-cost components. Since the voltage that the components need to withstand is reduced, this embodiment can use universal, low-cost NMOSFET transistors, diodes, and inductors without relying on special high-voltage components, significantly reducing the cost of the overall circuit.

[0127] 3. Maintaining the maximum current unchanged: Although the voltage stress is reduced, the maximum current flowing through transistors Q1-Q4 and inductors L1 and L2 remains essentially the same as in the prior art. The current handling capability of the circuit is not affected, maintaining the performance of the original circuit.

[0128] 4. Due to the phase difference between the two control signals of this embodiment, the noise voltage generated by the high-frequency charging current of the capacitors C3 and C4 on the equivalent circuit inductance and equivalent circuit resistance of the capacitors C3 and C4, after being connected in series, produces a peak-to-valley alternating complementary effect on the output voltage VO. Therefore, the output voltage noise of this embodiment is greatly reduced compared with the prior art.

[0129] 5. By reducing the voltage stress of components, this embodiment effectively improves the reliability of the circuit and reduces the risk of component failure caused by excessive voltage.

[0130] 6. This embodiment is particularly suitable for high input voltage scenarios and can use low-voltage components under high voltage conditions, further enhancing the adaptability and flexibility of the circuit.

[0131] As an implementation method, Figure 10 As shown, the staggered series buck-boost switching power converter further includes a control module 10, a first drive module 20 and a second drive module 30;

[0132] The output end of the control module 10 is respectively connected to the input end of the first driver module 20 and the input end of the second driver module 30. The first output end of the first driver module 20 is connected to the control end of the first switch module 101, the second output end of the first driver module 20 is connected to the second end of the first switch module 101, the third output end of the first driver module 20 is connected to the control end of the second switch module 102, the fourth output end of the first driver module 20 is connected to the second end of the second switch module 102, the first output end of the second driver module 30 is connected to the control end of the third switch module 103, the second output end of the second driver module 30 is connected to the second end of the third switch module 103, the third output end of the second driver module 30 is connected to the control end of the fourth switch module 104, and the fourth output end of the second driver module 30 is connected to the second end of the fourth switch module 104.

[0133] The control module 10 outputs a third control signal to the first driver module 20 and a fourth control signal to the second driver module 30. The first driver module 20 outputs a first control signal to the first switch module 101 and the second switch module 102 according to the third control signal, and the second driver module 30 outputs a second control signal to the third switch module 103 and the fourth switch module 104 according to the fourth control signal.

[0134] The third control signal and the first control signal are the same control signal, and the fourth control signal and the second control signal are the same control signal.

[0135] The control module 10 generates and outputs two control signals with a phase difference of 180°. This can be achieved by using a timer or a PWM (pulse width modulation) module. For example, many microcontrollers have built-in timers or PWM modules that can easily generate accurate control signals. Through appropriate configuration, two PWM signals with a phase difference of 180° can be generated. Specifically, a timer that supports PWM mode is selected, and the timer period is set so that it generates a PWM signal of the required frequency. Two PWM channels are set, each for generating two signals. By adjusting the phase offset of one PWM channel, two signals with a phase difference of 180° are generated.

[0136] The first driver module 20 receives the third control signal and converts it into a signal suitable for driving the first switch module 101 and the second switch module 102. The first driver module 20 ensures that the first switch module 101 and the second switch module 102 can be properly turned on and off when receiving the third control signal, thereby achieving charging and discharging control of the inductor module and the capacitor module.

[0137] The second driver module 30 receives the fourth control signal and converts it into a signal suitable for driving the third switch module 103 and the fourth switch module 104. The second driver module 30 ensures that the third switch module 103 and the fourth switch module 104 can be properly turned on and off when receiving the fourth control signal, thereby achieving charging and discharging control of the inductor module and the capacitor module.

[0138] The technical effect of this embodiment is that by using the same control signal, the design of the control module 10 can be simplified, and only a pair of control signals with a phase difference of 180° need to be generated instead of multiple different signals.

[0139] Ensuring that the first control signal and the third control signal, and the second control signal and the fourth control signal are identical can ensure the consistency of the control signals and avoid phase errors and time delays that may be caused by different signal sources.

[0140] The first driving module 20 and the second driving module 30 may have a variety of different structures to achieve corresponding driving functions and technical effects, including but not limited to the following structures:

[0141] 1. Optocoupler isolation structure: Use an optocoupler to achieve isolation and drive of the control signal. The output signal of the control module passes through the input end of the optocoupler, is isolated by the optocoupler, and then drives the switch tube at the output end.

[0142] 2. Transformer drive structure: The high-frequency transformation function of the transformer is used to achieve signal isolation and drive. The control signal passes through the primary coil of the transformer and generates a drive signal in the secondary coil after transformation. The signal of the secondary coil is rectified and filtered to drive the switching tube.

[0143] 3. Driver chip structure: A dedicated gate driver chip is used to drive the switch tube. The PWM signal output by the control module is input to the gate driver chip. After processing, the driver chip outputs a high-current, high-voltage drive signal to the switch tube.

[0144] 4. Inductive coupling structure: Inductive coupling is used to achieve signal isolation and drive. The control signal passes through the inductive coupler (such as a common-mode choke) to generate a drive signal on the isolated inductive side.

[0145] As an implementation method, Figure 11 As shown, the first driving module 20 includes a fifth switch module 201, a sixth switch module 202 and a first voltage transformation and isolation module 203;

[0146] A first end of the fifth switch module 201 is connected to a power supply voltage, a second end of the fifth switch module 201 is connected to a first end of the sixth switch module 202 and a first input end of the first voltage transformation and isolation module 203, respectively. The control end of the fifth switch module 201 and the control end of the sixth switch module 202 are commonly connected to the input end of the first driver module 20. The second end of the sixth switch module 202 and the second input end of the first voltage transformation and isolation module 203 are commonly connected to ground. The first output end of the first voltage transformation and isolation module 203 is the first output end of the first driver module 20. The second output end of the first voltage transformation and isolation module 203 is the second output end of the first driver module 20. The third output end of the first voltage transformation and isolation module 203 is the third output end of the first driver module 20. The fourth output end of the first voltage transformation and isolation module 203 is the fourth output end of the first driver module 20.

[0147] The fifth switch module 201 controls the flow of current. When the fifth switch module 201 is on, it provides a high-level voltage to the first voltage conversion and isolation module 203; when it is off, it provides no voltage. When the sixth switch module 202 is on, it provides a low-level voltage to the first voltage conversion and isolation module 203. The first voltage conversion and isolation module 203 isolates and converts electrical signals, converting input high- and low-level signals into multiple isolated output signals. When the fifth switch module 201 is on, the first voltage conversion and isolation module 203 outputs a high-level voltage. When the sixth switch module 202 is on, the first voltage conversion and isolation module 203 outputs a low-level voltage.

[0148] The technical effect of this embodiment is that the first driver module receives the third control signal from the control module, processes the signal through the fifth and sixth switch modules, isolates the processed control signal through the first voltage conversion and isolation module, and distributes it to different output terminals to drive the subsequent first and second switch modules. The first voltage conversion and isolation module achieves electrical isolation between the input and output signals, enhancing the reliability and anti-interference capabilities of the system. It can also generate multiple isolated output signals for driving different switch modules.

[0149] As an example, Figure 12 As shown, this is a circuit diagram of the first driving module 20, the fifth switch module 201 is an NPN transistor Q201, the sixth switch module 202 is a PNP transistor Q202, the first voltage transformation isolation module 203 is a transformer T201, and the first driving module 20 further includes a resistor R201, a resistor R202, a resistor R203, a resistor R204, a resistor R205, a resistor R206, a resistor R207, a diode D201, a diode D202, and a capacitor C201. One end of the resistor R201 is the input end of the first driving module 20, the other end of the resistor R201 is respectively connected to the base of the NPN transistor Q201 and the base of the PNP transistor Q202, the collector of the NPN transistor Q201 is connected to one end of the resistor R202, the other end of the resistor R202 is connected to the power supply voltage, the emitter of the NPN transistor Q201 is respectively connected to one end of the resistor R203 and the emitter of the PNP transistor Q202, the other end of the resistor R203 is connected to one end of the primary coil of the transformer T201, the other end of the primary coil of the transformer T201 is connected to one end of the capacitor C201, the other end of the capacitor C201 and the collector of the PNP transistor Q202 are commonly connected to ground, and the first secondary coil of the transformer T201 is connected to one end of the capacitor C201. One end is respectively connected to one end of the resistor R204 and the cathode of the diode D201, the other end of the resistor R204 is respectively connected to one end of the resistor R205 and the anode of the diode D201, the other end of the resistor R205 is respectively connected to the first output end of the first driving module 20, the other end of the first secondary coil of the transformer T201 is the second output end of the first driving module 20, one end of the second secondary coil of the transformer T201 is respectively connected to one end of the resistor R206 and the cathode of the diode D202, the other end of the resistor R206 is respectively connected to one end of the resistor R207 and the anode of the diode D202, the other end of the resistor R207 is the third output end of the first driving module 20, and the other end of the second secondary coil of the transformer T201 is the fourth output end of the first driving module 20.

[0150] The working process of this circuit is:

[0151] High-level input signal: When a high-level signal is input to one end of resistor R201, current flows through R201 to the bases of NPN transistor Q201 and PNP transistor Q202. The base voltage of NPN transistor Q201 rises, turning on NPN transistor Q201. Since the high-level signal passes through resistor R201, the base voltage of PNP transistor Q202 exceeds its emitter voltage, causing PNP transistor Q202 to turn off. When NPN transistor Q201 is turned on, current flows from the power supply voltage to the collector of NPN transistor Q201, then through the emitter of NPN transistor Q201 to resistor R203, flowing to one end of the primary winding of transformer T201, out of the other end of the primary winding of transformer T201, into one end of capacitor C201, and back to the negative ground of the power supply from the other end of capacitor C201. As a result, the primary winding is applied with a voltage equal to the difference between the power supply voltage and the voltage across capacitor C201. Current flows in the positive direction through the primary winding, generating an induced voltage in the secondary winding of transformer T201. After the current passes through resistors R204 and R205, a high-level signal is output between the first and second output terminals of the first driver module 20. Similarly, after the current passes through resistors R206 and R207, the same high-level signal is output between the third and fourth output terminals of the first driver module 20. Capacitor C201 functions to pass AC current and block DC current, preventing magnetic saturation in transformer T201.

[0152] The input signal is low level: when a low level signal is input to one end of the resistor R201, the base voltages of the NPN transistor Q201 and the PNP transistor Q202 are both lower than the emitter voltage, causing the NPN transistor Q201 to be turned off and the PNP transistor Q202 to be turned on. When the NPN transistor Q201 is turned off, no current flows between its collector and emitter. When the PNP transistor Q202 is turned on, its emitter is connected to the ground through the collector, and the voltage at one end of the primary coil becomes a negative voltage. The current of the primary coil of the transformer T201 flows in the opposite direction, causing the induced voltage of the secondary coil of the transformer T201 to become a negative voltage, and the secondary output end outputs a negative low level signal.

[0153] As an implementation method, Figure 13 As shown, the second driving module 30 includes a seventh switch module 301, an eighth switch module 302 and a second voltage transformation and isolation module 303;

[0154] A first end of the seventh switch module 301 is connected to a power supply voltage, a second end of the seventh switch module 301 is respectively connected to a first end of the eighth switch module 302 and a first input end of the second voltage transformation and isolation module 303, a control end of the seventh switch module 301 and a control end of the eighth switch module 302 are commonly connected to an input end of the first driver module 20, a second end of the eighth switch module 302 and a second input end of the second voltage transformation and isolation module 303 are commonly connected to ground, a first output end of the second voltage transformation and isolation module 303 is a first output end of the second driver module 30, a second output end of the second voltage transformation and isolation module 303 is a second output end of the second driver module 30, a third output end of the second voltage transformation and isolation module 303 is a third output end of the second driver module 30, and a fourth output end of the second voltage transformation and isolation module 303 is a fourth output end of the second driver module 30.

[0155] The seventh switch module 301 controls the flow of current. When the seventh switch module 301 is on, it provides a high-level voltage to the second voltage conversion and isolation module 303; when it is off, no voltage is provided. When the eighth switch module 302 is on, it provides a low-level voltage to the second voltage conversion and isolation module 303. The second voltage conversion and isolation module 303 isolates and converts electrical signals, converting input high- and low-level signals into multiple isolated output signals. When the seventh switch module 301 is on, the second voltage conversion and isolation module 303 outputs a high-level voltage. When the eighth switch module 302 is on, the second voltage conversion and isolation module 303 outputs a low-level voltage.

[0156] The technical effect of this embodiment is that the second driver module receives the fourth control signal from the control module, processes the signal through the seventh and eighth switch modules, isolates the processed control signal through the second voltage transformation and isolation module, and distributes it to different output terminals to drive the subsequent seventh and eighth switch modules. The second voltage transformation and isolation module achieves electrical isolation between the input and output signals, enhancing the reliability and anti-interference capabilities of the system, and can generate multiple isolated output signals for driving different switch modules.

[0157] As an example, the circuit diagram of the second driving module 30 is as follows: Figure 14As shown, the seventh switch module 301 is an NPN transistor Q301, the eighth switch module 302 is a PNP transistor Q302, the second voltage transformation isolation module 303 is a transformer T301, and the second driving module 30 further includes a resistor R301, a resistor R302, a resistor R303, a resistor R304, a resistor R305, a resistor R306, a resistor R307, a diode D301, a diode D302, and a capacitor C301. One end of the resistor R301 is the input end of the second driving module 30, the other end of the resistor R301 is respectively connected to the base of the NPN transistor Q301 and the base of the PNP transistor Q302, the collector of the NPN transistor Q301 is connected to one end of the resistor R302, the other end of the resistor R302 is connected to the power supply voltage, the emitter of the NPN transistor Q301 is respectively connected to one end of the resistor R303 and the emitter of the PNP transistor Q302 and one end of the resistor R303, the other end of the resistor R303 is connected to one end of the primary coil of the transformer T301, the other end of the primary coil of the transformer T301 is connected to one end of the capacitor C301, the other end of the capacitor C301 and the collector of the PNP transistor Q302 are commonly connected to ground, and the first end of the transformer T301 is connected to the first end of the capacitor C301. One end of the secondary coil is respectively connected to one end of the resistor R304 and the cathode of the diode D301. The other end of the resistor R304 is respectively connected to one end of the resistor R305 and the anode of the diode D301. The other end of the resistor R305 is the first output end of the first driver module 20. The other end of the first secondary coil of the transformer T301 is the second output end of the first driver module 20. One end of the second secondary coil of the transformer T301 is respectively connected to one end of the resistor R306 and the cathode of the diode D302. The other end of the resistor R306 is respectively connected to one end of the resistor R307 and the anode of the diode D302. The other end of the resistor R307 is the third output end of the second driver module 30. The other end of the second secondary coil of the transformer T301 is the fourth output end of the second driver module 30.

[0158] The working process of this circuit is:

[0159] The input signal is high: When a high-level signal is input to one end of resistor R301, current flows through R301 to the bases of NPN transistor Q301 and PNP transistor Q302. The base voltage of NPN transistor Q301 rises, turning on NPN transistor Q301. Because the high-level signal passes through resistor R301, the base voltage of PNP transistor Q302 exceeds its emitter voltage, causing PNP transistor Q302 to turn off. When NPN transistor Q301 is turned on, current flows from the power supply voltage to the collector of NPN transistor Q301, then through the emitter of NPN transistor Q301 to resistor R303, flowing to one end of the primary winding of transformer T301, out of the other end of the primary winding of transformer T301, into one end of capacitor C301, and back to the negative ground of the power supply from the other end of capacitor C301. Therefore, the primary coil is applied with a voltage equal to the difference between the power supply voltage and the voltage across capacitor C301. Current flows in a positive direction through the primary coil, generating an induced voltage in the secondary coil of transformer T301. After the current passes through resistors R304 and R305, a high-level signal is output between the first and second output terminals of the second driver module 30. Similarly, after the current passes through resistors R306 and R307, the same high-level signal is output between the third and fourth output terminals of the second driver module 30. The function of capacitor C301 is to pass AC and block DC, thereby preventing magnetic saturation in transformer T301.

[0160] The input signal is low level: when a low level signal is input to one end of the resistor R301, the base voltages of the NPN transistor Q301 and the PNP transistor Q302 are both lower than the emitter voltage, causing the NPN transistor Q301 to be turned off and the PNP transistor Q302 to be turned on. When the NPN transistor Q301 is turned off, no current flows between its collector and emitter. When the PNP transistor Q302 is turned on, its emitter is connected to the ground through the collector, and the voltage at one end of the primary coil becomes a negative voltage. The current of the primary coil of the transformer T301 flows in the opposite direction, causing the induced voltage of the secondary coil of the transformer T301 to become a negative voltage, and the secondary output end outputs a negative low level signal.

[0161] As an implementation method, Figure 15 As shown, the staggered series buck-boost switching power converter also includes an isolated current signal sampling module 40, the first end of the isolated current signal sampling module 40 is connected to the second end of the first capacitor module 107, the second end of the isolated current signal sampling module 40 is connected to the input end of the first unidirectional conduction module 111, the voltage output end of the isolated current signal sampling module 40 is connected to the input end of the control module 10, and the isolated current signal sampling module 40 and the control module 10 are commonly grounded.

[0162] Among them, the isolated current signal sampling module 40 collects the current signal and performs isolation processing. The isolated current signal sampling module 40 is connected to the common ground with the control module 10, and outputs a voltage signal consistent with the voltage reference point of the control module 10. The control module 10 receives the voltage signal output by the isolated current signal sampling module 40, performs feedback control according to the sampling signal, and adjusts the drive signal.

[0163] The technical effect of this embodiment is: by isolating the current signal sampling module, electrical isolation is achieved between the current sampling signal and the control module, protecting the control module from high voltage and noise interference, and being connected to the common ground with the control module to ensure that the output signal of the isolated current signal sampling module is consistent with the voltage reference point of the control module, avoiding signal errors caused by different potential reference points.

[0164] The isolated current signal sampling module 40 can have a variety of different structures to achieve current sampling and signal isolation, including but not limited to the following structures:

[0165] 1. Hall effect sensor: Utilizes the Hall effect principle to measure current in a non-contact manner and provide analog or digital signal output of the current.

[0166] 2. Shunt resistor and isolation amplifier: Use a high-precision shunt resistor to measure current, and use an isolation amplifier (such as a differential amplifier) ​​to amplify and isolate the signal.

[0167] 3. Optocoupler and shunt resistor: Use shunt resistor for current sampling and isolate and transmit analog signals through optocoupler.

[0168] 4. Current transmitter: Use current transformer to convert high current into low current, and transmit the signal to the control circuit through the transmission circuit.

[0169] As an implementation method, Figure 16 As shown, the isolated current signal sampling module 40 includes a current transformer 401 and a sampling resistor 402;

[0170] The first end of the primary coil of the current transformer 401 serves as the first end of the isolated current signal sampling module 40 , and the second end of the primary coil of the current transformer 401 serves as the second end of the isolated current signal sampling module 40 . The first end of the secondary coil of the current transformer 401 and the first end of the sampling resistor 402 are connected to the ground. The second end of the secondary coil of the current transformer 401 and the second end of the sampling resistor 402 are connected to the voltage output end of the isolated current signal sampling module 40 .

[0171] Current transformer 401 converts the current in the primary circuit into a secondary current through electromagnetic induction. This secondary current is proportional to the primary circuit current. It also provides galvanic isolation, ensuring electrical isolation between the primary circuit and the measurement circuit. Sampling resistor 402 converts the secondary current from current transformer 401 into a voltage signal, providing a measurable voltage signal that is proportional to the primary circuit current.

[0172] As an embodiment, the circuit structure of the isolated current signal sampling module 40 is as follows: Figure 17 As shown, the isolated current signal sampling module 40 includes a current transformer T401, a resistor R401, a resistor R402 and a diode D401. The first end of the primary coil of the current transformer T401 is the first end of the isolated current signal sampling module 40, and the second end of the primary coil of the current transformer T401 is the second end of the isolated current signal sampling module 40. The first end of the secondary coil of the current transformer T401, the first end of the resistor R401, and the first end of the resistor R402 are commonly connected to the ground. The second end of the secondary coil of the current transformer T401 is respectively connected to the second end of the resistor R401 and the anode of the diode D401. The cathode of the diode D401 and the second end of the resistor R402 are commonly connected to the voltage output end of the isolated current signal sampling module 40.

[0173] The current flowing through current transformer T401 is the measured current (main circuit current), and electromagnetic induction generates a secondary current proportional to the primary current. Resistors R401 and R402 convert the induced current in the secondary coil of current transformer 401 into a voltage signal. One end of resistors R401 and R402 is connected to the control module 10 to form a common reference point, ensuring that the voltage signals between the two modules have the same reference point and eliminating voltage potentials caused by different potential reference points. Diode D401 ensures unidirectional current flow. Through resistor R402, the voltage signal output by the secondary circuit of current transformer 401 is similar to the waveform of the unidirectional current signal of the main circuit, and prevents the influence of reverse current on the circuit. The resistance value of resistor R401 is generally selected to be large. When the main primary current reverses and diode D401 is reversely cut off, the secondary induced reverse current flowing through resistor R401 generates a high reverse voltage, which resets the magnetic core of current transformer T401 to avoid magnetic flux saturation.

[0174] The technical effect of this circuit structure is that by using a combination of current transformers, resistors and diodes, high-precision current measurement and signal isolation are achieved, and through common ground connection, the voltage difference between different relative grounds is reduced, thereby reducing the generation of noise and interference.

[0175] As an embodiment, the staggered series buck-boost switching power converter further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;

[0176] A first end of the first resistor is connected to the first output end of the first driver module 20, a second end of the first resistor is connected to the control end of the first switch module 101 and the first end of the second resistor, and a second end of the second resistor is connected to the second output end of the first driver module 20 and the second end of the first switch module 101.

[0177] A first end of the third resistor is connected to the third output end of the first driver module 20, a second end of the third resistor is connected to the control end of the second switch module 102 and the first end of the fourth resistor, and a second end of the fourth resistor is connected to the fourth output end of the first driver module 20 and the second end of the second switch module 102.

[0178] A first end of the fifth resistor is connected to the first output end of the second driving module 30, a second end of the fifth resistor is respectively connected to the control end of the third switch module 103 and the first end of the sixth resistor, and a second end of the sixth resistor is respectively connected to the second output end of the second driving module 30 and the second end of the third switch module 103;

[0179] The first end of the seventh resistor is connected to the third output end of the second driving module 30, the second end of the seventh resistor is respectively connected to the control end of the fourth switch module 104 and the first end of the eighth resistor, and the second end of the eighth resistor is respectively connected to the fourth output end of the second driving module 30 and the second end of the fourth switch module 104.

[0180] like Figure 18 As shown, the first resistor is resistor R1, the second resistor is resistor R2, the third resistor is resistor R3, the fourth resistor is resistor R4, the fifth resistor is resistor R5, the sixth resistor is resistor R6, the seventh resistor is resistor R7, and the eighth resistor is resistor R8.

[0181] The present embodiment is described in detail below through a specific circuit structure:

[0182] like Figure 18As shown, the staggered series buck-boost switching power converter includes the following circuit structure: the first capacitor module 107 is a capacitor C1, the second capacitor module 108 is a capacitor C2, the third capacitor module 109 is a capacitor C3, the fourth capacitor module 110 is C4, the first inductor module 105 is an inductor L1, the second inductor module 106 is an inductor L2, the first unidirectional conduction module 111 is a diode D1, the second unidirectional conduction module 112 is a diode D2, the third unidirectional conduction module 113 is a diode D3, the fourth unidirectional conduction module 114 is a diode D4, the first switch The switch module 101 is an NMOSFET transistor Q1, the second switch module 102 is an NMOSFET transistor Q2, the third switch module 103 is an NMOSFET transistor Q3, and the fourth switch module 104 is an NMOSFET transistor Q4. The staggered series buck-boost switching power converter also includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a control module 10, a first drive module 20, a second drive module 30, and an isolated current signal sampling module 40.

[0183] The connection relationship between the modules in the circuit structure of this embodiment is as follows: the negative terminal of capacitor C1 and the positive terminal of capacitor C2 are first connected to form the circuit midpoint. The positive terminal of capacitor C1 is connected to the positive input voltage electrode VI, and the negative terminal of capacitor C2 is connected to the negative input voltage electrode VI-GND, so that capacitors C1 and C2 are connected in series between the positive and negative electrodes of the input voltage U(VI, VI-GND). The negative terminal of capacitor C3 and the positive terminal of capacitor C4 are first connected to form the circuit midpoint. The positive terminal of capacitor C3 is connected to the positive output voltage electrode VO, and the negative terminal of capacitor C4 is connected to the negative output voltage electrode VO-GND, so that capacitors C3 and C4 are connected in series between the positive and negative electrodes of the output voltage U(VO, VO-GND). Capacitors C1 and C2 are connected in series, and their connection point is then connected to the input terminal VP1 of the isolated current signal sampling module 40. The positive terminal of capacitor C1 is commonly connected to the positive input voltage electrode V1 and the drain electrode D of transistor Q1. The negative terminal of capacitor C2 is commonly connected to the negative input voltage electrode V1-GND and one end of resistor R9. The other end of resistor R9 is commonly connected to the source electrode S of transistor Q4, one end of resistor R8, and the fourth output negative electrode VS-Q4 of the second driver module 30. Capacitors C3 and C4 are connected in series, and their connection point is further commonly connected to the input terminal VP2 of the isolated current signal sampling module 40, the source electrode S of transistor Q2, the drain electrode D of transistor Q3, the positive electrode of diode D1, the negative electrode of diode D4, the second output negative electrode VS-Q2 of the first driver module 20, and one end of resistor R4. The positive terminal of capacitor C3 is commonly connected to the positive output voltage electrode VO and the negative electrode of diode D2. The negative terminal of capacitor C4 is commonly connected to the negative output voltage electrode VO-GND and the positive electrode of diode D3. The source electrode S of transistor Q1 is commonly connected to one end of inductor L1, the cathode of diode D1, the negative electrode of the first output terminal VS-Q1 of the first driver module 20, and one end of resistor R2. The gate electrode G of transistor Q1 is commonly connected to one end of resistor R1 and the other end of resistor R2. The other end of resistor R1 is connected to the positive electrode VG-Q1 of the first output terminal of the first driver module 20. The other end of inductor L1 is commonly connected to the positive electrode of diode D2 and the drain electrode D of transistor Q2. The gate electrode G of transistor Q2 is commonly connected to one end of resistor R3 and the other end of resistor R4. The other end of resistor R3 is connected to the positive electrode VG-Q2 of the second output terminal of the first driver module 20. The source S of the transistor Q3 is commonly connected to one end of the inductor L2, the cathode of the diode D3, the negative electrode of the third output terminal VS-Q3 of the second driver module 30, and one end of the resistor R6. The gate G of the transistor Q3 is commonly connected to one end of the resistor R5 and the other end of the resistor R6. The other end of the resistor R5 is connected to the positive electrode VG-Q3 of the third output terminal of the second driver module 30.The other end of the inductor L2 is connected to the anode of the diode D4 and the drain D of the transistor Q4. The gate G of the transistor Q4 is connected to one end of the resistor R7 and the other end of the resistor R8. The other end of the resistor R7 is connected to the fourth positive output terminal VG-Q4 of the second driving module 30.

[0184] Transistor Q1, transistor Q2, inductor L1, capacitor C1, capacitor C3, diode D1, and diode D2 form a first group of main circuit modules. Transistor Q3, transistor Q4, inductor L2, capacitor C2, capacitor C4, diode D3, and diode D4 form a second group of main circuit modules.

[0185] The input signals and working power supply of the control module 10 include: the positive pole VI and the negative pole VI-GND of the input voltage, the voltage value VS2 signal on the current sampling resistor R9, the voltage signal VS1 output by the isolated current sampling module 40, the 0 potential reference end of the signals VS1 and VS2 connected to VCC-GND, and the positive pole VCC and the negative pole VCC-GND of the working power supply of the switching power converter.

[0186] The output signals of the control module 10 include: a first output high-frequency square wave signal with adjustable duty cycle VD1 , and a second output high-frequency square wave signal with adjustable duty cycle VD2 .

[0187] The input control signal and working power supply of the first driving module 20 include: a first input high-frequency square wave signal with adjustable duty cycle VD1, a working power supply VCC and a negative electrode VCC-GND.

[0188] The output drive signal of the first drive module 20 includes: a first output N-channel field effect transistor gate drive signal positive electrode VG-Q1 (at Figure 18 The first output is the negative electrode of the N-channel field effect transistor gate drive signal VS-Q1 (in Figure 18 The second output is the positive electrode VG-Q2 of the gate drive signal of the N-channel field effect transistor (in Figure 18 The second output is the negative electrode of the N-channel field effect transistor gate drive signal VS-Q2 (in Figure 18 The source S of transistor Q3 is connected in the middle).

[0189] The input control signal and working power supply of the second driving module 30 include: a second input high-frequency square wave signal with adjustable duty cycle VD2, a working power supply VCC and a negative electrode VCC-GND.

[0190] The output drive signal of the second drive module 30 includes: a third output N-channel field effect transistor gate drive signal positive electrode VG-Q3 (at Figure 18The third output is the negative electrode of the N-channel field effect transistor gate drive signal VS-Q3 (in Figure 18 The fourth output is the positive electrode VG-Q4 (in the Figure 18 The fourth output is the negative electrode of the N-channel field effect transistor gate drive signal VS-Q4 (in Figure 18 The source S of transistor Q4 is connected in the middle).

[0191] The input end of the isolated current signal sampling module 40 includes: a circuit connection point VP1 where the capacitor C1 and the capacitor C2 are connected in series, and a circuit connection point VP2 where the capacitor C3 and the capacitor C4 are connected in series.

[0192] The output end of the isolated current signal sampling module 40 includes: a voltage signal positive terminal VS1 having the same proportional value as the current flowing between its input terminals VP1 and VP2, and a voltage signal negative terminal connected to a zero potential reference point VCC-GND.

[0193] The control module 10 needs to output two drive signals VD1 and VD2 with different phases. The phase difference between the drive signals VD1 and VD2 is 180 degrees within one switching cycle. In addition, the other parameter characteristics of the drive signals VD1 and VD2 are the same. For example, the waveforms are both square waves, and their parameters such as frequency, duty cycle, voltage amplitude, rising edge, and falling edge remain basically the same (minor differences within an acceptable error range are allowed). The waveform diagrams of the drive waveforms VD1 and VD2 are shown in Figure 1. Figure 19 As shown, Figure 19 The meanings of the symbols are as follows:

[0194] Ton: The high-level period of the drive signal voltage within a switching cycle T, that is, the on-period of the switching transistor within a cycle T. Toff: The low-level period of the drive signal voltage within a switching cycle T, that is, the off-period of the switching transistor within a cycle T. 180°: The phase difference between the positive electrode of the first drive signal voltage VD1 output by the control module 10 and the second drive signal voltage VD2 is 180°. U(VD1, VCC-GND): The voltage waveform between the positive electrode of the first drive signal voltage VD1 output by the control module 10 and the 0-potential reference point VCC-GND. U(VD2, VCC-GND): The voltage waveform between the positive electrode of the second drive signal voltage VD2 output by the control module 10 and the 0-potential reference point VCC-GND.

[0195] Each circuit module in the first driver module 20 and the second driver module 30 needs to simultaneously output two N-channel field effect transistor gate drive signals of different potentials. The two signals output by the same driver circuit module are in phase. The waveforms of the two drive signals output by the first driver module 20 are in phase with the waveform of its input control signal VD1. At the same time, the waveforms of the two drive signals output by the second driver module 30 are in phase with the waveform of its input control signal VD2. Therefore, as described above, the phase difference between the drive signal output by the first driver module 20 and the drive signal output by the second driver module 30 within one switching cycle is 180°. Figure 20 As shown, Figure 20 The meanings of the symbols are:

[0196] VG-Q1: The positive electrode of the first drive signal output by the first driver module 20, connected to the gate G of transistor Q1 through resistor R1. VS-Q1: The negative electrode of the first drive signal output by the first driver module 20, connected to the source S of transistor Q1. U(GS-Q1): The voltage difference waveform of the first drive signal output by the first driver module 20. VG-Q2: The positive electrode of the second drive signal output by the first driver module 20, connected to the gate G of transistor Q2 through resistor R3. VS-Q2: The negative electrode of the second drive signal output by the first driver module 20, connected to the source S of transistor Q2. U(GS-Q2): The voltage difference waveform of the second drive signal output by the second driver module 30. VG-Q3: The positive electrode of the third drive signal output by the second driver module 30, connected to the gate G of transistor Q3 through resistor R5. VS-Q3: The negative electrode of the third drive signal output by the second driver module 30, connected to the source S of transistor Q3. U(GS-Q3): Voltage difference waveform of the first drive signal output by the second driver module 30. VG-Q4: Positive electrode of the fourth drive signal output by the second driver module 30, connected to the gate G of transistor Q4 via resistor R7. VS-Q4: Negative electrode of the fourth drive signal output by the second driver module 30, connected to the source S of transistor Q4. U(GS-Q4): Voltage difference waveform of the second drive signal output by the second driver module 30.

[0197] like Figures 19 to 20 As shown, the four driving signals output by the first driving module 20 and the second driving module 30 all use the S poles of the driven transistors (Q1-Q4) as the reference 0 potential of their respective signals. The potentials of these four circuit reference points are all different, and three of them are different from the reference 0 potential VCC-GND of the control module 10.

[0198] Therefore, voltage isolation function is required between the four driving signals output by the first driving module 20 and the second driving module 30 , and between the four driving signals and the output driving signal VD1 and the driving signal VD2 of the control module 10 .

[0199] An implementation circuit of the first driving module 20 and the second driving module 30 is as follows: Figure 12 and Figure 14 As shown, the first driving module 20 and the second driving module 30 use exactly the same internal circuit structure, the difference between them is the different phases of the input signals VD1 and VD2 and the different bit numbers of the connected external components. Figure 12 and Figure 14 This is just one implementation circuit of the first driving module 20 and the second driving module 30 . There are other types of implementation circuits, which will not be described in detail here.

[0200] like Figure 18 As shown, the potential difference between the current sampling point of the isolated current signal sampling module 40 and the 0 potential reference point of the control module 10 is large, and the isolated current sampling module 40 is needed to make the voltage signal at its output end have the same 0 potential reference point as the control module 10. An implementation circuit of the isolated current signal sampling module 40 is shown in FIG. Figure 17 See above for Figure 17 The description is not repeated here.

[0201] The meaning of the component symbols in the above schematic diagram includes the series and parallel combinations of physical components and components of the same properties. Some components in the schematic diagram can use extreme values, for example:

[0202] a. The resistance values ​​of resistors R2, R4, R6, and R8 can be infinite, which is equivalent to an open circuit. They can be removed and the resistor symbols do not need to be drawn in the schematic diagram.

[0203] b. The resistance values ​​of resistors R1, R3, R5, and R7 can be 0Ω. In this case, the resistor symbols can be replaced by short-circuited connecting wires.

[0204] like Figure 18 The working principle of the circuit structure shown is explained as follows:

[0205] like Figure 19 As shown, the control module 10 outputs two high-frequency square wave duty cycle control signals VD1 and VD2 with a phase difference of 180°. These control signals are high-level during the on-time period Ton and low-level during the off-time period Toff. Therefore, the output signals VD1 and VD2 of the control module 10 have the following four different operating modes within a working cycle T:

[0206] Mode 1: α<180°, VD1 is high level, VD2 is low level;

[0207] Mode 2: α<180°, VD1 is low level, VD2 is low level;

[0208] Mode 3: α>180°, VD1 is low level, VD2 is high level;

[0209] Mode 4: α>180°, VD1 is low level, VD2 is low level.

[0210] Working mode 1:

[0211] like Figures 18 to 20 As shown, in this working mode, in the interval α<180° of the upper half cycle of a working cycle T, the output voltage VD2 of the control module 10 and the output voltages U(VG-Q1, VS-Q1) and U(VG-Q2, VS-Q2) of the first driving module 20 are all high levels, and the output voltage VD1 of the control module 10 and the output voltages U(VG-Q3, VS-Q3) and U(VG-Q4, VS-Q4) of the second driving module 30 are all low levels.

[0212] At this time, since VD2, U(VG-Q1, VS-Q1), and U(VG-Q2, VS-Q2) are all high, transistors Q1 and Q2 are in the on state, U(DS-Q1) ≈ 0V, U(DS-Q2-) ≈ 0V, and diodes D1 and D2 are subjected to reverse voltage, U(D1) ≈ U(VI) / 2, U(D2) ≈ U(VO) / 2. Therefore, diodes D1 and D2 are in the off state. As mentioned above, U(VP1, VP2) ≈ 0V.

[0213] At this time, current flows out of the positive electrode of capacitor C1, passes through the drain D of transistor Q1, the source S of transistor Q1, the inductor L1, the drain D of transistor Q2, the source S of transistor Q2, the input terminals VP2 and VP1 of the isolated current signal sampling module 40, and flows back to the negative electrode of capacitor C1.

[0214] Based on the above current loop and substituting the above parameter approximations, the voltage across inductor L1 is calculated as shown in Formula 6:

[0215] U(L1)=U(C1)-U(DS-Q1)-U(DS-Q2)-U(VP1,VP2)≈U(C1)≈U(VI) / 2 Formula 6

[0216] At this time, the two ends of the coil of inductor L1 are subjected to a positive voltage, and the current flowing through inductor L1 begins to increase. Inductor L1 is in a state of increasing energy storage. The current I(L1) of inductor L1 is calculated as shown in Formula 7:

[0217]

[0218] At this time, since the drain D and source S of the transistors Q1 and Q2 and the input terminals VP1 and VP2 of the isolated current signal sampling module 40 are all in a single loop, the following formula 8 holds true:

[0219] I(DS-Q1)=I(DS-Q2)=I(40)=I(L1) Formula 8

[0220] The symbols in Formula 2-8 have the following meanings:

[0221] U(C*): instantaneous value of voltage across capacitor C*; U RMS (C*): RMS voltage across capacitor C*; U MAX (C*): Maximum voltage across capacitor C*; U MAX (D*): Maximum reverse voltage across diode D*; U RMS (VI): Effective value of the input voltage of the switching power converter; U RMS (VO): Effective value of the voltage at the output of the switching power converter; α: Phase angle of the output voltages VD1 and VD2 of the control module 10 within a switching cycle T; U(VI): Instantaneous value of the DC voltage at the input of the switching power converter; U MAX (VI): Maximum DC voltage at the input of the switching power converter; U MAX (DS-Q*): Maximum voltage between the drain D and source S of transistor Q*; U(VP1, VP2): Voltage between input terminals VP1 and VP2 of the isolated current signal sampling module 40; U(R9): Instantaneous voltage across current sampling resistor R9; U(L1): Instantaneous voltage across inductor L1, with the end connected to the cathode of diode D1 serving as the positive terminal of the measured voltage; I AVG (L*): average value of the current waveform flowing through the inductor L*; I MIN (L*): Minimum value of the current waveform flowing through the inductor L*;

[0222] I MAX (L*): Maximum value of the current waveform flowing through the inductor L*; I(L*): Instantaneous current value in the inductor L*;

[0223] I MAX (DS-Q*): Maximum current flowing through the drain D and source S of transistor Q*; I MAX (VI): Maximum current at the input terminal of the switching power converter; I(40): Instantaneous current value flowing through the input terminals VP1 and VP2 of the isolated current signal sampling module 40. *: The above symbol * represents a positive integer number.

[0224] At this time, since the output voltage VD1 of the control module 10 and the output voltages U(VG-Q3, VS-Q3) and U(VG-Q4, VS-Q4) of the second driving module 30 are all low levels, transistor Q3 and transistor Q4 are in the off state, and the current values ​​flowing through the drain D and source S of transistor Q3 and transistor Q4 are I(Q3-DS)≈0A and I(Q4-DS)≈0A.

[0225] At this time, the maximum voltage that transistor Q4 needs to withstand between its drain D and source S is:

[0226] U MAX (D,S_Q4)≈U MAX (C2)≈U MAX (VI) / 2

[0227] At this time, the maximum voltage that transistor Q3 needs to withstand between its drain D and source S is:

[0228] U MAX (D,S_Q3)≈U MAX (C4)≈U MAX (VO) / 2

[0229] At this time, the maximum reverse voltage that diode D1 needs to withstand is:

[0230] U MAX (D1)≈U MAX (C1)≈U MAX (VI) / 2

[0231] At this time, the maximum reverse voltage that diode D4 needs to withstand is:

[0232] U MAX (D2)≈U MAX (C3)≈U MAX (VO) / 2

[0233] Therefore, as mentioned above, in the working mode 1 period, the maximum voltage U(L1) across the inductor L1 and the maximum voltage between the drain D and source S of the transistor Q3 and the transistor Q4 are both Figure 1 The inductor of the prior art and the voltage between the drain D and the source S of the transistors Q1 and Q2 are shown to be half of the maximum value.

[0234] Because inductor L2 was in a current-increasing state during the previous operating cycle, its stored energy also increases. In operating mode 1 of this operating cycle, the current in inductor L2 cannot change suddenly. This current flows from the positive terminal of L2's self-inductance voltage through the anode and cathode of diode D4, and the junction of output capacitor C3 and capacitor C4 in series. It then splits into two paths. The first path flows through the cathode of capacitor C3, the positive terminal of capacitor C3, the positive terminal of the power converter output terminal VO, the positive terminal of the load, and the negative terminal of the load, and then into the junction of the cathode of capacitor C4 and the anode of diode D3. The second path flows through the positive terminal of capacitor C4 and into the junction of the cathode of capacitor C4 and the anode of diode D3. It then flows through the anode and cathode of diode D3 and into the negative terminal of inductor L2's self-inductance voltage.

[0235] At this time, the first freewheeling current in the inductor L2 passes through the capacitor C3 and, together with the charge stored in the capacitor C3, supplies power to the output load, and the capacitor C3 is discharged. The second freewheeling current in the inductor L2 charges the capacitor C4.

[0236] At this time, the instantaneous value of the current flowing through capacitors C3 and C4 is calculated as follows, formula 9:

[0237]

[0238] As mentioned above, since C3=C4 is selected, the voltages across capacitors C3 and C4 are close to U(C3)≈U(C4).

[0239] Based on the capacitor charging and discharging principle and the above formula, the voltage ripple values ​​of capacitors C3, C4, and the output of the power converter in operating mode 1 can be obtained as follows:

[0240]

[0241] The symbols in formula 9-10 have the following meanings:

[0242] I AVG1 (L2): Average value of inductor L2 in working mode 1; △U(C3-1): Ripple value of voltage U(C3) on capacitor C3 in working mode 1; △U(C4-1): Ripple value of voltage U(C4) on capacitor C4 in working mode 1; I(C4-1): Charging current and discharging current of current flowing through capacitor C4 in working mode 1, with discharging current as positive direction, that is, positive value indicates capacitor discharging, and negative value indicates capacitor charging; I(C3-1): Charging current and discharging current of current flowing through capacitor C3 in working mode 1, with discharging current as positive direction, that is, positive value indicates capacitor discharging, and negative value indicates capacitor charging; I(O): Output load current of switching power converter. The meanings of other symbols are the same as those in formula 1-8.

[0243] As can be seen from Equation 9, since this circuit structure is in operating mode 1, the current I(C3-1) in capacitor C3 is equal to the output current I(O), which is a constant value flowing out of the capacitor (in the positive direction). Therefore, capacitor C3 is in a discharge state, causing the voltage U(C3) across capacitor C3 to decrease.

[0244] As shown above, the current I(C4-1) flowing through capacitor C4 is the difference between the output current I(O) and the inductor current I(L2). Since the output current I(O) has minimal ripple and can be considered a high-frequency constant, while I(L2) decreases at a constant rate during Mode 1, the absolute value of the negative charging current through capacitor C4 decreases at a constant rate. As the voltage U(C4) across capacitor C4 increases, its rate of increase gradually slows.

[0245] Furthermore, the output voltage U(VO) of the power converter is equal to the sum of the voltage value U(C3) of the capacitor C3 and the voltage value U(C4) of the capacitor C4. Therefore, in the present invention, the two different voltage rise and fall states of the capacitors C3 and C4 can partially offset each other after being added in series, thereby significantly reducing the ripple value of the output voltage of the power converter (see Figure 23 U(C3) and U(C4) waveforms in Figure 1).

[0246] From the above analysis, it is easy to see that Figure 1 In the prior art, the ripple value of the output voltage in its working mode 1 is as follows:

[0247] ΔU(VO)≈2*I(O)*D*T / C3 Formula 11

[0248] As above, Figure 18 The output voltage ripple formula of the circuit structure of this embodiment shown in FIG10 is the same as Figure 1 Compared with the voltage ripple formula 11 of the prior art shown in FIG, the current value of the combined ripple of the capacitors C3 and C4 in formula 10 of this embodiment is 2*I(O)-I AVG1 (L2), which is significantly reduced by I compared to the combined ripple current value of 2*I(O) of capacitors C3 and C4 in the prior art formula 11. AVG1 (L2) value, so the output voltage ripple value △U(VO) generated by the comprehensive ripple current value of capacitor C3 and capacitor C4 is greatly reduced.

[0249] Similarly, under the same specification of the switching power converter output voltage ripple requirements, the circuit structure of this embodiment Figure 18 The switching power converter shown can use capacitors with smaller current specifications, which can greatly reduce the cost and size of the power converter.

[0250] As above, in Figure 18In the present utility model, the voltage between the drain D and the source S of the transistor Q4 and the transistor Q3 is reduced to Figure 1 The voltage between the drain D and source S of transistor Q4 and transistor Q3 in the prior art is about half of that in the prior art. Therefore, in the present invention, when the input voltage of the switching power converter is high, a general-purpose NMOSFET transistor with a lower voltage can be selected.

[0251] In summary, this embodiment meets the economic and social development direction of high performance, energy saving, consumption reduction, low carbon and low cost, and has broad application prospects.

[0252] Working mode 2:

[0253] like Figure 18 、 Figure 20 As shown, in this working mode, in the interval α<180° of the first half cycle of a working cycle T, the output voltage VD2 of the control module 10 and the output voltages U(GS-Q1) and U(GS-Q2) of the first driver module 20 are all low levels, and the output voltage VD1 of the control module 10 and the output voltages U(GS-Q3) and U(GS-Q4) of the second driver module 30 are all low levels.

[0254] At this time, since the driving signals of the above four NMOSFET transistors are all low, transistor Q1, transistor Q2, transistor Q3, and transistor Q4 are all in the off state, and the current values ​​flowing through the drain D and source S of transistor Q1, transistor Q2, transistor Q3, and transistor Q4 are I(DS-Q1)≈0A, I(DS-Q2)≈0A, I(DS-Q3)≈0A, and I(DS-Q4)≈0A.

[0255] Because inductor L1 is in a state of increasing current in operating mode 1, its stored energy also increases. Inductor L2 releases energy in operating mode 1. There are two situations for inductor L2 in operating mode 2: one in which the energy in inductor L2 has not yet been fully released in operating mode 2, and current I(L2) > 0A; the other in which the energy in inductor L2 is fully released at a certain moment in operating mode 2, and after this moment, current I(L2) = 0A.

[0256] A. In the first case of operating mode 2, because the current in inductor L1 cannot change suddenly, its current flows from the positive terminal of the self-inductance voltage of inductor L1 through the anode of diode D2 and the positive output terminal VO of the power converter. It then splits into two paths. One path flows into the positive terminal of capacitor C3, charges capacitor C3, and then flows out from the negative terminal of capacitor C3 and into the anode of diode D1. The other path flows into the positive output terminal VO, the positive terminal of the load, and the negative terminal of the load. Together with the charging current flowing from the negative terminal of capacitor C4, it flows into the anode of diode D3, then flows through the negative terminal of diode D3 and back to the negative terminal of the self-inductance voltage of inductor L2.

[0257] In the first case of operating mode 2, the current in inductor L2 is always greater than 0A. This current flows from the positive terminal of the self-inductance voltage of inductor L2 through the positive terminal of diode D4 and the negative terminal of diode D4, and then splits into two paths. One current flows through the positive terminal of capacitor C4, charges capacitor C4, and then flows out of the negative terminal of capacitor C4. It joins the current flowing back from the negative terminal of the load and enters the positive terminal of diode D3. Then, it flows through the negative terminal of diode D3 and returns to the negative terminal of the self-inductance voltage of inductor L2. The other current flows into the positive terminal of diode D1, joins with the current flowing out of the negative terminal of capacitor C3 after charging capacitor C3 in inductor L1, and then flows through the negative terminal of diode D1 and returns to the negative terminal of the self-inductance voltage of inductor L1.

[0258] At this time, the instantaneous value of the current flowing through capacitors C3 and C4 is calculated as follows, formula 12:

[0259]

[0260] As mentioned above, since C3=C4 is selected, the voltages across capacitors C3 and C4 are close to U(C3)≈U(C4).

[0261] Based on the capacitor charging and discharging principle and the above formula, the voltage ripple values ​​of capacitors C3, C4, and the output of the power converter in operating mode 2 can be obtained as follows:

[0262]

[0263] Equation 13 shows that in the first case of this circuit's operating mode 2, the current in capacitor C3, I(C3-2-1), equals the difference between the output current I(O) and the inductor current I(L1). Since the ripple of the output current I(O) is minimal, it can be considered a constant value during high-frequency cycles. Because the current I(L1) in inductor L1 increases during operating mode 1 and exceeds the output current I(O), the current in capacitor C3 becomes a negative charging current. Since capacitor C3 is in a charging state, the voltage U(C3) across capacitor C3 increases.

[0264] As shown above, the current in capacitor C4, I(C4-2-1), is the difference between the output current I(O) and the inductor current I(L2). Because the ripple of the output current I(O) is very small, it can be considered a constant value during high-frequency cycles. I(L2) decreases at a constant slope for two consecutive periods in operating mode 1 and mode 4, which precedes mode 1. During this period, the current value of I(L2) decreases from being greater than the output current I(O) to being less than I(O). Therefore, the current in capacitor C4 transitions from the charging direction in the previous operating mode to the discharging (forward) state in operating mode 2. At this time, the voltage U(C4) across capacitor C4 decreases.

[0265] Furthermore, the output voltage U(VO) of the power converter is equal to the sum of the voltage value U(C3) of the capacitor C3 and the voltage value U(C4) of the capacitor C4. Therefore, in the present invention, the two different voltage rise and fall states of the capacitors C3 and C4 can offset each other after being added in series, thereby significantly reducing the ripple value of the output voltage of the power converter (see Figure 23 U(C3) and U(C4) waveforms in Figure 1).

[0266] As above, Figure 18 The output voltage ripple formula of the circuit structure of this embodiment shown in Formula 13 is the same as Figure 1 Compared with the voltage ripple formula 11 of the prior art shown in FIG, the current value of the combined ripple of the capacitors C3 and C4 in the formula 13 of this embodiment is 2I(O)-I AVG2 (L1)-I AVG2 (L2), which is significantly reduced by I compared to the combined ripple current value of 2*I(O) of capacitors C3 and C4 in the prior art formula 11. AVG2 (L1)+I AVG2 (L2) value, therefore, the output voltage ripple value △U(VO) generated by the comprehensive ripple current value is greatly reduced.

[0267] As above, if L1=L2 and C3=C4, the voltage across capacitors C3 and C4 is approximately U(C3)≈U(C4). In the first case of operating mode 2 of this embodiment, the voltage across inductors L1 and L2 is calculated as follows:

[0268] U(L1)≈U(L2)≈U(C3)≈U(C4)≈U(VO) / 2 Formula 14

[0269] The meaning of symbols in formulas 12-14:

[0270] I(C3-2-1): The instantaneous value of the current on capacitor C3 in the first case of operating mode 2.

[0271] I(C4-2-1): The instantaneous value of the current on capacitor C4 in the first case of operating mode 2.

[0272] Note: The meanings of other symbols are the same as those in Formula 1-11.

[0273] Since the phase difference between control signals VD1 and VD2 of this circuit structure is 180°, the noise voltage generated by the high-frequency charging current of the above-mentioned capacitors C3 and C4 on the equivalent circuit inductance and equivalent circuit resistance of capacitors C3 and C4, after being connected in series, produces a peak-to-valley alternating complementary effect on the output voltage VO (VO, VO-GND). Therefore, the output voltage noise of the power converter of this embodiment is significantly reduced compared with the prior art.

[0274] At this time, the voltage value that transistor Q1 and transistor Q4 need to withstand between the drain D and source S is:

[0275] U MAX (D,S_Q1)≈U MAX (C1)≈U MAX (VI) / 2

[0276] U MAX (D,S_Q4)≈U(C2)≈U MAX (VI) / 2

[0277] At this time, the voltage value that transistor Q2 and transistor Q3 need to withstand between the drain D and source S is:

[0278] U MAX (D,S_Q2)≈U MAX (C3)≈U MAX (VO) / 2

[0279] U MAX (D,S_Q3)≈U MAX (C4)≈U MAX (VO) / 2

[0280] B. In the second case of operating mode 2, at a certain moment in operating mode 2, the energy in inductor L2 is completely released, and I(L2) = 0A. Before this moment, because I(L2) > 0A, the power converter's operating state and current flow are exactly the same as in the first case above, and will not be further described here. After this moment, because I(L2) = 0A, diodes D3 and D4 enter the cutoff state due to the reverse voltage.

[0281] As mentioned above, in the second case of operating mode 2, when I(L2) = 0A, transistors Q1, Q2, Q3, Q4, and diodes D3 and D4 are all in the off state. At this point, because the current in inductor L1 cannot change suddenly, it flows from the positive terminal of the self-inductance voltage of inductor L1 through the anode of diode D2 and the positive output terminal VO of the power converter. It then splits into two paths. One path flows into the positive terminal of capacitor C3, charging capacitor C3 before flowing out of the negative terminal of capacitor C3 and into the anode of diode D1. The other path flows into the positive output terminal VO, the positive terminal of the load, the negative terminal of the load, and then into the negative terminal of capacitor C4. It then flows out of the positive terminal of capacitor C4, passes through the anode of diode D1, the negative terminal of diode D1, and returns to the negative terminal of the self-inductance voltage of inductor L1.

[0282] At this time, as analyzed above, the current on capacitor C3 is as shown in Formula 15:

[0283] I(C3-2-2)=I(O)-I(L1) Formula 15

[0284] As analyzed in the first case above, at this time the capacitor C3 is in a charging state (negative current).

[0285] At this point, capacitor C4 is discharged, and the discharge current I(C4-2-2) = I(0). Therefore, in the second case of operating mode 2 of this embodiment, the voltage rise and fall caused by the two different current flows in capacitors C3 and C4 can partially offset each other at the output of the power converter, thereby significantly reducing the ripple value of the output voltage of the power converter.

[0286] At this time, the maximum voltage that transistor Q1 needs to withstand between its drain D and source S is:

[0287] U MAX (D,S_Q1)≈U MAX (C2)≈U MAX (VI) / 2

[0288] At this time, the maximum voltage that transistor Q2 needs to withstand between its drain D and source S is:

[0289] U MAX (D,S_Q2)≈U MAX (C3)≈U MAX (VO) / 2

[0290] At this time, the maximum voltage that transistor Q4 needs to withstand between its drain D and source S is:

[0291] U MAX (D,S_Q4)≤U MAX (C2)≈U MAX (VI) / 2

[0292] At this time, the maximum voltage value that transistor Q3 needs to withstand between its drain D and source S is:

[0293] U MAX (D,S_Q3)≤U MAX (C4)≈U MAX (VI) / 2

[0294] In summary, in this embodiment, during operating mode 2, the maximum voltage across inductor L1 and inductor L2 is half the output voltage. The maximum voltage across the drain D and source S of transistors Q1 and Q4 is half the maximum input voltage. The maximum voltage across the drain D and source S of transistors Q2 and Q3 is half the maximum output voltage.

[0295] Therefore, in this embodiment, the maximum voltage value that each of the above components can withstand is Figure 1 The voltage borne by the corresponding components in the prior art (inductor L1, diodes D1 and D2, and transistors Q1 and Q2 (between drain D and source S)) is half of the maximum value.

[0296] Working mode 3:

[0297] like Figure 18 、 Figure 20 As shown, in this working mode, in the second half period α>180° interval of a working cycle T, the output voltage VD2 of the control module 10 and the output voltages U(GS-Q1) and U(GS-Q2) of the first driver module 20 are all low levels, and the output voltage VD1 of the control module 10 and the output voltages U(GS-Q3) and U(GS-Q4) of the second driver module 30 are all high levels.

[0298] The operating process of operating mode 3 is identical to that of operating mode 1, with only the corresponding component numbers being different. The operating principle of operating mode 3 is also identical to that of operating mode 1. Therefore, this embodiment achieves the same beneficial effects in operating mode 3 as in operating mode 1, and will not be further elaborated upon.

[0299] Working mode 4:

[0300] like Figure 18 、 Figure 20 As shown, in this working mode, in the second half period α>180° interval of a working cycle T, the output voltage VD2 of the control module 10 and the output voltages U(GS-Q1) and U(GS-Q2) of the first driver module 20 are all low levels, and the output voltage VD1 of the control module 10 and the output voltages U(GS-Q3) and U(GS-Q4) of the second driver module 30 are all low levels.

[0301] The operating process of operating mode 4 is identical to that of operating mode 2, with only the corresponding component numbers being different. The operating principle of operating mode 4 is also identical to that of operating mode 2. Therefore, this embodiment achieves the same beneficial effects in operating mode 4 as in operating mode 2, and will not be further elaborated upon.

[0302] As an example, when this embodiment Figure 12 、 Figure 14 、 Figure 17 and Figure 18 The parameters of each component in the circuit shown are selected as follows:

[0303] Resistors: R1 = R3 = R5 = R7 = 10Ω, R2 = R4 = R6 = R8 = 10KΩ; capacitors: C1 = C2 = 5000uF, C3 = C4 = 100uF; N-channel field-effect transistors Q1, Q2, Q3, Q4 model: SPP11N80C3; inductor L1 = L2 = 2mH; input voltage: U(VI) = 1500V DC.

[0304] Auxiliary power supply voltage: (VCC1, VCC1-GNG) = 12V; drive signals VD1, VD2: frequency 50kHz, duty cycle D = 21%; current transformer T401 coil turns ratio N = 100:1; current sampling resistor R9 = 0.1Ω; load resistance value between the power converter output terminals VO and VO-GND: 200Ω.

[0305] It can be obtained that this embodiment Figure 12 、 Figure 14 、 Figure 17 and Figure 18 The voltage and current waveforms of each component in the circuit, such as Figure 21-23 As shown, Figure 21-23 Meaning of symbols:

[0306] U(Q*): Voltage waveform between drain D and source S of NMOSFEY transistor Q*, which is also U(DS-Q*) in the above formula, * represents any number or letter number. U(L*): Voltage waveform between both ends of inductor, with the positive end of the voltage when the inductor is continuously flowing as the positive direction of measurement, * represents any number or letter number. U(C*): Voltage waveform between both ends of capacitor, with the negative end of the capacitor as the reference 0 level, * represents any number or letter number. U(VO): Voltage waveform at the output end VO of the switching power converter, with the voltage of the present invention as the reference 0 level. Figure 18 The circuit node VO-GND in the circuit is the reference 0 level, which is U(VO, VO-GND) in the above formula. U(VI): The voltage waveform of the input terminal VI of the switching power converter. Figure 18The circuit node VI-GND in the equation is referenced to the zero voltage level, which is also referred to as U(VI, VI-GND) in the above formula. I(L*): Current waveform flowing through the inductor, measured with the current flowing when the inductor current increases as the positive direction. The * represents any number or letter. I(C*): Current waveform flowing through the capacitor, measured with the current flowing out of the capacitor's positive terminal as the positive direction. The * represents any number or letter. I(OUT): Current waveform output from the switching power converter, measured with the current flowing out of the switching power converter's positive terminal as the positive direction. The other numbers have the same meaning as in the above equations 1-9.

[0307] from Figure 22 It can be seen that the fluctuation patterns of the currents I(C3) and I(C4) on the output capacitors C3 and C4 are complementary positive and negative current patterns, that is, the charging and discharging currents of the capacitors C3 and C4 are staggered in the above-mentioned working modal analysis of this embodiment, so that the voltage fluctuations on the capacitors C3 and C4 are complementary peak-valley patterns.

[0308] from Figure 23 It can be seen that because the fluctuation patterns of the voltages U(C3) and U(C4) across the output capacitors C3 and C4 are complementary peak-to-valley, and U(VO)=U(C3)+U(C4), the fluctuation amplitude of the output voltage U(VO) of this embodiment is significantly reduced. This conclusion is exactly the same as the conclusion of the calculation formula in the above-mentioned working modal analysis of this embodiment.

[0309] from Figure 21 and Figure 23 It can be seen that the maximum values ​​of the voltages U(Q1) and U(Q4) across the drain D and source S of the NMOSFET transistors Q1-Q4 are both half of the switching power converter input voltage U(VI), the maximum values ​​of U(Q2) and U(Q3) are both half of the switching power converter output voltage U(VO), and the maximum absolute value of the voltage across the inductors L1 and L2 is half of U(VI). This conclusion is exactly the same as the conclusion calculated using the formula in the above-mentioned working modal analysis of this embodiment.

[0310] In summary, the technical innovations and significant beneficial effects of this embodiment include the following:

[0311] 1. If Figure 18 As shown, in this embodiment, there are two groups of switching power supply conversion circuits with the same structure. Figure 1 Compared with the prior art shown in FIG, the voltage value between the drain D and the source S of the transistor Q1 and the transistor Q4 is reduced to Figure 1 At the same time, the voltage between the drain D and source S of transistors Q2 and Q3 is reduced to Figure 1 About half of the corresponding devices in .

[0312] Therefore, in this embodiment, when the input voltage of the switching power converter is relatively high, a general-purpose, low-cost NMOSFET transistor with relatively low voltage can be selected.

[0313] 2. In this embodiment, the control module 10 outputs two phase drive signals, VD1 and VD2. VD1 and VD2 are pulsed square wave control signals with the same frequency and duty cycle, but a phase difference of 180°. Compared with the prior art, through reasonable parameter design, this embodiment can achieve extremely low output voltage ripple in most common application scenarios. Similarly, under the same switching power converter output voltage ripple requirements, this embodiment can select capacitors with smaller current specifications, significantly reducing the cost and size of the power converter.

[0314] Therefore, this embodiment has the characteristics of low cost, high electrical performance index and high reliability, and is suitable for high-end application scenarios with high electrical performance requirements. At the same time, the low cost can make the utility model have the prospect of large-scale application.

[0315] 3. This embodiment has two sets of first drive modules 20 and second drive modules 30 with the same structure. Compared with the prior art, the first drive modules 20 and the second drive modules 30 of this embodiment can avoid the serious safety hazard of the control module 10 being broken down and burned by the input high voltage U(VI, VI-GND) when an abnormal state occurs in the power converter circuit. Therefore, the utility model has high reliability and strong maintainability.

[0316] Therefore, this embodiment meets the economic and social development requirements of high performance, strong versatility, low cost, high reliability, and maintainability, and has broad application prospects. It is particularly applicable to applications with high DC input voltages, such as those where U(VI, GND) is greater than 1000V. This embodiment enables universal, low-cost, low-voltage NMOSFET field-effect transistors to have a large number of new high-voltage applications, with considerable social and economic benefits.

[0317] 4. The circuit structure provided in this embodiment is firstly applied in high-frequency switching industrial power supplies in the fields of solar energy, wind power generation equipment, energy storage equipment, industrial power supplies, etc.

[0318] 5. The circuit structure provided by this utility model can be applied to high-frequency switching power supplies of any appearance and structure. The circuit structure provided by this utility model can be implemented in any printed circuit board layout and connection method. The components in the circuit structure provided by this utility model can be components of the same principle and performance in any package, as well as any series or parallel combination thereof.

[0319] Example 2

[0320] The second embodiment of the present invention provides a staggered series buck-boost switching power supply converter, such as Figure 24 As shown, it includes a first switch module 101, a second switch module 102, a third switch module 103, a fourth switch module 104, a first inductor module 105, a second inductor module 106, a first capacitor module 107, a second capacitor module 108, a third capacitor module 109, a fourth capacitor module 110, a ninth switch module 121, a tenth switch module 122, an eleventh switch module 123 and a twelfth switch module 124;

[0321] The first end of the first capacitor module 107 is connected to the first end of the first switch module 101, the second end of the first capacitor module 107 is respectively connected to the first end of the second capacitor module 108, the input end of the ninth switch module 121, the output end of the twelfth switch module 124, the second end of the second switch module 102, the first end of the third switch module 103, the second end of the third capacitor module 109 and the first end of the fourth capacitor module 110, the second end of the first switch module 101 is respectively connected to the first end of the first inductor module 105 and the output end of the ninth switch module 121, and the second end of the first inductor module 105 is respectively connected to An input end of the tenth switch module 122 is connected to a first end of the second switch module 102, and an output end of the tenth switch module 122 is connected to a first end of the third capacitor module 109. A second end of the second capacitor module 108 is connected to a second end of the fourth switch module 104. A first end of the fourth switch module 104 is respectively connected to an input end of the twelfth switch module 124 and a first end of the second inductor module 106. A second end of the second inductor module 106 is respectively connected to a second end of the third switch module 103 and an output end of the eleventh switch module 123. An input end of the eleventh switch module 123 is connected to a second end of the fourth capacitor module 110.

[0322] The control end of the first switch module 101 and the control end of the second switch module 102 receive the same first control signal, the control end of the third switch module 103 and the control end of the fourth switch module 104 receive the same second control signal, and the first control signal and the second control signal have different phases;

[0323] The on-off states of the ninth switch module 121 and the tenth switch module 122 are opposite to the on-off states of the first switch module 101 and the second switch module 122;

[0324] The on-off states of the eleventh switch module 123 and the twelfth switch module 124 are opposite to the on-off states of the third switch module 103 and the fourth switch module 104 .

[0325] The first control signal and the second control signal are pulse square wave signals with the same frequency and the same duty cycle, and the phase difference between the first control signal and the second control signal is 180°.

[0326] The difference between this embodiment 2 and embodiment 1 is that: the first unidirectional conduction module 111 is replaced by the ninth switch module 121, the second unidirectional conduction module 112 is replaced by the tenth switch module 122, the third unidirectional conduction module 113 is replaced by the eleventh switch module 123, and the fourth unidirectional conduction module 114 is replaced by the twelfth switch module 124. The remaining added modules and working methods are the same, and the on and off states of the ninth switch module 121, the tenth switch module 122, the eleventh switch module 123 and the twelfth switch module 124 are controlled so that the current flow direction is the same as that in the working process of embodiment 1. For the specific working process and technical effects, please refer to embodiment 1 and will not be repeated here.

[0327] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A staggered series buck-boost switching power converter, characterized in that: The staggered series buck-boost switching power converter includes a first switch module, a second switch module, a third switch module, a fourth switch module, a first inductor module, a second inductor module, a first capacitor module, a second capacitor module, a third capacitor module, a fourth capacitor module, a first unidirectional conduction module, a second unidirectional conduction module, a third unidirectional conduction module, and a fourth unidirectional conduction module; A first end of the first capacitor module is connected to a first end of the first switch module; a second end of the first capacitor module is respectively connected to a first end of the second capacitor module, an input end of the first unidirectional conduction module, an output end of the fourth unidirectional conduction module, a second end of the second switch module, a first end of the third switch module, a second end of the third capacitor module, and a first end of the fourth capacitor module; a second end of the first switch module is respectively connected to a first end of the first inductor module and an output end of the first unidirectional conduction module; a second end of the first inductor module is respectively connected to an input end of the second unidirectional conduction module and a first end of the second switch module; an output end of the second unidirectional conduction module is connected to a first end of the third capacitor module; a second end of the second capacitor module is connected to a second end of the fourth switch module; a first end of the fourth switch module is respectively connected to an input end of the fourth unidirectional conduction module and a first end of the second inductor module; a second end of the second inductor module is respectively connected to a second end of the third switch module and an output end of the third unidirectional conduction module; and an input end of the third unidirectional conduction module is connected to a second end of the fourth capacitor module; The control end of the first switch module and the control end of the second switch module receive the same first control signal, the control end of the third switch module and the control end of the fourth switch module receive the same second control signal, and the phases of the first control signal and the second control signal are different.

2. The interleaved series buck-boost switching power converter according to claim 1, wherein: The first control signal and the second control signal are pulse square wave signals with the same frequency and the same duty cycle, and the phase difference between the first control signal and the second control signal is 180°.

3. The staggered series buck-boost switching power converter according to claim 1 or 2, characterized in that: The staggered series buck-boost switching power converter further includes a control module, a first drive module and a second drive module; The output end of the control module is connected to the input end of the first driver module and the input end of the second driver module respectively; the first output end of the first driver module is connected to the control end of the first switch module; the second output end of the first driver module is connected to the second end of the first switch module; the third output end of the first driver module is connected to the control end of the second switch module; the fourth output end of the first driver module is connected to the second end of the second switch module; the first output end of the second driver module is connected to the control end of the third switch module; the second output end of the second driver module is connected to the second end of the third switch module; the third output end of the second driver module is connected to the control end of the fourth switch module; and the fourth output end of the second driver module is connected to the second end of the fourth switch module. The control module outputs a third control signal to the first driving module and a fourth control signal to the second driving module, the first driving module outputs a first control signal to the first switch module and the second switch module respectively according to the third control signal, and the second driving module outputs a second control signal to the third switch module and the fourth switch module respectively according to the fourth control signal; The third control signal and the first control signal are the same control signal, and the fourth control signal and the second control signal are the same control signal.

4. The interleaved series buck-boost switching power converter according to claim 3, wherein: The first driving module includes a fifth switch module, a sixth switch module and a first voltage transformation isolation module; The first end of the fifth switch module is connected to the power supply voltage, the second end of the fifth switch module is respectively connected to the first end of the sixth switch module and the first input end of the first voltage transformation and isolation module, the control end of the fifth switch module and the control end of the sixth switch module are commonly connected to the input end of the first driver module, the second end of the sixth switch module and the second input end of the first voltage transformation and isolation module are commonly connected to ground, the first output end of the first voltage transformation and isolation module is the first output end of the first driver module, the second output end of the first voltage transformation and isolation module is the second output end of the first driver module, the third output end of the first voltage transformation and isolation module is the third output end of the first driver module, and the fourth output end of the first voltage transformation and isolation module is the fourth output end of the first driver module.

5. The staggered series buck-boost switching power converter according to claim 3, wherein: The second driving module includes a seventh switch module, an eighth switch module and a second voltage transformation isolation module; The first end of the seventh switch module is connected to the power supply voltage, the second end of the seventh switch module is respectively connected to the first end of the eighth switch module and the first input end of the second transformer and isolation module, the control end of the seventh switch module and the control end of the eighth switch module are commonly connected to the input end of the first driver module, the second end of the eighth switch module and the second input end of the second transformer and isolation module are commonly connected to ground, the first output end of the second transformer and isolation module is the first output end of the second driver module, the second output end of the second transformer and isolation module is the second output end of the second driver module, the third output end of the second transformer and isolation module is the third output end of the second driver module, and the fourth output end of the second transformer and isolation module is the fourth output end of the second driver module.

6. The interleaved series buck-boost switching power converter according to claim 3, wherein: The staggered series buck-boost switching power converter further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; The first end of the first resistor is connected to the first output end of the first driving module, the second end of the first resistor is respectively connected to the control end of the first switch module and the first end of the second resistor, and the second end of the second resistor is respectively connected to the second output end of the first driving module and the second end of the first switch module; A first end of the third resistor is connected to the third output end of the first driving module, a second end of the third resistor is respectively connected to the control end of the second switch module and the first end of the fourth resistor, and a second end of the fourth resistor is respectively connected to the fourth output end of the first driving module and the second end of the second switch module; A first end of the fifth resistor is connected to the first output end of the second driving module, a second end of the fifth resistor is respectively connected to the control end of the third switch module and the first end of the sixth resistor, and a second end of the sixth resistor is respectively connected to the second output end of the second driving module and the second end of the third switch module; The first end of the seventh resistor is connected to the third output end of the second driving module, the second end of the seventh resistor is respectively connected to the control end of the fourth switch module and the first end of the eighth resistor, and the second end of the eighth resistor is respectively connected to the fourth output end of the second driving module and the second end of the fourth switch module.

7. The interleaved series buck-boost switching power converter according to claim 3, wherein: The staggered series buck-boost switching power converter also includes an isolated current signal sampling module, a first end of the isolated current signal sampling module is connected to the second end of the first capacitor module, a second end of the isolated current signal sampling module is connected to the input end of the first unidirectional conduction module, a voltage output end of the isolated current signal sampling module is connected to the input end of the control module, and the isolated current signal sampling module and the control module are commonly grounded.

8. The interleaved series buck-boost switching power converter according to claim 7, wherein: The isolated current signal sampling module includes a current transformer and a sampling resistor; The first end of the primary coil of the current transformer serves as the first end of the isolated current signal sampling module, the second end of the primary coil of the current transformer serves as the second end of the isolated current signal sampling module, the first end of the secondary coil of the current transformer and the first end of the sampling resistor are commonly connected to the ground, and the second end of the secondary coil of the current transformer and the second end of the sampling resistor are commonly connected as the voltage output end of the isolated current signal sampling module.

9. A staggered series buck-boost switching power converter, characterized in that: The staggered series buck-boost switching power converter includes a first switch module, a second switch module, a third switch module, a fourth switch module, a first inductor module, a second inductor module, a first capacitor module, a second capacitor module, a third capacitor module, a fourth capacitor module, a ninth switch module, a tenth switch module, an eleventh switch module, and a twelfth switch module; The first end of the first capacitor module is connected to the first end of the first switch module. The second end of the first capacitor module is respectively connected to the first end of the second capacitor module, the input end of the ninth switch module, the output end of the twelfth switch module, the second end of the second switch module, the first end of the third switch module, the second end of the third capacitor module, and the first end of the fourth capacitor module. The second end of the first switch module is respectively connected to the first end of the first inductor module and the output end of the ninth switch module. The second end of the first inductor module is respectively connected to the input end of the tenth switch module and the first end of the second switch module. The output end of the tenth switch module is connected to the first end of the third capacitor module. The second end of the second capacitor module is connected to the second end of the fourth switch module. The first end of the fourth switch module is respectively connected to the input end of the twelfth switch module and the first end of the second inductor module. The second end of the second inductor module is respectively connected to the second end of the third switch module and the output end of the eleventh switch module. The input end of the eleventh switch module is connected to the second end of the fourth capacitor module. The control end of the first switch module and the control end of the second switch module receive the same first control signal, the control end of the third switch module and the control end of the fourth switch module receive the same second control signal, and the first control signal and the second control signal have different phases; The on-off state of the ninth switch module and the tenth switch module is opposite to the on-off state of the first switch module and the second switch module; The on-off state of the eleventh switch module and the twelfth switch module is opposite to the on-off state of the third switch module and the fourth switch module.

10. The interleaved series buck-boost switching power converter according to claim 9, wherein: The first control signal and the second control signal are pulse square wave signals with the same frequency and the same duty cycle, and the phase difference between the first control signal and the second control signal is 180°.

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