Unidirectional switching circuit of signal control power supply

Abstract

The embodiment of the utility model discloses a unidirectional switch circuit of a signal control power supply, which comprises an MOS tube Q1, an MOS tube Q2, a resistor R1, a resistor R2 and a capacitor C2, the G pole of the MOS tube Q1 is used for receiving a control signal, the D pole of the MOS tube Q1 is connected with the G pole of the MOS tube Q2 through the resistor R1, the D pole of the MOS tube Q2 is used for connecting a peripheral function module power supply, the S pole of the MOS tube Q2 is connected with the positive pole of a voltage source, the S pole of the MOS tube Q1 is connected with GND, and the D pole of the MOS tube Q2 is connected with the negative pole of the voltage source. The two ends of the resistor R2 and the two ends of the capacitor C2 are connected with the S pole and the G pole of the MOS tube Q2 respectively. The GPIO interface signal control circuit is used for controlling on-off of a power supply through GPIO interface signals, and is simple in structure and low in cost.

Description

Technical Field

[0001] The utility model relates to the technical field of power supply control, in particular to a unidirectional switch circuit for signal-controlled power supply. Background Art

[0002] Currently, some electronic devices rely on the CPU's GPIO to control switching circuits, thereby turning peripheral modules on and off. However, these existing switching circuits are complex and costly, and cannot be adjusted to accommodate varying control voltage sources, power levels, power ripple quality, and load power-up and power-down sequencing requirements. This limits their applicability and fails to meet user needs. Utility Model Content

[0003] The technical problem to be solved by the embodiments of the present utility model is to provide a unidirectional switch circuit for controlling power supply with a signal, so as to simplify the structure and reduce the cost.

[0004] To solve the above technical problems, an embodiment of the present utility model provides a unidirectional switch circuit for a signal-controlled power supply, including a MOS transistor Q1, a MOS transistor Q2, a resistor R1, a resistor R2, and a capacitor C2. The G pole of the MOS transistor Q1 is used to receive a control signal, the D pole of the MOS transistor Q1 is connected to the G pole of the MOS transistor Q2 via the resistor R1, the D pole of the MOS transistor Q2 is used to connect to the power supply of a peripheral functional module, the S pole of the MOS transistor Q2 is connected to the positive pole of the voltage source, the S pole of the MOS transistor Q1 is connected to GND, and both ends of the resistor R2 and the capacitor C2 are connected to the S pole and the G pole of the MOS transistor Q2, respectively.

[0005] Furthermore, a capacitor C3 is included, and two ends of the capacitor C3 are connected to the S pole of the MOS transistor Q1 and the D pole of the MOS transistor Q2 respectively.

[0006] Furthermore, a resistor R5 is included, and two ends of the resistor R5 are respectively connected to the S pole and the G pole of the MOS tube Q1.

[0007] Furthermore, a capacitor C1 is included, one end of the capacitor C1 is connected to the S pole of the MOS tube Q2, and the other end is connected to GND.

[0008] Furthermore, a resistor R3 is included, and the G pole of the MOS tube Q1 receives a control signal through the resistor R3.

[0009] Furthermore, the MOS transistor Q1 and the MOS transistor Q2 are respectively an NMOS transistor and a PMOS transistor.

[0010] The beneficial effects of the present invention are as follows: the present invention is used for controlling the power on and off of a GPIO port signal, has a simple structure, and is low in cost. The present invention is often used in system hardware to control the power on and off of peripheral function modules through the CPU's GPIO, thereby achieving the purpose of controlling the peripheral function modules. In practical applications, the present invention can be adapted to different control voltage sources, power levels, power ripple quality, load power-on and power-off timing requirements, etc. by adjusting the device values ​​in the hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of a unidirectional switch circuit of a signal-controlled power supply according to Example 1 of the present utility model.

[0012] Figure 2 This is a schematic diagram of a unidirectional switch circuit of a signal-controlled power supply according to Example 2 of the present utility model.

[0013] Figure 3 This is a schematic diagram of a unidirectional switch circuit of a signal-controlled power supply according to Example 3 of the present utility model.

[0014] Figure 4 This is a schematic diagram of a unidirectional switch circuit of a signal-controlled power supply according to Example 4 of the present utility model.

[0015] Figure 5 This is a schematic diagram of a unidirectional switch circuit of a signal-controlled power supply according to Example 5 of the present utility model.

[0016] Figure 6 This is a waveform diagram of the unidirectional switch circuit of the signal-controlled power supply in Example 1 of the present utility model.

[0017] Figure 7 This is a waveform diagram of the unidirectional switch circuit of the signal-controlled power supply in Example 2 of the present utility model.

[0018] Figure 8 This is a waveform diagram of the unidirectional switch circuit of the signal-controlled power supply in Example 3 of the present utility model.

[0019] Figure 9 This is a waveform diagram of the unidirectional switch circuit of the signal-controlled power supply in Example 4 of the present utility model.

[0020] Figure 10 This is a waveform diagram of the unidirectional switch circuit of the signal-controlled power supply in Example 5 of the present utility model. DETAILED DESCRIPTION

[0021] It should be noted that, unless there is a conflict, the embodiments in this application and the features described in the embodiments can be combined with each other. The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] In the embodiments of the present invention, if there are directional indications (such as up, down, left, right, front, back, etc.), they are only used to explain the relative position relationship and movement status of the various components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0023] In addition, in this utility model, the terms "first," "second," etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include at least one of these features.

[0024] Please refer to Figures 1 to 10 The unidirectional switch circuit of the signal-controlled power supply of the embodiment of the present invention includes a MOS transistor Q1, a MOS transistor Q2, a resistor R1, a resistor R2, and a capacitor C2.

[0025] The G electrode of the MOS transistor Q1 is used to receive a control signal. The D electrode of the MOS transistor Q1 is connected to the G electrode of the MOS transistor Q2 through the resistor R1. The D electrode of the MOS transistor Q2 is used to connect to the power supply of the peripheral functional module. The S electrode of the MOS transistor Q2 is connected to the positive electrode of the voltage source. The S electrode of the MOS transistor Q1 is connected to GND. The resistor R2 and the two ends of the capacitor C2 are respectively connected to the S electrode and the G electrode of the MOS transistor Q2.

[0026] As an embodiment, the unidirectional switch circuit of the signal-controlled power supply further includes a capacitor C3, with its two terminals connected to the S-pole of MOS transistor Q1 and the D-pole of MOS transistor Q2, respectively. Capacitor C3 can store energy, stabilize waveforms, and perform filtering.

[0027] As an implementation manner, the unidirectional switch circuit of the signal-controlled power supply further includes a resistor R5 , and two ends of the resistor R5 are respectively connected to the S pole and the G pole of the MOS transistor Q1 .

[0028] As an implementation manner, the unidirectional switch circuit of the signal-controlled power supply further includes a capacitor C1 , one end of the capacitor C1 is connected to the S pole of the MOS transistor Q2 , and the other end is connected to GND.

[0029] As an implementation manner, the unidirectional switch circuit of the signal-controlled power supply further includes a resistor R3 , and the G pole of the MOS tube Q1 receives the control signal through the resistor R3 .

[0030] As an implementation manner, the MOS transistor Q1 and the MOS transistor Q2 are an NMOS transistor and a PMOS transistor respectively.

[0031] Example 1: In order to explain more clearly how this circuit works and to demonstrate how adjusting the values ​​of the components in the circuit affects the performance of the entire circuit, this utility model has built a circuit based on PROTEUS simulation software. Figure 1 As shown: There is a function button on the left side of R3. Pressing and disconnecting can connect or disconnect the signal on the square wave signal generator on the left side of the button (Note: This description mainly describes in detail how the circuit controls the on and off of the power supply through GPIO, so the square wave signal generator is used to simulate the high and low levels of GPIO. The signal generator voltage used in this simulation is 3.3V and the frequency is 0.5HZ).

[0032] When the G pole of the NMOS (Q1, model: 2N7002) (the pin connected to the resistors R3 and R5) receives a high-level signal from the square wave on the left side of the button, the G pole of Q1 is high (V=[10K / (240R+10K)]*3.3V=3.29V). At this time, the NMOS tube Q1 is turned on, and the 3.3V current passes through the resistors R2, R1 and the S and D poles of Q1, and then flows back to GND. At this time, the voltage of the G terminal of the PMOS tube Q2 (model: NTS4101P) is V=[10K / (10K+110K)]*3.3V≈0.3V; the S terminal of the PMOS tube Q2 is directly connected to 3.3V, so the VGS of the PMOS tube Q2 is 3.3V-0.3V=3.0V; at this time, by consulting the specification of the PMOS tube Q2 (model: NTS4101P), it can be known that the VGS at this time is greater than the minimum voltage for the signal conduction of the PMOS tube Q2, so the PMOS tube Q2 is turned on at this time, and the power flows from the S terminal of the PMOS tube Q2 (directly connected to the power supply 3.3V pin) through the D terminal of the PMOS tube Q2. In this embodiment, Figure 1 In the simulation circuit, the D pole of the PMOS tube Q2 is connected to the A channel of the simulation oscilloscope.

[0033] When the G pole of the NMOS (Q1, model: 2N7002) (the pin connected to the resistors R3 and R5) receives a low-level signal from the square wave on the left side of the button, the G pole of Q1 is at a low level (V=[240R / (240R+10K)]*3.3V=0V). At this time, the NMOS tube Q1 is turned off, and the voltage of the G pole of the PMOS tube Q2 (model: NTS4101P) is V=3.3V; the S pole of the PMOS tube Q2 is directly connected to 3.3V, so the VGS of the PMOS tube Q2 is 0V; therefore, the PMOS tube Q2 is not turned on at this time, and the power supply 3.3V cannot flow from the S pole of the PMOS tube Q2 through the D pole of the PMOS tube Q2, so the level of the D pole of the PMOS tube Q2 becomes a low level.

[0034] Example 2: The unidirectional switching circuit of a signal-controlled power supply of the present invention is not universal. When the GPIO controls the power supply on and off, the controlled power supply voltage will be different, and the back-end load power consumption will also be different. Therefore, in actual applications, the present invention will adjust the size of the device value in the circuit according to actual conditions to ensure stable operation of the circuit.

[0035] This circuit uses simulation software to demonstrate the changes in the output waveform of a GPIO-controlled power supply before and after adjusting the device values.

[0036] When adjusting Figure 2 When the components R1=100K; R2=100K; C2=2.2uF, when the signal generator output waveform is 3.3V, square wave, 0.5HZ, duty cycle is 50% (at Figure 7 The square wave above), you can see the waveform of the power output (located at Figure 7 The square wave below) has the following variations:

[0037] 1. The waveform has a delayed rise time relative to the waveform of the signal generator;

[0038] 2. The duty cycle is slightly greater than 50%;

[0039] 3. The falling edge of the waveform has a relatively slow slope and is no longer a standard square wave.

[0040] Circuit application scenario: If the back-end load requires a large current, has high requirements for power ripple, and the power supply cannot have too high a spur, you can use Figure 2 circuits, such as Figure 2 The C2 in the circuit is 2.2uF, which can absorb the ripple at the front end. If the waveform at the back end has burrs during the test, you can increase this value appropriately to improve the ripple at the back end.

[0041] Example 3: When adjusting Figure 3 When the components R1=10K; R2=100K; C2=2.2uF, the signal generator output waveform is 3.3V, square wave, 0.5HZ, duty cycle is 50% (at Figure 8 The square wave above), you can see the waveform of the power output (located at Figure 8 The square wave below) has the following variations:

[0042] 1. The waveform has almost no delay in rising edge time compared to the waveform of the signal generator;

[0043] 2. The duty cycle is greater than 50%, which is greater than when R1=100K;

[0044] 3. The falling edge of the waveform has a relatively slow slope and is no longer a standard square wave.

[0045] Analysis of the cause of the waveform change after changing R1=100K to 10K:

[0046] Analysis change 1: Compared with the waveform of the signal generator, the waveform has almost no delay in the rising edge.

[0047] When the PMOS tube Q2 is not turned on, the 3.3V power supply charges the capacitor C2 through R2, so that both end pins of C2 are 3.3V. When the G pole of the NMOS (Q1, model: 2N7002) (the pin connected to the resistors R3 and R5) receives a high-level signal from the square wave on the left side of the button, the G pole of Q1 is high (V=[10K / (240R+10K)]*3.3V=3.29V). At this time, the NMOS tube Q1 is turned on, and the 3.3V current passes through the resistors R2, R1 and the S and D poles of Q1, and then flows back to GND. At this time, the C2 pin connected to the G pole of the PMOS tube Q2 begins to discharge. Since R1=100K is changed to 10K, the discharge speed through the C2 pin connected to the G pole of the PMOS tube Q2 is faster than when R1=100K. Therefore, the G pole voltage of the PMOS tube Q2 drops more quickly, and the PMOS tube Q2 turns on faster, so the waveform will appear with almost no delay in the rising edge compared to the waveform of the signal generator.

[0048] Analysis of change 2: The duty cycle is greater than 50%, which is greater than the duty cycle when R1=100K.

[0049] There are two reasons why the duty cycle is greater than 50%. The first reason is that after the PMOS tube Q2 is turned off, there is a capacitor C3 at the back end (the size of this capacitor can be adjusted, and capacitors of different values ​​can be connected in parallel. The capacitor can store energy, stabilize the waveform, and filter). Therefore, the capacitor C3 discharges the stored electricity to the load R4 (R4 simulates the load), so the D-pole voltage at the PMOS tube Q2 will be delayed for a little time; the second reason is that after R1 is changed from 100K to 10K, when the PMOS tube Q2 is turned off, the G-pole voltage of the PMOS tube Q2 is cut off due to the shutdown of the NMOS tube Q1, and the current flow from 3.3V--→R2--→R1--→Q1--→GND is disconnected, and the PM The G-pole voltage of the OS tube Q2 begins to rise to 3.3V. However, since the voltage of VGS in the on-state when R2=100K is: R1 / (R1+R2)*3.3V=1.65V, and the voltage of VGS in the on-state when R=10K is: R1 / (R1+R2)*3.3V≈0.3V, the time for VGS of the PMOS tube Q2 to rise from 0.3V to 3.3V when R=10K is longer than the time for VGS of the PMOS tube to rise from 1.65V to 3.3V when R=100K. Therefore, the shutdown time of the PMOS tube Q2 in response to the IO port is longer when R=10K, so the duty cycle will be greater than 50%, which is greater than the duty cycle when R1=100K.

[0050] Circuit application scenario: If the backend has timing requirements and requires a certain delay in powering off, the following circuit can be used.

[0051] Example 4: When adjusting Figure 4 When the components R1=10K; R2=100K; C2=0.1uF, when the signal generator output waveform is 3.3V, square wave, 0.5HZ, duty cycle is 50% (at Figure 9 The square wave above), you can see the waveform of the power output end (located at Figure 9 The square wave below) has the following changes:

[0052] 1. Compared Figure 3 After C2 was changed from 2.2uF to 0.1uF, the duty cycle quickly changed from much greater than 50% to closer to 50%.

[0053] Analysis of changes: After C2 is changed from 2.2uF to 0.1uF, the duty cycle changes rapidly from far greater than 50% to closer to 50% because: when the PMOS tube Q2 is turned off, the G-pole voltage of the PMOS tube Q2 is cut off due to the shutdown of the NMOS tube Q1, and the current flow from 3.3V--→R2--→R1--→Q1--→GND is cut off. The G-pole voltage of the PMOS tube Q2 begins to rise to 3.3V, but when C2=2.2uF is changed to 0.1uF, due to the P of the capacitor C2 IN2 starts to charge, and the voltages across capacitor C2 begin to approach the same value. As the value of capacitor C2 decreases, the charging time decreases, so the time it takes for the VGS of the PMOS tube Q2 to recover from 0.3V to 3.3V is also faster. Therefore, when C2=0.1uF, the turn-off time of the PMOS tube Q2 in response to the IO port is shorter, and the D-pole voltage of the PMOS tube Q2 will respond quickly and fall back, so the duty cycle will decrease rapidly, approaching 50%, which is faster than the duty cycle when C2=2.2uF.

[0054] Circuit application scenario: If the back-end power-on speed is required to be fast, and the power-on time from 0V to 3.3V is required to be short (some multi-power supply modules require fast power-on, and power-on too slowly will cause timing disorder, insufficient power supply, etc., and cannot work properly), then you can proportionally reduce the resistance values ​​of R1 and R2, and appropriately adjust the value of C2 to ensure faster power-on speed.

[0055] Example 5: When adjusting Figure 5 When the components R1=10K; R2=100K; C2=0.1uF; C3=10uF, the signal generator output waveform is 3.3V, square wave, 0.5HZ, duty cycle is 50% (at Figure 10 The square wave above), you can see the waveform of the power output end (located at Figure 10 The square wave below) has the following changes:

[0056] 1. Compared Figure 4 After C3 is changed from 1uF to 10uF, the voltage at the D pole of the PMOS tube Q2 will slowly decrease.

[0057] Analysis of changes: After the PMOS tube Q2 is turned off, due to the presence of capacitor C3 at the back end (the size of this capacitor can be adjusted, and capacitors of different values ​​can be connected in parallel. The capacitor can store energy, stabilize the waveform, and filter), the capacitor C3 discharges the stored electricity to the load R4 (R4 simulates the load), so the D-pole voltage at the PMOS tube Q2 will slowly drop. Of course, the size of the load R4 will also affect the power drop speed.

[0058] Circuit application scenario: If the back-end load requires a fast power-off speed (when some modules are powered on and off quickly, if the power-off and power-on interval is too short, the module will be powered on before it is completely powered off, causing timing disorder and faults), you can add a bleeder resistor at the power supply output to speed up the voltage drop after power failure.

[0059] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A unidirectional switch circuit for a signal-controlled power supply, characterized in that: The circuit includes a MOS transistor Q1, a MOS transistor Q2, a resistor R1, a resistor R2, and a capacitor C2. The G pole of the MOS transistor Q1 is used to receive a control signal. The D pole of the MOS transistor Q1 is connected to the G pole of the MOS transistor Q2 through the resistor R1. The D pole of the MOS transistor Q2 is used to connect to the power supply of the peripheral functional module. The S pole of the MOS transistor Q2 is connected to the positive pole of the voltage source. The S pole of the MOS transistor Q1 is connected to GND. Both ends of the resistor R2 and the capacitor C2 are connected to the S pole and the G pole of the MOS transistor Q2, respectively.

2. The unidirectional switch circuit of the signal-controlled power supply according to claim 1, characterized in that: The device further includes a capacitor C3 , with two ends of the capacitor C3 connected to the S pole of the MOS transistor Q1 and the D pole of the MOS transistor Q2 , respectively.

3. The unidirectional switch circuit of the signal-controlled power supply according to claim 1, characterized in that: The device further includes a resistor R5 , the two ends of which are connected to the S pole and the G pole of the MOS tube Q1 .

4. The unidirectional switch circuit of the signal-controlled power supply according to claim 1, wherein: The device further includes a capacitor C1 , one end of which is connected to the S pole of the MOS tube Q2 , and the other end is connected to GND.

5. The unidirectional switch circuit of the signal-controlled power supply according to claim 1, characterized in that: A resistor R3 is also included, and the G pole of the MOS tube Q1 receives a control signal through the resistor R3.

6. The unidirectional switch circuit of the signal-controlled power supply according to claim 1, characterized in that: The MOS transistor Q1 and the MOS transistor Q2 are respectively an NMOS transistor and a PMOS transistor.

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