Battery SOC (State of Charge) estimation circuit, battery module and electric equipment

Abstract

The utility model provides a battery SOC estimation circuit, a battery module and electric equipment, and belongs to the technical field of batteries, a main loop of a battery is provided with a diverter, and the circuit comprises an integration module connected with the diverter and used for integrating voltage at one end of the diverter; the comparison module is connected with the integration module, the comparison module is used for converting the voltage of the integration module into a level signal, and the level signal is used for determining the integration frequency of the integration module; and the discharging module is respectively connected with the integration module and the comparison module, and the discharging module controls the integration module to discharge based on the level signal.

Description

Technical Field

[0001] The present disclosure relates to the field of battery technology, and in particular to a battery SOC estimation circuit, a battery module, and an electrical device. Background Art

[0002] In a battery management system (BMS), SOC (State of Charge) is a state variable used to indicate the remaining capacity of a battery. SOC is defined as the percentage of the battery's remaining capacity under a specific discharge rate to the rated capacity under the same conditions. Existing SOC algorithms primarily include the ampere-hour integration method. Most ampere-hour integration schemes use a Hall effect sensor or shunt to convert the current into a proportional voltage. The voltage is then sampled using an ADC. The software then obtains the sampled current value at fixed intervals and multiplies it by the time interval to obtain the required integral value, which is the sum of the products of discrete current values ​​and small time intervals. This method can only produce a relatively close theoretical integral value. For accurate calculations, the high-frequency calculations place an excessive burden on the microcontroller. Utility Model Content

[0003] The embodiments of the present disclosure provide a battery SOC estimation circuit and a vehicle, which can solve the problem of excessive computational burden on a controller due to high-frequency calculations.

[0004] In a first aspect, an embodiment of the present application provides a battery SOC estimation circuit, wherein a shunt is provided on the main circuit of the battery, and the circuit includes:

[0005] an integration module connected to the shunt, the integration module being configured to integrate the voltage at one end of the shunt;

[0006] a comparison module, the comparison module being connected to the integration module, the comparison module being used to convert the voltage of the integration module into a level signal, the level signal being used to determine the number of integration times of the integration module;

[0007] The discharge module is connected to the integration module and the comparison module respectively, and the discharge module controls the integration module to discharge based on the level signal.

[0008] Optionally, the integration module includes a first integration circuit and a second integration circuit, and the comparison module includes a first comparison circuit, a second comparison circuit and an SR latch;

[0009] The current divider, the first integration circuit, the first comparison circuit, and the first input terminal of the SR latch are connected in sequence;

[0010] The current divider, the second integration circuit, the second comparison circuit, and the second input terminal of the SR latch are connected in sequence.

[0011] Optionally, the first integration circuit includes a first resistor, a first capacitor, and a first operational amplifier, wherein the shunt, the first resistor, and the first capacitor are connected in sequence, and the first capacitor is connected between the inverting input terminal and the output terminal of the first operational amplifier;

[0012] The second integration circuit includes a second resistor, a second capacitor and a second operational amplifier, wherein the shunt, the second resistor and the second capacitor are connected in sequence, and the second capacitor is connected between the inverting input terminal and the output terminal of the second operational amplifier.

[0013] The positive input terminals of the first operational amplifier and the second operational amplifier are connected to a power supply.

[0014] Optionally, the first comparison circuit includes a first comparator, a second comparator and a first AND gate circuit;

[0015] The inverting input terminal of the first comparator and the positive input terminal of the second comparator are respectively connected to the output terminal of the first operational amplifier, the positive input terminal of the first comparator and the inverting input terminal of the second comparator are respectively input with reference voltages of the battery in the charging state and the discharging state, and the output terminals of the first comparator and the second comparator are connected to the input terminal of the first AND gate circuit;

[0016] The second comparison circuit includes a third comparator, a fourth comparator and a second AND gate circuit;

[0017] The inverting input terminal of the third comparator and the positive input terminal of the fourth comparator are respectively connected to the output terminal of the second operational amplifier, the positive input terminal of the third comparator and the inverting input terminal of the fourth comparator are respectively input with reference voltages in the battery charging state and the battery discharging state, and the output terminals of the third comparator and the fourth comparator are connected to the input terminals of the second AND gate circuit.

[0018] The output end of the first AND gate circuit is connected to the first input end of the SR latch, and the output end of the second AND gate circuit is connected to the second input end of the SR latch.

[0019] Optionally, the discharge module includes a first discharge circuit and a second discharge circuit;

[0020] The first discharge circuit includes a first switch tube and a third resistor. The first discharge circuit is connected in parallel with the first capacitor. The first switch tube is connected to the first output terminal of the SR latch and controls the first switch tube to be turned on based on a level signal output by the first output terminal, so as to discharge the first capacitor.

[0021] The second discharge circuit includes a second switch tube and a fourth resistor. The second discharge circuit is connected in parallel with the second capacitor. The second switch tube is connected to the second output end of the SR latch and controls the second switch tube to be turned on based on the level signal output by the second output end to discharge the second capacitor.

[0022] Optionally, the circuit includes a control module, any output terminal of the SR latch is connected to the control module, and the control module calculates the SOC of the battery based on the level signal output by the output terminal.

[0023] Optionally, the circuit further includes a charge and discharge detection module for detecting whether the battery is in a charging state or a discharging state.

[0024] Optionally, the charge and discharge detection module includes a fifth comparator, wherein the non-inverting input terminal and the inverting input terminal of the fifth comparator are respectively connected to the two ends of the shunt, and the fifth comparator is used to output a status signal indicating whether the battery is in a charging state or a discharging state.

[0025] In a second aspect, an embodiment of the present application provides a battery module, comprising a battery SOC estimation circuit as described in any one of the first aspects.

[0026] In a third aspect, an embodiment of the present application provides an electrical device, comprising a battery module and a battery SOC estimation circuit as described in any one of the first aspects.

[0027] One beneficial effect of the embodiments of the present disclosure is that the shunt is connected in series with the main charging and discharging circuit of the battery to convert the battery charging and discharging current into a voltage signal in proportion. The battery SOC estimation circuit can integrate the voltage signal on the main circuit through the integration module, and convert it into a level signal that determines the number of integrations through the comparison module. The discharge module can also control the integration module to discharge and re-integrate through the level signal. Through the above circuit, the control unit can determine the change in the battery charge amount only by determining the level signal of the integration number and the integrated charge amount of the integration module to determine the battery SOC. It does not need to perform high-frequency integration operations, which reduces the calculation amount of the control module and solves the problem of excessive burden on the control module.

[0028] Other features and advantages of the embodiments of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0030] Figure 1The figure shows a structural block diagram of a battery SOC estimation circuit according to an embodiment of the present disclosure.

[0031] Figure 2 A schematic diagram showing an example of a battery SOC estimation circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention.

[0033] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present invention, its application, or uses.

[0034] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0035] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0036] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0037] like Figure 1 As shown, the embodiment of the present application introduces a battery SOC estimation circuit, which is characterized in that a shunt Rs is provided on the main circuit of the battery, and the circuit includes: an integration module 1001, which is connected to the shunt Rs, and the integration module 1001 is used to integrate the voltage at one end of the shunt Rs; a comparison module 1002, which is connected to the integration module 1001, and is used to convert the voltage of the integration module 1001 into a level signal, and the level signal is used to determine the number of integration times of the integration module 1001; a discharge module 1003, which is respectively connected to the integration module 1001 and the comparison module 1002, and the discharge module 1003 controls the integration module 1001 to discharge based on the level signal.

[0038] In the embodiment of the present application, the shunt Rs can be a small resistance with high precision and small temperature coefficient, which is used as the shunt Rs and is set in the main circuit of the battery, such as Figure 2 shown.

[0039] In this embodiment, the integration module 1001 can integrate the voltage at one end of the shunt Rs. The integration module 1001 can be a conventional integration circuit. After the capacitor of the integration module 1001 is fully charged, the voltage of the module can be converted into a level signal by the comparison module 1002. The level signal can be a pulse signal, etc. The output of the comparison module 1002 can be connected to a battery control system or other microcontroller so that the control module can calculate the number of times the integration module 1001 is fully charged based on the level signal. At the same time, the level signal can also be input into the discharge module 1003 to control the integration module 1001 to discharge so as to re-integrate. The control module can estimate the battery SOC based on the number of integrations of the integration module 1001 and the capacitance value of the capacitor.

[0040] In an example of this embodiment, the integration module 1001 includes a first integration circuit and a second integration circuit, and the comparison module 1002 includes a first comparison circuit, a second comparison circuit and an SR latch; the shunt Rs, the first input ends of the first integration circuit, the first comparison circuit and the SR latch are connected in sequence; the shunt Rs, the second input ends of the second integration circuit, the second comparison circuit and the SR latch are connected in sequence.

[0041] In this embodiment, the integration module 1001 may include two integration circuits connected in parallel. At the same time, the comparison module 1002 correspondingly includes two comparison circuits. The two integration circuits and the two comparison circuits are connected correspondingly to serve as a dual-channel SOC estimation circuit. When the integration module 1001 of one channel completes integration and is discharged, integration can be seamlessly performed through the other channel circuit. Compared with a single-channel circuit, the error of the SOC accumulated due to discharge can be reduced, thereby improving the accuracy of the final SOC.

[0042] In one example of this embodiment, a first integration circuit includes a first resistor R1, a first capacitor C1, and a first operational amplifier P1, wherein a shunt Rs, the first resistor R1, and the first capacitor C1 are connected in sequence, and the first capacitor C1 is connected between the inverting input terminal and the output terminal of the first operational amplifier P1. A second integration circuit includes a second resistor R2, a second capacitor C2, and a second operational amplifier P2, wherein the shunt Rs, the second resistor R2, and the second capacitor C2 are connected in sequence, and the second capacitor C2 is connected between the inverting input terminal and the output terminal of the second operational amplifier P2. The positive input terminals of the first operational amplifier P1 and the second operational amplifier P2 are connected to a power supply.

[0043] like Figure 2As shown, the first integration circuit includes a first resistor R1, a first capacitor C1, and a first operational discharger, wherein one end of the first resistor R1 is connected to a shunt Rs and the other end is connected to the capacitor. The inverting input of the first operational amplifier P1 is connected between the first resistor R1 and the first capacitor C1, and the positive input is connected to the power supply. Similarly, the second integration circuit includes a second resistor R2, a second capacitor C2, and a second operational discharger, wherein one end of the second resistor R2 is connected to the shunt Rs and the other end is connected to the capacitor. The inverting input of the second operational amplifier P2 is connected between the second resistor R2 and the second capacitor C2, and the positive input is connected to the power supply. In this example, the integration circuit can proportionally convert the battery's charge and discharge current into a voltage value across the capacitor, which can then be compared with a reference voltage in the comparison circuit.

[0044] In one example of this embodiment, the first comparison circuit includes a first comparator, a second comparator, and a first AND gate circuit; the inverting input of the first comparator and the positive input of the second comparator are respectively connected to the output of the first operational amplifier P1, the positive input of the first comparator and the inverting input of the second comparator are respectively input with reference voltages for the battery charging state and the battery discharging state, and the outputs of the first and second comparators are connected to the input of the first AND gate circuit; the second comparison circuit includes a third comparator, a fourth comparator, and a second AND gate circuit; the inverting input of the third comparator and the positive input of the fourth comparator are respectively connected to the output of the second operational amplifier P2, the positive input of the third comparator and the inverting input of the fourth comparator are respectively input with reference voltages for the battery charging state and the battery discharging state, and the outputs of the third and fourth comparators are connected to the input of the second AND gate circuit. The output of the first AND gate is connected to the first input of the SR latch, and the output of the second AND gate is connected to the second input of the SR latch.

[0045] In this embodiment, if Figure 2 As shown, the first comparison circuit includes two comparators, namely a first comparator and a second comparator, wherein the inverting input terminal of the first comparator and the positive input terminal of the second comparator are connected to the output terminal of the first operational amplifier P1. At the same time, the positive input terminal of the first comparator inputs the reference voltage of the battery in the charging state, which can be determined based on the capacity of the first capacitor C1, and the inverting input terminal of the second comparator inputs the reference voltage of the discharge state, which can be a negative reference voltage in the charging state. In this embodiment, based on the charge and discharge state of the battery, the voltage at the capacitor terminal may be positive or negative. Therefore, when the capacitor is fully charged, one of the first comparator and the second comparator can output a low level, and the other comparator will definitely output a high level. After passing through the first AND gate circuit, the final output result of the first channel is a low level.

[0046] Similarly, the second comparison circuit includes two comparators, namely a third comparator and a fourth comparator, wherein the inverting input terminal of the third comparator and the positive input terminal of the fourth comparator are connected to the output terminal of the second operational amplifier P2. At the same time, the positive input terminal of the second comparator inputs the reference voltage of the battery in the charging state, which can be determined based on the capacity of the second capacitor C2. The inverting input terminal of the fourth comparator inputs the reference voltage of the discharge state, which can be a negative reference voltage in the charging state.

[0047] In this embodiment, the component selections of the first integration circuit and the first comparison circuit may be consistent with those of the second integration circuit and the second comparison circuit, respectively.

[0048] In this embodiment, the output terminals of the first and second AND gates are connected to the first and second input terminals of the SR latch, respectively. The SR latch is composed of two NAND gates, and its state is controlled by its two input terminals. Each time the first and second AND gates output a low level, the square wave output by the SR latch undergoes a level shift.

[0049] In this example, due to the circuit characteristics, the pulse interval output by the comparator is too short, and directly outputting it to the microcontroller may cause problems such as loss. Using a latch can record the pulse and convert it into a level flip, thereby outputting a more regular rectangular wave, which can reduce the problem of second-pulse signal loss.

[0050] In an example of this embodiment, the discharge module 1003 includes a first discharge circuit and a second discharge circuit; the first discharge circuit includes a first switch tube and a third resistor Rd1, the first discharge circuit is connected in parallel with the first capacitor C1, the first switch tube is connected to the first output end of the SR latch, and the first switch tube is controlled to be turned on based on the level signal output by the first output end, so that the first capacitor C1 is discharged; the second discharge circuit includes a second switch tube and a fourth resistor Rd2, the second discharge circuit is connected in parallel with the second capacitor C2, the second switch tube is connected to the second output end of the SR latch, and the second switch tube is controlled to be turned on based on the level signal output by the second output end, so that the second capacitor C2 is discharged.

[0051] In one example, Figure 2As shown, corresponding to the dual-channel SOC estimation circuit, its corresponding discharge circuit also includes two, and the device selection of these two discharge circuits can be the same. In this example, the first discharge circuit can include a first switch tube and a third resistor Rd1. The first switch tube can be a switch tube such as a MOS tube. For example, the gate of the first switch tube is connected to the first output terminal of the SR latch, and the source and drain are connected to the third resistor Rd1 and the first capacitor C1 respectively. After the first capacitor C1 is fully charged, the first output terminal of the SR latch outputs a high level. At this time, the first switch tube is continuously turned on, and the first capacitor C1 continues to discharge. After the second capacitor C2 is fully discharged, the first switch tube is turned off, so that the first capacitor C1 and the second capacitor C2 are charged in a cycle. The second discharge circuit is similar.

[0052] In this example, the capacitor discharge process of the traditional integration circuit needs to quickly enter the next integration stage, and the time must be controlled within a negligible time. Therefore, a discharge bypass without resistance is required. However, a bypass without resistance will generate an impact current during discharge, which can easily cause circuit failure. The embodiment of the present application does not have special requirements for the discharge time. Therefore, adding a discharge bypass with resistance eliminates this problem.

[0053] In this embodiment, the shunt Rs is connected in series with the battery charging and discharging main circuit to convert the battery charging and discharging current into a voltage signal in proportion. The battery SOC estimation circuit can integrate the voltage signal on the main circuit through the integration module 1001, and convert it into a level signal that determines the number of integrations through the comparison module 1002. The discharge module 1003 can also control the integration module 1001 to discharge and re-integrate through the level signal. Through the above circuit, the control unit can determine the change in the battery charge amount only by determining the number of integrations and the integrated charge amount of the integration module 1001 to determine the battery SOC. There is no need to perform high-frequency integration operations, which reduces the calculation amount of the control module and solves the problem of excessive burden on the control module.

[0054] In an example of this embodiment, the circuit includes a control module, any output terminal of the SR latch is connected to the control module, and the control module calculates the SOC of the battery based on the level signal output by the output terminal.

[0055] In this example, any output of the SR latch is connected to the control module, which can calculate the battery SOC by the number of transitions of the output level signal. For example, the actual current integral value of the main circuit is Q 实 , the actual current is I 实 , the single integral of the first capacitor C1 or the second capacitor C2 is Q C , the current charging the capacitor is I C , then according to the charge formula, the following expression can be listed:

[0056]

[0057] According to Ohm's law, taking the first capacitor C1 as an example, we can get I 实 with I C Relationship:

[0058]

[0059] And because when the capacitor is "full" once, the voltage across it should be the reference voltage Vref, according to the capacitance formula:

[0060]

[0061] Arranged:

[0062]

[0063] Since R S , R1 is a constant, and after a slight rearrangement of the above formula, the relationship between the actual single integral and the circuit component parameters is:

[0064]

[0065] As can be seen from the above formula, if the resistance of the first resistor R1, the resistance of the shunt Rs, and the first capacitor C1 are known in advance, the value of the single integrated charge can be determined based on the above formula and stored in the control unit. At the same time, the controller can determine the current charging or discharging state based on software and calculate the battery SOC based on this.

[0066] In this embodiment, the pin connected to the control module and the SR latch can be configured as an external interrupt channel. When a pulse signal is generated at the output of the SR latch, the software can enter the relevant terminal processing function. After entering the interrupt processing function, the control module can obtain the last battery power value SOC' and obtain the single pulse current integral value Q from the initially configured parameters. 单 and battery rated capacity Q 额 .

[0067] SOC' and Q 单 With Q 额 The current SOC is obtained by adding the ratio of

[0068]

[0069] It should be noted that a single pulse represents two level flips, so the relationship between the integrated power of a single pulse and the single level flip of the level signal is Q 单 =2Q 实 .

[0070] In an example of this embodiment, the circuit further includes a charge and discharge detection module for detecting whether the battery is in a charging state or a discharging state.

[0071] The charge and discharge detection module includes a fifth comparator, the non-inverting input terminal and the reverse input terminal of the fifth comparator are respectively connected to the two ends of the shunt Rs, and the fifth comparator is used to output a state signal representing whether the battery is in a charging state or a discharging state.

[0072] In this embodiment, a charge and discharge detection module can also be provided in the circuit. Specifically, the current direction, that is, whether it is in a charging state or a discharging state, can be determined by the voltage across the shunt Rs in the main circuit of the battery. In this example, the charge and discharge detection module may include a fifth comparator. The two input terminals of the fifth comparator may be respectively connected to the two terminals of the shunt Rs. By comparing the voltages across the two terminals, the charge and discharge state of the battery can be determined based on the output comparison result. In this example, the output terminal of the third comparator may also be connected to the control module.

[0073] In this example, compared with monitoring the charge and discharge status through software, the additional charge and discharge detection module can further reduce the operating resources of the control module through software monitoring, reduce the burden on the control module, and save computing power.

[0074] In an example of this embodiment, a battery module is also introduced, including the battery SOC estimation circuit 1000 of any of the above embodiments.

[0075] In one example of this embodiment, an electric device is also introduced, including a battery module and a battery SOC estimation circuit 1000 of any of the above embodiments, and can achieve the same technical effect. To avoid repetition, it is not described here. In this embodiment, the electric device can be a vehicle.

[0076] The various embodiments of this disclosure are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the device and apparatus embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For relevant portions, reference can be made to the descriptions of the method embodiments.

[0077] The above embodiments mainly focus on the differences from other embodiments, but it should be clear to those skilled in the art that the above embodiments can be used alone or in combination with each other as needed.

[0078] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A battery SOC estimation circuit, characterized in that: A shunt is provided on the main circuit of the battery, and the circuit includes: an integration module connected to the shunt, the integration module being configured to integrate the voltage at one end of the shunt; a comparison module, the comparison module being connected to the integration module, the comparison module being used to convert the voltage of the integration module into a level signal, the level signal being used to determine the number of integration times of the integration module; The discharge module is connected to the integration module and the comparison module respectively, and the discharge module controls the integration module to discharge based on the level signal.

2. The circuit according to claim 1, wherein: The integration module includes a first integration circuit and a second integration circuit, and the comparison module includes a first comparison circuit, a second comparison circuit and an SR latch; The current divider, the first integration circuit, the first comparison circuit, and the first input terminal of the SR latch are connected in sequence; The current divider, the second integration circuit, the second comparison circuit, and the second input terminal of the SR latch are connected in sequence.

3. The circuit according to claim 2, characterized in that include: The first integration circuit includes a first resistor, a first capacitor, and a first operational amplifier, wherein the shunt, the first resistor, and the first capacitor are connected in sequence, and the first capacitor is connected between the inverting input terminal and the output terminal of the first operational amplifier; The second integration circuit includes a second resistor, a second capacitor, and a second operational amplifier, wherein the shunt, the second resistor, and the second capacitor are connected in sequence, and the second capacitor is connected between the inverting input terminal and the output terminal of the second operational amplifier; The positive input terminals of the first operational amplifier and the second operational amplifier are connected to a power supply.

4. The circuit according to claim 3, characterized in that include: The first comparison circuit includes a first comparator, a second comparator and a first AND gate circuit; The inverting input terminal of the first comparator and the positive input terminal of the second comparator are respectively connected to the output terminal of the first operational amplifier, the positive input terminal of the first comparator and the inverting input terminal of the second comparator are respectively input with reference voltages of the battery in the charging state and the discharging state, and the output terminals of the first comparator and the second comparator are connected to the input terminal of the first AND gate circuit; The second comparison circuit includes a third comparator, a fourth comparator and a second AND gate circuit; The inverting input terminal of the third comparator and the positive input terminal of the fourth comparator are respectively connected to the output terminal of the second operational amplifier, the positive input terminal of the third comparator and the inverting input terminal of the fourth comparator are respectively input with reference voltages of the battery in the charging state and the discharging state, and the output terminals of the third comparator and the fourth comparator are connected to the input terminal of the second AND gate circuit; The output end of the first AND gate circuit is connected to the first input end of the SR latch, and the output end of the second AND gate circuit is connected to the second input end of the SR latch.

5. The circuit according to claim 4, characterized in that The discharge module includes a first discharge circuit and a second discharge circuit; The first discharge circuit includes a first switch tube and a third resistor. The first discharge circuit is connected in parallel with the first capacitor. The first switch tube is connected to the first output terminal of the SR latch and controls the first switch tube to be turned on based on a level signal output by the first output terminal, so as to discharge the first capacitor. The second discharge circuit includes a second switch tube and a fourth resistor. The second discharge circuit is connected in parallel with the second capacitor. The second switch tube is connected to the second output end of the SR latch and controls the second switch tube to be turned on based on the level signal output by the second output end to discharge the second capacitor.

6. The circuit according to claim 5, characterized in that The circuit includes a control module. Any output terminal of the SR latch is connected to the control module. The control module calculates the SOC of the battery based on the level signal output by the output terminal.

7. The circuit according to claim 1, wherein: The circuit further includes a charge and discharge detection module for detecting whether the battery is in a charging state or a discharging state.

8. The circuit according to claim 7, characterized in that The charge and discharge detection module includes a fifth comparator, wherein a non-inverting input terminal and an inverting input terminal of the fifth comparator are respectively connected to two ends of the shunt, and the fifth comparator is used to output a status signal indicating whether the battery is in a charging state or a discharging state.

9. A battery module, characterized in that: A battery SOC estimation circuit comprising the battery SOC estimation circuit according to any one of claims 1 to 8.

10. An electrical device, characterized in that: The invention comprises a battery module and a battery SOC estimation circuit according to any one of claims 1 to 8.

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