Array substrate with high driving performance and liquid crystal display panel

Abstract

The utility model discloses an array substrate with high driving performance and a liquid crystal display panel. The substrate comprises a grid electrode layer, a source and drain electrode layer, a common electrode layer, a pixel electrode layer, a first via hole, a second via hole and a third via hole, a first wiring area of the pixel electrode layer is in first lap joint with the grid electrode layer through a first via hole, the pixel electrode layer of the first wiring area is in second lap joint with the common electrode layer through a second via hole, and a second wiring area of the pixel electrode layer is in third lap joint with the source and drain electrode layer through a third via hole; and through the first lap joint, the second lap joint and the third lap joint, a first capacitor, a second capacitor and a third capacitor which are connected in parallel are formed between the gate layer and the source and drain electrode layer, between the source and drain electrode layer and the common electrode layer and between the pixel electrode layer and the common electrode layer respectively. According to the array substrate, under the condition that the occupied area is not increased, the capacitance value of the array substrate is increased, and the driving capacity is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of array substrates of liquid crystal displays, and in particular to an array substrate and a liquid crystal display panel with high driving performance. Background Art

[0002] With the development of liquid crystal display technology, narrow-border displays have become a major trend in the development of high-quality displays due to their simplicity, aesthetics, and large viewing area for the same size. Liquid crystal display panels, also known as thin-film transistor (TFT) liquid crystal display panels, primarily consist of an array substrate, a color filter substrate, and liquid crystal disposed between the array and color filter substrates. The array substrate is provided with multiple TFTs. The basic structure of a TFT consists of a substrate, a gate, a gate insulation layer, an active layer, a source / drain (S / D) electrode, and an insulating protective layer. Liquid crystal display panels primarily utilize a voltage difference between the pixel electrodes on the array substrate and the common electrode to drive the deflection of liquid crystal molecules, thereby emitting light of varying brightness to display images.

[0003] Existing liquid crystal display panels require capacitors to be manufactured. The capacitance of a capacitor is related to the area of ​​the capacitor plates and the distance between the capacitor plates. As the area increases, the capacitance increases, and as the distance decreases, the capacitance increases.

[0004] However, array circuits in existing liquid crystal display panels, such as GIP circuits, require capacitors. However, due to limitations such as the frame, it is usually impossible to increase the capacitance by increasing the area, resulting in insufficient driving of the liquid crystal display panel.

[0005] Therefore, at present, there is an urgent need for a solution to increase the capacitance value without increasing the space occupied, so as to improve the display effect and thus enhance the competitiveness of the product. Utility Model Content

[0006] The array circuit in the existing liquid crystal display panel has insufficient driving capability of the capacitance value due to the limitation of the narrow frame structure design.

[0007] In response to the above problems, an array substrate and liquid crystal display panel with high driving performance are proposed. By partitioning the wiring of the pixel electrode layer, and connecting the first wiring area and the gate layer of the pixel electrode layer through vias, connecting the first wiring area and the common electrode layer of the pixel electrode layer through vias, and connecting the second wiring area and the source and drain layer of the pixel electrode layer through vias, three capacitors in parallel are formed. Without increasing the occupied area, the capacitance value of the array substrate is increased, and the driving capability is improved. This solves the problem of insufficient driving capability of the capacitance value of the array circuit in the existing liquid crystal display panel due to the structural design of the narrow frame.

[0008] In a first aspect, an array substrate with high driving performance includes:

[0009] gate layer;

[0010] source and drain layers;

[0011] common electrode layer;

[0012] pixel electrode layer;

[0013] First via;

[0014] Second via;

[0015] The third via;

[0016] The first wiring area of ​​the pixel electrode layer is firstly overlapped with the gate layer through the first via hole, the pixel electrode layer of the first wiring area is also secondly overlapped with the common electrode layer through the second via hole, and the second wiring area of ​​the pixel electrode layer is thirdly overlapped with the source and drain electrode layer through the third via hole;

[0017] Through the first overlap, the second overlap and the third overlap, a first capacitor, a second capacitor and a third capacitor connected in parallel are formed between the gate layer and the source-drain layer, between the source-drain layer and the common electrode layer, and between the pixel electrode layer and the common electrode layer respectively.

[0018] In conjunction with the array substrate with high driving performance described in the first aspect of the present utility model, in a first possible implementation manner, the array substrate further includes an insulating layer, an isolation layer, and a planarization layer;

[0019] The gate layer is made in the insulating layer, the isolation layer is made on the insulating layer, the flat layer is made in the isolation layer, the source and drain layers are made in the flat layer, and the gate layer and the source and drain layers serve as two plates of the first capacitor respectively, overlapping each other.

[0020] In conjunction with the array substrate with high driving performance described in the first aspect of the present utility model, in a second possible implementation manner, the array substrate further includes an insulating layer and a planar layer;

[0021] The gate layer is made in the insulating layer, the planar layer is made in the insulating layer, the source and drain layers are made in the planar layer, and the gate layer and the source and drain layers serve as two plates of the first capacitor respectively, overlapping each other.

[0022] In combination with the first or second possible implementation manner of the first aspect of the present utility model, in a third possible implementation manner, the array substrate further includes a passivation layer;

[0023] The passivation layer is formed on the flat layer, and the common electrode layer is formed in the passivation layer. The common electrode layer and the source and drain electrode layer serve as two plates of the second capacitor, respectively, and overlap with each other.

[0024] In combination with the third possible implementation of the first aspect of the present invention, in a fourth possible implementation, the first routing area and the second routing area of ​​the pixel electrode layer are respectively made on the passivation layer, and the second routing area and the common electrode layer serve as the two plates of the third capacitor, respectively, overlapping up and down.

[0025] In combination with the fourth possible implementation manner of the first aspect of the present utility model, in a fifth possible implementation manner, the array substrate further includes a glass substrate;

[0026] The glass substrate is disposed on a lower side of the insulating layer.

[0027] In a second aspect, a liquid crystal display panel includes the array substrate with high driving performance described in the first aspect.

[0028] The high-driving performance array substrate and liquid crystal display panel described in the present invention are implemented by partitioning the wiring of the pixel electrode layer, and connecting the first wiring area of ​​the pixel electrode layer and the gate layer through vias, connecting the first wiring area of ​​the pixel electrode layer and the common electrode layer through vias, and connecting the second wiring area of ​​the pixel electrode layer and the source and drain layer through vias to form three parallel capacitors. Without increasing the occupied area, the capacitance value of the array substrate is increased, the driving capability is improved, and the problem of insufficient driving capability of the capacitance value of the array circuit in the existing liquid crystal display panel due to the structural design of the narrow frame is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 Schematic top view of a capacitor film layer in the prior art;

[0031] Figure 2 In the existing technology Figure 1 Schematic diagram of the main view of the corresponding capacitor film layer;

[0032] Figure 3 Schematic diagram of the film layer structure of the array substrate of Example 1 of the present utility model;

[0033] Figure 4Schematic diagram of the film layer structure of the array substrate of Example 2 of the present utility model;

[0034] Figure 5 This is a schematic diagram of the capacitor structure of the array substrate in the present invention.

[0035] Components and their serial numbers:

[0036] 110 - glass substrate, 120 - insulating layer, 130 - isolation layer, 140 - flat layer, 150 - passivation layer, 210 - gate layer, 220 - source and drain layer, 230 - common electrode layer, 241 - first routing area, 242 - second routing area, 310 - first via, 320 - second via, 330 - third via. DETAILED DESCRIPTION

[0037] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0042] The array circuit in the existing liquid crystal display panel has insufficient driving capability of the capacitance value due to the limitation of the narrow frame structure design.

[0043] like Figure 1 and Figure 2 , Figure 1 is a schematic top view of a capacitor film layer in the prior art, Figure 2 In the existing technology Figure 1 Schematic diagram of the main view of the corresponding capacitor film layer;

[0044] In the prior art, only the gate layer (Gate) 210 and the source-drain layer (SD) 220 metal are used as capacitor plates to form a capacitance value, which is relatively small. Figure 2 The capacitance value cannot meet the capacitance requirements of existing panels.

[0045] In order to solve the above problems, an array substrate and a liquid crystal display panel with high driving performance are proposed.

[0046] First, as Figure 3 , Figure 3 This is a schematic diagram of the film layer structure of the array substrate of Example 1 of the present utility model.

[0047] A high-driving-performance array substrate includes a gate layer (Gate) 210, a source-drain layer (SD) 220, a common electrode layer (VITO) 230, a pixel electrode layer (PITO), a first via hole 310, a second via hole 320, and a third via hole 330; a first wiring area 241 of the pixel electrode layer (PITO) is first overlapped with the gate layer (Gate) 210 through the first via hole 310, and the first wiring area 241 of the pixel electrode layer (PITO) is also second overlapped with the common electrode layer (VITO) 230 through the second via hole 320; a second wiring area 242 of the pixel electrode layer (PITO) is third overlapped with the source-drain layer (SD) 220 through the third via hole 330; through the first overlap, the second overlap, and the third overlap, as Figure 5 , Figure 5This schematic diagram illustrates the capacitor structure of the array substrate of the present invention. A first capacitor, a second capacitor, and a third capacitor are formed in parallel between the gate layer (Gate) 210 and the source / drain layer (SD) 220, between the source / drain layer (SD) 220 and the common electrode layer (VITO) 230, and between the pixel electrode layer (PITO) and the common electrode layer (VITO) 230, respectively. By partitioning the wiring of the pixel electrode layer (PITO), and connecting the first wiring area 241 of the pixel electrode layer (PITO) to the gate layer (Gate) 210, the first wiring area 241 of the pixel electrode layer (PITO) to the common electrode layer, and the second wiring area 242 of the pixel electrode layer (PITO) to the source / drain layer (SD) 220 through vias, three parallel capacitors are formed. This increases the capacitance of the array substrate and improves driving capability without increasing the occupied area, thus resolving the problem of insufficient driving capability of the capacitance of array circuits in existing liquid crystal display panels due to the narrow bezel design.

[0048] Furthermore, the array substrate also includes an insulating layer 120, an isolation layer 130 and a flat layer 140; the gate layer (Gate) 210 is made in the insulating layer 120, the isolation layer 130 is made on the insulating layer 120, the flat layer 140 is made in the isolation layer 130, and the source-drain layer (SD) 220 is made in the flat layer 140, and the gate layer (Gate) 210 and the source-drain layer (SD) 220 serve as two plates of the first capacitor, respectively, overlapping up and down.

[0049] Furthermore, the array substrate also includes a passivation layer 150; the passivation layer 150 is made on the flat layer 140, and the common electrode layer (VITO) 230 is made in the passivation layer 150, and the common electrode layer (VITO) 230 and the source and drain layer (SD) 220 serve as two plates of the second capacitor, overlapping each other.

[0050] Furthermore, the first wiring region 241 and the second wiring region 242 of the pixel electrode layer (PITO) are respectively fabricated on the passivation layer 150 , and the second wiring region 242 and the common electrode layer (VITO) 230 serve as two plates of the third capacitor, overlapping each other.

[0051] Furthermore, the array substrate further includes a glass substrate 110 ; the glass substrate 110 is disposed on the lower side of the insulating layer 120 .

[0052] In embodiment 1, the array substrate includes, from the lower right to the top, the following components:

[0053] Glass substrate 110 , insulating layer 120 , gate layer (Gate) 210 , isolation layer 130 , planarization layer 140 , source / drain layer (SD) 220 , passivation layer 150 , common electrode layer (VITO) 230 , pixel electrode layer (PITO).

[0054] In this embodiment, if Figure 5 The gate metal and VITO are connected through PITO vias, realizing the capacitance C2 between VITO and SD, while retaining the original capacitance C1 formed by the gate and SD. In addition, PITO is connected to SD through vias, realizing the capacitance C3 between PITO and VITO.

[0055] Obviously, C1, C2 and C3 in this embodiment are in a parallel relationship. When the capacitors are connected in parallel, the capacitance value increases, which is much larger than the capacitance value in the original technology. The capacitance value is increased without increasing the plate area, thereby improving the competitiveness of the product.

[0056] like Figure 4 , Figure 4 This is a schematic diagram of the film layer structure of an array substrate according to Example 2 of the present invention. The array substrate further includes an insulating layer 120 and a planar layer 140. A gate layer 210 is fabricated within the insulating layer 120, and the planar layer 140 is fabricated within the insulating layer 120. A source-drain layer (SD) 220 is fabricated within the planar layer 140. The gate layer 210 and the source-drain layer (SD) 220 serve as the two plates of a first capacitor, overlapping one another.

[0057] Different from the first embodiment, in this embodiment, the isolation layer 130 is missing, so that the distance between the source-drain layer (SD) 220 and the gate layer (Gate) 210 is reduced, and the capacitance value of the generated first capacitor is larger.

[0058] In a second aspect, a liquid crystal display panel includes the array substrate with high driving performance according to the first aspect.

[0059] The high-driving performance array substrate and liquid crystal display panel of the present invention partition the wiring of the pixel electrode layer (PITO) and connect the first wiring area 241 of the pixel electrode layer (PITO) and the gate layer (Gate) 210 through vias, connect the first wiring area 241 of the pixel electrode layer (PITO) and the common electrode layer through vias, and connect the second wiring area 242 of the pixel electrode layer (PITO) and the source-drain layer (SD) 220 through vias to form three parallel capacitors. Without increasing the occupied area, the capacitance value of the array substrate is increased, and the driving capability is improved. This solves the problem of insufficient driving capability of the capacitance value of the array circuit in the existing liquid crystal display panel due to the structural design of the narrow frame.

[0060] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An array substrate with high driving performance, characterized in that: include: gate layer; source and drain layers; common electrode layer; pixel electrode layer; First via; Second via; The third via; The first wiring area of ​​the pixel electrode layer is firstly overlapped with the gate layer through the first via hole, the pixel electrode layer of the first wiring area is also secondly overlapped with the common electrode layer through the second via hole, and the second wiring area of ​​the pixel electrode layer is thirdly overlapped with the source and drain electrode layer through the third via hole; Through the first overlap, the second overlap and the third overlap, a first capacitor, a second capacitor and a third capacitor connected in parallel are formed between the gate layer and the source-drain layer, between the source-drain layer and the common electrode layer, and between the pixel electrode layer and the common electrode layer respectively.

2. The array substrate with high driving performance according to claim 1, characterized in that: The array substrate further includes an insulating layer, an isolation layer and a planarization layer; The gate layer is made in the insulating layer, the isolation layer is made on the insulating layer, the flat layer is made in the isolation layer, the source and drain layers are made in the flat layer, and the gate layer and the source and drain layers serve as two plates of the first capacitor respectively, overlapping each other.

3. The array substrate with high driving performance according to claim 2, characterized in that: The array substrate further includes an insulating layer and a planar layer; The gate layer is made in the insulating layer, the planar layer is made in the insulating layer, the source and drain layers are made in the planar layer, and the gate layer and the source and drain layers serve as two plates of the first capacitor respectively, overlapping each other.

4. The array substrate with high driving performance according to claim 2 or 3, characterized in that: The array substrate further includes a passivation layer; The passivation layer is formed on the flat layer, and the common electrode layer is formed in the passivation layer. The common electrode layer and the source and drain electrode layer serve as two plates of the second capacitor, respectively, and overlap with each other.

5. The array substrate with high driving performance according to claim 4, characterized in that: The first wiring region and the second wiring region of the pixel electrode layer are respectively formed on the passivation layer, and the second wiring region and the common electrode layer serve as two plates of the third capacitor, overlapping each other.

6. The array substrate with high driving performance according to claim 5, characterized in that: The array substrate further includes a glass substrate; The glass substrate is disposed on a lower side of the insulating layer.

7. A liquid crystal display panel, characterized in that: An array substrate with high driving performance comprising the array substrate according to any one of claims 1 to 6.

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