Array substrate and thin film transistor liquid crystal display panel

Abstract

The utility model discloses an array substrate and a thin film transistor liquid crystal display panel. The substrate comprises a grid electrode metal layer, a source and drain electrode metal layer, a common electrode layer, a first via hole and a second via hole. The gate metal layer is connected with the common electrode layer through a first via hole, the common electrode layer is connected with the source and drain metal layer through a second via hole, and the first end of the source and drain metal layer connecting part is aligned right above or partially overlapped with the second end of the gate metal layer connecting part according to a specified value; the first end and the second end are opposite in horizontal direction and close to each other. When the via holes are connected, the close ends of the source and drain electrode metal layer connecting part and the gate electrode metal layer connecting part are aligned or partially overlapped right above, so that the common electrode layer is prevented from climbing and then being overlapped with the source and drain electrode metal layer, and the problems that the gate electrode metal layer, the common electrode layer and the source and drain electrode metal layer are connected through the via holes, the climbing is more, and the power consumption is reduced are solved. Therefore, the problems of poor connection effect and resistance increase are solved, and the display quality is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of film layer connection of thin film transistor liquid crystal display panels, in particular to an array substrate and a thin film transistor liquid crystal display panel. Background Art

[0002] Thin-film transistor liquid crystal (TFT-LCD) displays utilize large-scale semiconductor integrated circuit manufacturing technology using new materials and processes. Thin-film transistors are formed on non-single-chip substrates such as glass or plastic substrates (though they can also be formed on wafers) through sputtering and chemical deposition processes to form the various films necessary for circuit manufacturing. Large-scale semiconductor integrated circuits are then produced by processing these films. The structure of a TFT-LCD panel generally consists of a color filter substrate (CF substrate), a thin-film transistor array substrate (TFT substrate), and a liquid crystal layer positioned between the two substrates. A driving voltage is applied across the two glass substrates to control the rotation of the liquid crystal molecules in the liquid crystal layer, refracting light from the backlight module to produce the image. By adjusting the electric field strength through voltage variations, the twist and angle of the liquid crystal material can be controlled, thereby controlling the amount of light transmitted through that area, ultimately achieving the desired image.

[0003] In the process of connecting each thin film via, the gate metal layer is connected to the common electrode layer through the via, and the common electrode layer is connected to the source and drain metal layer through the via, thereby realizing the connection between the gate metal layer and the source and drain metal layer. However, in the actual film formation process, there is a slope angle, and the distance and film thickness between the gate metal layer and the source and drain metal layer will affect the connection effect of the top common electrode layer. If the slope is too much, the common electrode layer will climb and cause the connection effect to deteriorate. At the same time, there may be differences in resistance after film formation, which may affect the display effect and thus reduce the display quality. Utility Model Content

[0004] In existing thin film transistor liquid crystal display panels, when the gate metal layer, common electrode layer, and source and drain metal layers are connected through vias, there is a lot of climbing, which not only deteriorates the connection effect, but also increases the resistance after film formation, reducing the display quality.

[0005] In response to the above problems, an array substrate and a thin-film transistor liquid crystal display panel are proposed. When connecting through vias, the source and drain metal layer connection parts are aligned or partially overlapped with the near ends of the gate metal layer connection parts, thereby avoiding the common electrode layer from climbing and then overlapping with the source and drain metal layers. This solves the problem that when the gate metal layer, the common electrode layer, and the source and drain metal layer are connected through vias, there is a lot of climbing, which leads to poor connection effect and increased resistance, thereby improving the display quality.

[0006] In a first aspect, an array substrate includes:

[0007] gate metal layer;

[0008] source and drain metal layers;

[0009] common electrode layer;

[0010] First via;

[0011] Second via;

[0012] The gate metal layer is connected to the common electrode layer through the first via hole, and the common electrode layer is connected to the source and drain metal layer through the second via hole, and:

[0013] The first end of the source-drain metal layer connecting portion and the second end of the gate metal layer connecting portion are aligned directly above each other or partially overlapped by a specified value;

[0014] The first end and the second end are in opposite horizontal directions and close to each other.

[0015] In conjunction with the array substrate described in the first aspect of the present utility model, in a first possible implementation manner, the array substrate further includes:

[0016] glass substrate;

[0017] Insulation layer;

[0018] The insulating layer is formed on the glass substrate, and the gate metal layer is formed in the insulating layer.

[0019] In combination with the first possible implementation of the first aspect of the present utility model, in a second possible implementation, the array substrate further includes:

[0020] Isolation layer;

[0021] The isolation layer is formed on the insulating layer, and the source-drain metal layer is formed on the isolation layer.

[0022] In combination with the second possible implementation manner of the first aspect of the present utility model, in a third possible implementation manner, the array substrate further includes:

[0023] flat layer;

[0024] The planar layer is formed on the isolation layer, and the source and drain metal layers are formed in the planar layer.

[0025] In combination with the third possible implementation manner of the first aspect of the present utility model, in a fourth possible implementation manner, the array substrate further includes:

[0026] Passivation layer;

[0027] The passivation layer is formed on the planar layer, and the common electrode layer is fabricated in the passivation layer and formed on the planar layer.

[0028] In combination with the fourth possible implementation manner of the first aspect of the present utility model, in a fifth possible implementation manner, the array substrate further includes:

[0029] pixel electrode layer;

[0030] The pixel electrode layer is formed on the passivation layer.

[0031] In a second aspect, a thin film transistor liquid crystal display panel includes the array substrate described in the first aspect.

[0032] The array substrate and thin-film transistor liquid crystal display panel described in the present invention are implemented by aligning or partially overlapping the proximal ends of the source-drain metal layer connection portion and the gate metal layer connection portion directly above each other during via connection, thereby preventing the common electrode layer from climbing and then overlapping with the source-drain metal layer. This solves the problem of excessive climbing when the gate metal layer, the common electrode layer, and the source-drain metal layer are connected through vias, resulting in poor connection effect and increased resistance, thereby improving display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a schematic diagram of the first structure of the array substrate film layer in the present utility model;

[0035] Figure 2 This is a schematic diagram of the second structure of the array substrate film layer in the present utility model;

[0036] Figure 3 This is a schematic diagram of the top view of the film layer of the array substrate in the present invention;

[0037] Figure 4 This is a third structural diagram of the array substrate film layer in the present invention;

[0038] The numbers in the accompanying drawings indicate the following parts: 100 - glass substrate, 200 - insulating layer, 300 - gate metal layer, 400 - isolation layer, 500 - flat layer, 600 - source and drain metal layer, 700 - passivation layer, 800 - common electrode layer, 900 - pixel electrode layer, 101 - first via hole, and 102 - second via hole. DETAILED DESCRIPTION

[0039] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0042] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0044] To address the above problems, an array substrate and a thin film transistor liquid crystal display panel are proposed.

[0045] In a first aspect, an array substrate includes a gate metal layer 300 (gate layer), a source / drain metal layer 600 (SD layer), a common electrode layer 800 (VITO layer), a first via 101 (con1), and a second via 101 (con2); the gate metal layer 300 (gate layer) is connected to the common electrode layer 800 (VITO layer) through the first via 101 (con1), and the common electrode layer 800 (VITO layer) is connected to the source / drain metal layer 600 (SD layer) through the second via 101 (con2), and a first end of a connecting portion of the source / drain metal layer 600 (SD layer) and a second end of a connecting portion of the gate metal layer 300 (gate layer) are aligned directly above or partially overlapped by a specified value; the first end and the second end are horizontally opposite and close to each other.

[0046] In this embodiment, the first end and the second end are the close ends of the source-drain metal layer 600 (SD layer) and the gate metal layer 300 (gate layer). In order to reduce the slope of the common electrode layer 800 (VITO layer), one end of the source-drain metal layer 600 (SD layer) can be aligned close to one end of the gate metal layer 300 (gate layer) directly above. Figure 1 , Figure 1 This is a schematic diagram of the first structure of the array substrate film layer in the present invention. After alignment, the common electrode layer 800 (VITO layer) and the source and drain metal layer 600 (SD layer) overlap more smoothly without climbing.

[0047] In another preferred embodiment, in order to reduce the slope of the common electrode layer 800 (VITO layer), one end of the source and drain metal layer 600 (SD layer) can be overlapped with one end of the gate metal layer 300 (gate layer) directly above. Figure 1 , Figure 1 This is a schematic diagram of the second structure of the array substrate film layer in the present invention. After overlapping, the common electrode layer 800 (VITO layer) and the source / drain metal layer 600 (SD layer) overlap without any slope, resulting in a smoother connection. By aligning or partially overlapping the proximal ends of the source / drain metal layer 600 (SD layer) and the gate metal layer 300 (gate layer) during via connections, the common electrode layer 800 (VITO layer) is prevented from having to overlap the source / drain metal layer 600 (SD layer) by slope. This solves the problem of significant slope when connecting the gate metal layer 300 (gate layer), common electrode layer 800 (VITO layer), and source / drain metal layer 600 (SD layer) through vias, resulting in poor connection quality and increased resistance. This improves display quality.

[0048] Depend on Figure 1 and Figure 2As can be seen, the array substrate in this embodiment further includes: an isolation layer 400, a glass substrate 100, an insulating layer 200, a planarization layer 500, a passivation layer 700, and a pixel electrode layer 900 (PITO layer). The insulating layer 200 is formed on the glass substrate 100, and the gate metal layer 300 (gate layer) is formed within the insulating layer 200. The isolation layer 400 is formed on the insulating layer 200, and the source / drain metal layer 600 (SD layer) is formed on the isolation layer 400. The planarization layer 500 is formed on the isolation layer 400, and the source / drain metal layer 600 (SD layer) is formed within the planarization layer 500. The passivation layer 700 is formed on the planarization layer 500, and the common electrode layer 800 (VITO layer) is formed within the passivation layer 700 and formed on the planarization layer 500. The pixel electrode layer 900 (PITO layer) is formed on the passivation layer 700.

[0049] In specific implementation, Figure 3 , Figure 3 This is a schematic diagram of the top view structure of the array substrate film layer in the present invention, in which the gate metal layer 300 (gate layer) and the source and drain metal layer 600 (SD layer) partially overlap. Figure 4 This is a third structural diagram of the array substrate film layer in the present invention; Figure 4 It can be seen that the connection between the common electrode layer 800 (VITO layer) and the source and drain metals does not go through a slope, and a smooth overlap between the two is achieved.

[0050] In a second aspect, a thin film transistor liquid crystal display panel includes the array substrate of the first aspect.

[0051] The array substrate and thin-film transistor liquid crystal display panel of the present invention align or partially overlap the proximal ends of the source-drain metal layer connection portion and the gate metal layer connection portion when connecting vias, thereby preventing the common electrode layer from climbing and then overlapping with the source-drain metal layer. This solves the problem of excessive climbing when the gate metal layer, the common electrode layer, and the source-drain metal layer are connected through vias, resulting in poor connection effect and increased resistance, thereby improving display quality.

[0052] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: include: gate metal layer; source and drain metal layers; common electrode layer; First via; Second via; The gate metal layer is connected to the common electrode layer through the first via hole, and the common electrode layer is connected to the source and drain metal layer through the second via hole, and: The first end of the source-drain metal layer connecting portion and the second end of the gate metal layer connecting portion are aligned directly above each other or partially overlapped by a specified value; The first end and the second end are close ends of the source / drain metal layer and the gate metal layer.

2. The array substrate according to claim 1, wherein: The array substrate further includes: glass substrate; Insulation layer; The insulating layer is formed on the glass substrate, and the gate metal layer is formed in the insulating layer.

3. The array substrate according to claim 2, wherein: The array substrate further includes: Isolation layer; The isolation layer is formed on the insulating layer, and the source-drain metal layer is formed on the isolation layer.

4. The array substrate according to claim 3, wherein: The array substrate further includes: flat layer; The planar layer is formed on the isolation layer, and the source and drain metal layers are formed in the planar layer.

5. The array substrate according to claim 4, wherein: The array substrate further includes: Passivation layer; The passivation layer is formed on the planar layer, and the common electrode layer is fabricated in the passivation layer and formed on the planar layer.

6. The array substrate according to claim 5, wherein: The array substrate further includes: pixel electrode layer; The pixel electrode layer is formed on the passivation layer.

7. A thin film transistor liquid crystal display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 6.

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