Pixel of display device and display device

Abstract

The utility model discloses a pixel of a display device and the display device. The pixel includes: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node; a second transistor including a gate receiving a scan signal and a terminal connected to a second node; a third transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node and a terminal connected to the first node; a fifth transistor including a gate receiving a scan signal, a first terminal connected to a line; a sixth transistor including a terminal connected to the third node; and a light emitting element including an anode connected to the second terminal of the sixth transistor and a cathode connected to a line conveying a second power supply voltage.

Description

Technical Field

[0001] Embodiments of the present inventive concept relate to a display device, and more particularly, to a pixel of a display device and a display device including the pixel. Background Art

[0002] Due to process variations, degradation, etc., the driving transistors of pixels of a display device (such as an organic light emitting diode ("OLED") display device) may have different threshold voltages. Due to such variations in the threshold voltage, the pixels of the display device may not emit light with consistent brightness. In order to prevent or reduce brightness inconsistency, a pixel that performs a compensation operation to compensate for the threshold voltage of the driving transistor has been developed. For example, in order to perform the compensation operation in a diode connection method, the pixel may be diode-connected to the driving transistor, and a data voltage may be transmitted to the gate node of the driving transistor through the driving transistor connected in the diode manner. Therefore, in the pixel, a data voltage that compensates for the threshold voltage of the driving transistor may be applied to the gate node.

[0003] In a pixel that performs a compensation operation using a diode connection method, it is desirable that the gate node be initialized to an initialization voltage lower than the data voltage before the data voltage is applied to the gate node. The pixel may receive an initialization signal to provide the initialization voltage to the gate node. In addition, the pixel may further receive an emission signal for dividing a frame period into a non-emission period during which the pixel does not emit light and an emission period during which the pixel emits light. Utility Model Content

[0004] Some embodiments provide a pixel of a display device that operates normally without an initialization signal and an emission signal.

[0005] Some embodiments provide a display device that operates normally without an initialization signal and an emission signal.

[0006] In an embodiment of the present disclosure, a pixel of a display device is provided, the pixel including: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to a data line, and a second terminal connected to the second node; a third transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving a scan signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal; and a light-emitting element including an anode connected to the second terminal of the sixth transistor and a cathode connected to the line transmitting the second power supply voltage.

[0007] In an embodiment, the type of the second and third transistors may be different from the type of the fifth and sixth transistors.

[0008] In an embodiment, the second transistor and the third transistor may be N-type metal oxide semiconductor ("NMOS") transistors, and the fifth transistor and the sixth transistor may be P-type metal oxide semiconductor ("PMOS") transistors.

[0009] In an embodiment, when the scan signal has a relatively high level, the second transistor and the third transistor may be turned on, and the fifth transistor and the sixth transistor may be turned off. When the scan signal has a relatively low level, the second transistor and the third transistor may be turned off, and the fifth transistor and the sixth transistor may be turned on.

[0010] In an embodiment, the second transistor and the third transistor may be PMOS transistors, and the fifth transistor and the sixth transistor may be NMOS transistors.

[0011] In an embodiment, when the scan signal has a relatively high level, the second transistor and the third transistor may be turned off, and the fifth transistor and the sixth transistor may be turned on. When the scan signal has a relatively low level, the second transistor and the third transistor may be turned on, and the fifth transistor and the sixth transistor may be turned off.

[0012] In an embodiment, the fourth transistor may be turned on in response to a reference voltage transmitted to the second node through the data line and the second transistor, and the initialization voltage may be higher than the reference voltage.

[0013] In an embodiment, the fourth transistor may be turned off in response to a data voltage transmitted to the second node through the data line and the second transistor.

[0014] In an embodiment, the initialization voltage may be lower than the data voltage.

[0015] In an embodiment, a frame period for a pixel may include an initialization period for initializing the first node and the third node, a data writing and compensation period for providing a data voltage through a data line, and an emission period for emitting light from the light emitting element.

[0016] In an embodiment, during the initialization period, the scan signal may have a first level, the reference voltage may be provided through the data line, the second transistor may transmit the reference voltage transmitted by the data line to the second node in response to the scan signal having the first level, the fourth transistor may transmit the initialization voltage to the first node in response to the reference voltage of the second node, the third transistor may transmit the initialization voltage of the first node to the third node in response to the scan signal having the first level, and the first node and the third node may be initialized based on the initialization voltage.

[0017] In an embodiment, during a data write and compensation period, a scan signal may have a first level, a data voltage may be provided through a data line, a second transistor may transmit the data voltage transmitted by the data line to a second node in response to a scan signal having the first level, a third transistor may be diode-connected to the first transistor in response to a scan signal having the first level, and a voltage obtained by subtracting a threshold voltage of the first transistor from the data voltage may be applied to the first node through the first transistor connected in a diode manner.

[0018] In an embodiment, during the emission period, the scan signal may have a second level different from the first level, the fifth transistor and the sixth transistor may be turned on in response to the scan signal having the second level, the first transistor may generate a driving current based on the voltage of the first node, and the light-emitting element may emit light based on the driving current.

[0019] In an embodiment, the pixel may further include a seventh transistor including a gate receiving a scan signal, a first terminal connected to a line transmitting an anode initialization voltage, and a second terminal connected to an anode of the light emitting element.

[0020] In an embodiment of the present disclosure, a pixel of a display device is provided, the pixel including: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to a third node; a second transistor including a gate receiving a first scan signal, a first terminal connected to a data line, and a second terminal connected to the second node; a third transistor including a gate receiving a second scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving a first scan signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving a second scan signal, a first terminal connected to the third node, and a second terminal; and a light-emitting element including an anode connected to the second terminal of the sixth transistor and a cathode connected to the line transmitting the second power supply voltage.

[0021] In an embodiment, the type of the second transistor may be different from the type of the fifth transistor, and the type of the third transistor may be different from the type of the sixth transistor.

[0022] In an embodiment, the frame period for a pixel may include a source initialization period for initializing the second node, an initialization period for initializing the first node and the third node, a data writing and compensation period for providing a data voltage through a data line, and an emission period for the light emitting element to emit light.

[0023] In an embodiment, in a source initialization period, the first scan signal may have a second level, the second scan signal may have a first level different from the second level, the fifth transistor may transmit the first power supply voltage to the second node in response to the first scan signal having the second level, and the second node may be initialized based on the first power supply voltage.

[0024] According to an embodiment, a display device is provided, the display device comprising: a display panel including a plurality of pixels; a data driver connected to each of the plurality of pixels via a data line; and a scan driver providing a scan signal to each of the plurality of pixels. Each of the plurality of pixels comprises: a capacitor connected between a line transmitting a first power supply voltage and a first node; a first transistor comprising a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor comprising a gate receiving a scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor comprising a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor comprising a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor comprising a gate receiving a scan signal, a first terminal connected to a line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor comprising a gate receiving a scan signal, a first terminal connected to the third node, and a second terminal; and a light-emitting element comprising an anode connected to the second terminal of the sixth transistor and a cathode connected to a line transmitting the second power supply voltage.

[0025] In an embodiment, the type of the second and third transistors may be different from the type of the fifth and sixth transistors.

[0026] As described above, in the pixel of the display device in the embodiment, the gate of the fourth transistor can be connected to the second node. In addition, the fourth transistor can be turned on in response to a reference voltage applied to the second node by the data line and the second transistor, and can be turned off in response to a data voltage applied to the second node by the data line and the second transistor. Therefore, the pixel in the embodiment can be implemented in the absence of a separate signal (e.g., initialization signal) for turning on or off the fourth transistor. In addition, in the pixel of the display device in the embodiment, the type of the second transistor and the third transistor can be different from the type of the fifth transistor and the sixth transistor, and the second transistor, the third transistor, the fifth transistor and the sixth transistor can receive the same scan signal. Therefore, the pixel in the embodiment can be implemented in the absence of a separate signal (e.g., emission signal) for turning on or off the fifth transistor and the sixth transistor. Therefore, the number of signal lines of the display device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a circuit diagram illustrating an embodiment of a pixel.

[0029] Figure 2 is a timing chart for describing an embodiment of the operation of a pixel in the embodiment.

[0030] Figure 3 is a circuit diagram used to describe the operation of a pixel in an initialization period.

[0031] Figure 4 is a circuit diagram used to describe the operation of a pixel during the data writing and compensation cycles.

[0032] Figure 5 is a circuit diagram used to describe the operation of a pixel during the emission cycle.

[0033] Figure 6 is a circuit diagram illustrating an embodiment of a pixel.

[0034] Figure 7 is a circuit diagram showing an embodiment of a pixel in the embodiment.

[0035] Figure 8 is a timing diagram for describing an embodiment of the operation of a pixel.

[0036] Figure 9 is a circuit diagram illustrating an embodiment of a pixel.

[0037] Figure 10 is a circuit diagram illustrating an embodiment of a pixel.

[0038] Figure 11 is a timing diagram for describing an embodiment of the operation of a pixel.

[0039] Figure 12 is a block diagram illustrating an embodiment of a display device.

[0040] Figure 13 is a timing chart for describing an embodiment of the operation of the display device.

[0041] Figure 14 is a block diagram illustrating an embodiment of an electronic device including a display device. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings.

[0043] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0044] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, the "first element," "first component," "first region," "first layer," or "first section" discussed below may be referred to as the "second element," "second component," "second region," "second layer," or "second section" without departing from the spirit and scope of the present disclosure.

[0045] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "one (kind / one)" and "the (the)" are also intended to include plural forms, including "at least one (kind / one)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more relevant listed items. It will also be understood that the terms "comprises and / or comprising" or "includes and / or including" when used in this specification specify the presence of the features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their combinations.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device is turned over in a drawing, an element described as being on the "lower" side of the other elements will subsequently be oriented to be on the "upper" side of the other elements. Thus, depending on the specific orientation of the drawing, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in a drawing, an element described as being "below" or "beneath" the other elements will subsequently be oriented to be "above" the other elements. Thus, the exemplary terms "below" or "below" can cover both "upper" and "lower" orientations.

[0047] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined otherwise herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0049] Figure 1 is a circuit diagram illustrating an embodiment of a pixel.

[0050] Reference Figure 1 The pixel 100 in the embodiment may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a light emitting element EL.

[0051] The capacitor CST may be connected between a line for transmitting a first power supply voltage ELVDD (e.g., a relatively high power supply voltage) and a first node N1. The first node N1 may be a gate node connected to the gate of the first transistor T1. In some embodiments, the capacitor CST may also be referred to as a storage capacitor for storing a data voltage. In some embodiments, the capacitor CST may include a first electrode connected to the line for transmitting the first power supply voltage ELVDD and a second electrode connected to the first node N1.

[0052] The first transistor T1 can generate a driving current based on the voltage of the first node N1. In some embodiments, the first transistor T1 can also be referred to as a driving transistor for driving the light-emitting element EL. In addition, in some embodiments, the first transistor T1 may include a gate connected to the first node N1, a first terminal (e.g., a source) connected to the second node N2, and a second terminal (e.g., a drain) connected to the third node N3.

[0053] The second transistor T2 can connect the data line DL to the second node N2 in response to the scan signal GW. The second node N2 can be a source node connected to the source of the first transistor T1. In some embodiments, the second transistor T2 can also be referred to as a scan transistor or a switching transistor, and is configured to transmit the voltage of the data line DL to the second node N2. In addition, in some embodiments, the second transistor T2 can include a gate for receiving the scan signal GW, a first terminal connected to the data line DL, and a second terminal connected to the second node N2.

[0054] The third transistor T3 can connect the first node N1 and the third node N3 to each other in response to the scan signal GW. The third node N3 can be a drain node connected to the drain of the first transistor T1. Through the third transistor T3, the gate node and the drain node are connected to each other, and thus the first transistor T1 can be connected in a diode manner. In some embodiments, the third transistor T3 can also be referred to as a compensation transistor for connecting the first transistor T1 in a diode manner. In addition, in some embodiments, the third transistor T3 may include a gate for receiving the scan signal GW, a first terminal connected to the third node N3, and a second terminal connected to the first node N1.

[0055] The fourth transistor T4 can transmit the initialization voltage VINT to the first node N1 in response to the voltage of the second node N2. In some embodiments, the fourth transistor T4 may also be referred to as an initialization transistor for providing the initialization voltage VINT to the first node N1 (or gate node). In addition, in some embodiments, the fourth transistor T4 may include a gate connected to the second node N2, a first terminal connected to a line for transmitting the initialization voltage VINT, and a second terminal connected to the first node N1.

[0056] The fifth transistor T5 can connect the line for transmitting the first power supply voltage ELVDD and the second node N2 to each other in response to the scan signal GW. In some embodiments, the fifth transistor T5 can also be referred to as a first emission transistor, and is used to form a path for providing a drive current to the light-emitting element EL. In addition, in some embodiments, the fifth transistor T5 may include a gate for receiving the scan signal GW, a first terminal connected to the line for transmitting the first power supply voltage ELVDD, and a second terminal connected to the second node N2.

[0057] The sixth transistor T6 can connect the third node N3 and the anode of the light-emitting element EL to each other in response to the scan signal GW. In some embodiments, the sixth transistor T6 can also be referred to as a second emission transistor, which is used to form a path for providing a drive current to the light-emitting element EL. In some embodiments, the sixth transistor T6 may include a gate for receiving the scan signal GW, a first terminal connected to the third node N3, and a second terminal connected to the anode of the light-emitting element EL.

[0058] The light emitting element EL can emit light in response to the driving current generated by the first transistor T1. In some embodiments, the light emitting element EL can be an organic light emitting diode ("OLED"), but is not limited thereto. In an embodiment, for example, the light emitting element EL can be a nano light emitting diode ("NED"), a quantum dot ("QD") light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element. In addition, in some embodiments, the light emitting element EL can include an anode connected to the second terminal of the sixth transistor T6 and a cathode connected to a line for transmitting a second power supply voltage ELVSS (e.g., a relatively low power supply voltage).

[0059] In the pixel 100 of the display device in the embodiment, the type of the second transistor T2 and the third transistor T3 may be different from the type of the fifth transistor T5 and the sixth transistor T6. Figure 1 As shown in , the second transistor T2 and the third transistor T3 can be N-type transistors, for example, N-type metal oxide semiconductor ("NMOS") transistors, and the fifth transistor T5 and the sixth transistor T6 can be P-type transistors, for example, P-type metal oxide semiconductor ("PMOS") transistors. In addition, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 can receive the same scan signal GW. In this case, when the scan signal GW has a relatively high level (or high level), the second transistor T2 and the third transistor T3 can be turned on, and the fifth transistor T5 and the sixth transistor T6 can be turned off. In addition, when the scan signal GW has a relatively low level (or low level), the second transistor T2 and the third transistor T3 can be turned off, and the fifth transistor T5 and the sixth transistor T6 can be turned on.

[0060] In addition, in the pixel 100 of the display device in the embodiment, the gate of the fourth transistor T4 can be connected to the second node N2. Therefore, the fourth transistor T4 may not receive a separate signal (e.g., an initialization signal) and may be turned on or off in response to the voltage of the second node N2. In some embodiments, the fourth transistor T4 may be turned on in response to a reference voltage applied to the second node N2 through the data line DL and the second transistor T2, and may be turned off in response to a data voltage applied to the second node N2 through the data line DL and the second transistor T2. Therefore, the pixel 100 in the embodiment can be implemented without a separate signal (e.g., an initialization signal) for turning on or off the fourth transistor T4, and the number of signal lines of the display device including the pixel 100 can be reduced.

[0061] In addition, as described above, the types of the second transistor T2 and the third transistor T3 can be different from the types of the fifth transistor T5 and the sixth transistor T6, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 can receive the same scan signal GW. Therefore, the pixel 100 in the embodiment can be implemented without a separate signal (e.g., an emission signal) for turning on or off the fifth transistor T5 and the sixth transistor T6, and the number of signal lines of the display device including the pixel 100 can be further reduced.

[0062] In the following, reference will be made to Figures 1 to 5 The operation of the pixel 100 in the embodiment is described.

[0063] Figure 2 is a timing diagram for describing an embodiment of the operation of a pixel in the embodiment, Figure 3 is a circuit diagram for describing the operation of a pixel during the initialization period, Figure 4 is a circuit diagram for describing the operation of a pixel during data writing and compensation cycles, and Figure 5 is a circuit diagram used to describe the operation of a pixel during the emission cycle.

[0064] Reference Figure 1 and Figure 2 , the frame period FP for the pixel 100 may include an initialization period INIP in which the first node N1 and the third node N3 are initialized, a data writing and compensation period DWCP in which the data voltage VDAT is supplied through the data line DL, and an emission period EMP in which the light emitting element EL emits light.

[0065] Reference Figure 2 and Figure 3 In the initialization period INIP, the scan signal GW may have a first level, and the reference voltage VREF may be provided through the data line DL. In some embodiments, as shown in FIG. Figure 2As shown in , the first level may be a relatively high level. Figure 3 As shown in , the fifth transistor T5 and the sixth transistor T6 can be turned off in response to the scan signal GW having a first level. The second transistor T2 can be turned on in response to the scan signal GW having a first level, and the reference voltage VREF of the data line DL can be transmitted to the second node N2. The fourth transistor T4 can be turned on in response to the reference voltage VREF transmitted to the second node N2 through the data line DL and the second transistor T2. In some embodiments, in order to turn on the fourth transistor T4, the reference voltage VREF applied to the gate of the fourth transistor T4 can be lower than the initialization voltage VINT applied to one terminal (e.g., source) of the fourth transistor T4. That is, the initialization voltage VINT and the reference voltage VREF can be set so that the initialization voltage VINT is higher than the reference voltage VREF. In an embodiment, for example, the initialization voltage VINT can be approximately 3 volts (V), and the reference voltage VREF can be approximately 0V. However, the initialization voltage VINT and the reference voltage VREF are not limited thereto.

[0066] In addition, the fourth transistor T4, which is turned on in response to the reference voltage VREF at the second node N2, can transmit the initialization voltage VINT to the first node N1. Since the initialization voltage VINT applied to the first node N1 is higher than the reference voltage VREF applied to the second node N2, the first transistor T1 can be turned off. In addition, the third transistor T3 can be turned on in response to the scan signal GW having a first level and can transmit the initialization voltage VINT at the first node N1 to the third node N3. Therefore, the first node N1 and the third node N3 can be initialized based on the initialization voltage VINT. Since the first node N1 (e.g., the gate node) is initialized to the initialization voltage VINT, the compensation operation in the diode connection method can be performed normally during the data write and compensation period DWCP. In addition, since the third node N3 (e.g., the drain node) is initialized to the initialization voltage VINT, the residual charge remaining at the drain node can be discharged or removed.

[0067] Reference Figure 2 and Figure 4 In the data writing and compensation period DWCP, the scan signal GW may have a first level and the data voltage VDAT may be provided through the data line DL. Figure 4As shown in FIG, the fifth transistor T5 and the sixth transistor T6 can be turned off in response to the scan signal GW having a first level. The second transistor T2 can be turned on in response to the scan signal GW having a first level and can transmit the data voltage VDAT of the data line DL to the second node N2. The fourth transistor T4 can be turned off in response to the data voltage VDAT transmitted to the second node N2 through the data line DL and the second transistor T2. In some embodiments, in order to turn off the fourth transistor T4, the data voltage VDAT applied to the gate of the fourth transistor T4 can be higher than the initialization voltage VINT applied to one terminal (e.g., the source) of the fourth transistor T4. That is, the range of the initialization voltage VINT and the data voltage VDAT can be set so that the initialization voltage VINT is lower than the range of the data voltage VDAT, or the initialization voltage VINT is lower than the minimum data voltage (e.g., the data voltage VDAT corresponding to the highest grayscale). In an embodiment, for example, the initialization voltage VINT can be about 3V, and the data voltage VDAT can range from about 5V to about 7V. However, the initialization voltage VINT and the data voltage VDAT are not limited thereto.

[0068] In addition, the third transistor T3 can be turned on in response to the scan signal GW having a first level and can be diode-connected to the first transistor T1. Since the data voltage VDAT of the second node N2 is applied to the first node N1 through the diode-connected first transistor T1, a voltage VDAT-VTH obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the data voltage VDAT can be applied to the first node N1. This operation can also be referred to as a compensation operation in the diode connection method. In addition, the capacitor CST can store a voltage VDAT-VTH obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the data voltage VDAT at the first node N1.

[0069] Reference Figure 2 and Figure 5 In the emission period EMP, the scanning signal GW may have a second level. Figure 2 As shown in , the second level may be a relatively low level. Figure 5As shown in FIG, the second transistor T2 and the third transistor T3 can be turned off in response to the scan signal GW having a second level. In addition, the fourth transistor T4 can be kept in an off state based on the first power supply voltage ELVDD transmitted to the second node N2 by the fifth transistor T5. The first transistor T1 can generate a drive current IDR based on the voltage of the first node N1 or the voltage VDAT-VTH obtained by subtracting the threshold voltage (VTH) from the data voltage VDAT. The fifth transistor T5 can be turned on in response to the scan signal GW having a second level and can connect the line for transmitting the first power supply voltage ELVDD to the second node N2. The sixth transistor T6 can be turned on in response to the scan signal GW having a second level and can connect the third node N3 to the anode of the light-emitting element EL. Therefore, the fifth transistor T5 and the sixth transistor T6 can form a path for the drive current IDR from the line for transmitting the first power supply voltage ELVDD to the line for transmitting the second power supply voltage ELVSS. The light-emitting element EL can emit light based on the drive current IDR generated by the first transistor T1.

[0070] As described above, in the pixel 100 of the display device in the embodiment, since the fourth transistor T4 is turned on or off based on the reference voltage VREF and the data voltage VDAT provided by the data line DL, the display device including the pixel 100 can be implemented without a separate signal (e.g., an initialization signal). In addition, in the pixel 100 of the display device in the embodiment, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 can be turned on or off based on the same scan signal GW. Therefore, only one scan signal GW can be used to drive the pixel 100, and the number of signal lines of the display device including the pixel 100 can be reduced.

[0071] Figure 6 is a circuit diagram illustrating an embodiment of a pixel.

[0072] Reference Figure 6 In the embodiment, the pixel 200 may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a light emitting element EL. In addition to the seventh transistor T7, the pixel 200 may also include Figure 6 The pixel 200 may have Figure 1 The configuration of the pixel 100 is basically the same configuration.

[0073] The seventh transistor T7 can transmit the anode initialization voltage AVINT to the anode of the light emitting element EL in response to the scan signal GW. Figure 2In the initialization period INIP and the data writing and compensation period DWCP shown in FIG, the seventh transistor T7 can provide the anode initialization voltage AVINT to the anode of the light emitting element EL, and can initialize the anode of the light emitting element EL based on the anode initialization voltage AVINT. In some embodiments, the seventh transistor T7 may include a gate for receiving the scan signal GW, a first terminal connected to a line for transmitting the anode initialization voltage AVINT, and a second terminal connected to the anode of the light emitting element EL.

[0074] The type of the seventh transistor T7 can be substantially the same as the type of the second transistor T2 and the third transistor T3, so that when the second transistor T2 and the third transistor T3 are turned on, the seventh transistor T7 is turned on. In some embodiments, the seventh transistor T7 can be an N-type transistor, for example, an NMOS transistor. In other embodiments, as described below with reference to Figure 9 As described, the seventh transistor T7 may be a P-type transistor, for example, a PMOS transistor.

[0075] In addition, in some embodiments, the anode initialization voltage AVINT may be substantially the same as the initialization voltage VINT, and the line for transmitting the anode initialization voltage AVINT and the line for transmitting the initialization voltage VINT may be the same line. In other embodiments, the anode initialization voltage AVINT may be different from the initialization voltage VINT, and the line for transmitting the anode initialization voltage AVINT may be different from the line for transmitting the initialization voltage VINT.

[0076] Figure 7 is a circuit diagram showing an embodiment of a pixel in the embodiment, and Figure 8 is a timing diagram for describing an embodiment of the operation of a pixel.

[0077] Reference Figure 7 , the pixel 300 in the embodiment may include a capacitor CST, a first transistor T1, a second transistor T2', a third transistor T3', a fourth transistor T4, a fifth transistor T5', a sixth transistor T6' and a light emitting element EL. In addition to the second transistor T2' and the third transistor T3' being PMOS transistors, and the fifth transistor T5' and the sixth transistor T6' being NMOS transistors, Figure 7 The pixel 300 may have Figure 1 The configuration of the pixel 100 is basically the same configuration.

[0078] exist Figure 7In the pixel 300, the second transistor T2', the third transistor T3', the fifth transistor T5', and the sixth transistor T6' can receive the same scan signal GW'. When the scan signal GW' has a relatively high level, the second transistor T2' and the third transistor T3' can be turned off, and the fifth transistor T5' and the sixth transistor T6' can be turned on. In addition, when the scan signal GW' has a relatively low level, the second transistor T2' and the third transistor T3' can be turned on, and the fifth transistor T5' and the sixth transistor T6' can be turned off. In addition, as Figure 8 As shown in , the scan signal GW' may have a relatively low level during the initialization period INIP and the data writing and compensation period DWCP, and may have a relatively high level during the emission period EMP. Therefore, during the initialization period INIP and the data writing and compensation period DWCP, the second transistor T2' and the third transistor T3' may be turned on, and the fifth transistor T5' and the sixth transistor T6' may be turned off. In addition, during the emission period EMP, the second transistor T2' and the third transistor T3' may be turned off, and the fifth transistor T5' and the sixth transistor T6' may be turned on.

[0079] Figure 9 is a circuit diagram illustrating an embodiment of a pixel.

[0080] Reference Figure 9 In the embodiment, the pixel 400 may include a capacitor CST, a first transistor T1, a second transistor T2', a third transistor T3', a fourth transistor T4, a fifth transistor T5', a sixth transistor T6', a seventh transistor T7' and a light emitting element EL. In addition to the seventh transistor T7', the pixel 400 may also include Figure 9 The pixel 400 may have Figure 7 The configuration of the pixel 300 is basically the same configuration.

[0081] The seventh transistor T7' may be of substantially the same type as the second transistor T2' and the third transistor T3', such that when the second transistor T2' and the third transistor T3' are turned on, the seventh transistor T7' is turned on. Figure 9 As shown in FIG, the seventh transistor T7 ′ may be a P-type transistor, for example, a PMOS transistor.

[0082] Figure 10 is a circuit diagram showing an embodiment of a pixel, and Figure 11 is a timing diagram for describing an embodiment of the operation of a pixel.

[0083] Reference Figure 10The pixel 500 in the embodiment may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a light emitting element EL. In addition to the gate of the second transistor T2 and the gate of the fifth transistor T5 receiving the first scan signal GWa, and the gate of the third transistor T3 and the gate of the sixth transistor T6 receiving the second scan signal GWb, Figure 10 The pixel 500 may have Figure 1 The configuration of the pixel 100 is basically the same configuration.

[0084] In addition, refer to Figure 10 and Figure 11 , the frame period FP of the pixel 500 may include a source initialization period SINIP in which the second node N2 is initialized, an initialization period INIP, a data writing and compensation period DWCP, and an emission period EMP. In addition to the source initialization period SINIP, the frame period FP may also include: Figure 11 The timing diagram can be compared with Figure 2 The timing diagrams are basically the same.

[0085] During the source initialization period SINIP, the first scan signal GWa may have a second level (e.g., a relatively low level), and the second scan signal GWb may have a first level (e.g., a relatively high level). The sixth transistor T6 may be turned off in response to the second scan signal GWb having the first level. Therefore, a path for the driving current from the line for transmitting the first power supply voltage ELVDD to the line for transmitting the second power supply voltage ELVSS may not be formed, and the light-emitting element EL may not emit light. In addition, in response to the first scan signal GWa having the second level, the second transistor T2 may be turned off, and the fifth transistor T5 may be turned on. The turned-on fifth transistor T5 may transmit the first power supply voltage ELVDD to the second node N2. Therefore, the second node N2 may be initialized based on the first power supply voltage ELVDD. Since the second node N2 (e.g., the source node) is initialized to the first power supply voltage ELVDD, the residual charge retained at the source node may be discharged or removed.

[0086] In the initialization period INIP and the data writing and compensation period DWCP, both the first scan signal GWo and the second scan signal GWb may have the first level. In the emission period EMP, both the first scan signal GWo and the second scan signal GWb may have the second level. Therefore, in the initialization period INIP, the data writing and compensation period DWCP, and the emission period EMP, the operation of the pixel 500 may be the same as Figure 1 The operation of the pixel 100 is basically the same.

[0087] although Figure 10 The embodiment in which the second transistor T2 and the third transistor T3 are NMOS transistors and the fifth transistor T5 and the sixth transistor T6 are PMOS transistors is shown. However, in other embodiments, the second transistor T2 and the third transistor T3 can be implemented as PMOS transistors, and the fifth transistor T5 and the sixth transistor T6 can be implemented as NMOS transistors. In addition, in other embodiments, the pixel 500 may further include a seventh transistor for transmitting an anode initialization voltage to the anode of the light-emitting element EL in response to the first scan signal GWa or the second scan signal GWb.

[0088] Figure 12 is a block diagram showing an embodiment of a display device, and Figure 13 is a timing chart for describing an embodiment of the operation of the display device.

[0089] Reference Figure 12 The display device 600 in the embodiment may include: a display panel 610, including a plurality of pixels PX; a data driver 620, connected to each of the plurality of pixels PX through a data line; a scan driver 630, providing scan signals GW1, GW2, GW3, ...; and a controller 650, controlling the data driver 620 and the scan driver 630.

[0090] The display panel 610 may include a plurality of pixels PX. According to an embodiment, each pixel PX of the display panel 610 may be Figure 1 100 pixels, Figure 6 200 pixels, Figure 7 300 pixels, Figure 9 400 pixels or Figure 10 Pixel 500, etc. In each pixel PX, the fourth transistor can be turned on based on the reference voltage VREF provided from the data driver 620 through the data line, and can be turned off based on the data voltage VDAT provided from the data driver 620 through the data line. Therefore, the display device 600 can be implemented without a separate signal (e.g., initialization signal) for turning on or off the fourth transistor. In addition, in each pixel PX, the second transistor, the third transistor, the fifth transistor, and the sixth transistor can be turned on or off based on the same scan signal GW1, GW2, GW3, .... Therefore, the display device 600 can be implemented without a separate signal (e.g., emission signal) for turning on or off the fifth transistor and the sixth transistor. Therefore, each pixel PX can be driven using only one scan signal GW1, GW2, GW3, ..., and the number of signal lines of the display device 600 can be reduced.

[0091] The data driver 620 can generate a reference voltage VREF and a data voltage VDAT based on the output image data ODAT and the data control signal DCTRL received from the controller 650, and can provide the reference voltage VREF and the data voltage VDAT to a plurality of pixels PX. In some embodiments, the data control signal DCTRL may include but is not limited to an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 620 can alternately provide the reference voltage VREF and the data voltage VDAT to each data line. In addition, in each horizontal time, the data driver 620 can sequentially output the reference voltage VREF and the data voltage VDAT to each data line. In an embodiment, as Figure 13 As shown in , for example, in a first horizontal time 1H allocated to a first pixel row, the data driver 620 may first output a reference voltage VREF to each data line DL, and then may output a data voltage VDAT for each pixel PX in the first pixel row to the data line DL. Furthermore, in a second horizontal time allocated to a second pixel row, the data driver 620 may sequentially output a reference voltage VREF and a data voltage VDAT for each pixel PX in the second pixel row to each data line DL. Furthermore, in a third horizontal time allocated to a third pixel row, the data driver 620 may sequentially output a reference voltage VREF and a data voltage VDAT for each pixel PX in the third pixel row to each data line DL. Furthermore, in some embodiments, the data driver 620 and the controller 650 may be implemented as a single integrated circuit ("IC"), which may also be referred to as a timing controller embedded data driver ("TED"). In other embodiments, the data driver 620 and the controller 650 may be implemented as separate ICs.

[0092] The scan driver 630 may provide scan signals GW1, GW2, GW3, ... to the plurality of pixels PX based on the scan control signal SCTRL received from the controller 650. The scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. Figure 13As shown in , the scan driver 630 may sequentially provide scan signals GW1, GW2, GW3, ... to a plurality of pixels PX on a row-by-row basis. In an embodiment, for example, the scan driver 630 may provide a first scan signal GW1 having a first level (e.g., a relatively high level) to a first pixel row, and may then provide a second scan signal GW2 having a first level to a second pixel row. Thereafter, the scan driver 630 may provide a third scan signal GW3 having a first level to a third pixel row. In some embodiments, the scan driver 630 may be integrated or formed in a peripheral area of ​​the display panel 610. In other embodiments, the scan driver 630 may be integrated or formed in a display area of ​​the display panel 610. In other embodiments, the scan driver 630 may be implemented as one or more ICs.

[0093] The controller 650 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (“GPU”), an application processor (“AP”), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal. The controller 650 may generate output image data ODAT, a data control signal DCTRL, and a scan control signal SCTRL based on the input image data IDAT and the control signal CTRL. The controller 650 may control the data driver 620 by providing the output image data ODAT and the data control signal DCTRL to the data driver 620, and may control the scan driver 630 by providing the scan control signal SCTRL to the scan driver 630.

[0094] Figure 14 is a block diagram illustrating an embodiment of an electronic device including a display device.

[0095] Reference Figure 14 , the electronic device 1000 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output ("I / O") device 1140, a power supply 1150, and a display device 1160. The electronic device 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electrical devices, and the like.

[0096] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor ("AP"), a microprocessor, a central processing unit ("CPU"), or the like. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, or the like. In addition, in some embodiments, the processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus.

[0097] The memory device 1120 may store data used for the operation of the electronic device 1000. In embodiments, for example, the memory device 1120 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, and a ferroelectric random access memory (“FRAM”) device) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, and a mobile dynamic random access memory (“mobile DRAM”) device).

[0098] The storage device 1130 may be a solid-state drive ("SSD") device, a hard disk drive ("HDD") device, a compact disc read-only memory ("CD-ROM") device, etc. The I / O device 1140 may be an input device (such as a keyboard, a keypad, a mouse, a touch screen, etc.) and an output device (such as a printer, a speaker, etc.). The power supply 1150 may supply power for the operation of the electronic device 1000. The display device 1160 may be coupled to other components via a bus or other communication link.

[0099] In the display device 1160, the fourth transistor of each pixel can be turned on or off in response to a reference voltage and a data voltage provided by a data line rather than a separate signal (e.g., an initialization signal). In addition, the second transistor, the third transistor, the fifth transistor, and the sixth transistor of each pixel can be turned on or off based on the same scan signal. Therefore, only one signal (or scan signal) can be used to drive each pixel, and the number of signal lines of the display device 1160 can be reduced.

[0100] The present invention can be applied to any display device 1160 and any electronic device 1000 including the display device 1160. In embodiments, the present invention can be applied to, for example, smart phones, wearable electronic devices, mobile phones, televisions ("TVs") (e.g., digital TVs and three-dimensional ("3D") TVs), personal computers ("PCs") (e.g., tablet computers or laptop computers), home appliances, personal digital assistants ("PDAs"), portable multimedia players ("PMPs"), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0101] The foregoing is illustrative of embodiments and should not be construed as limiting the embodiments. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting the disclosed illustrative embodiments, and that modifications of the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel of a display device, characterized in that: The pixels include: a capacitor connected between a line transmitting a first power supply voltage and the first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving the scan signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal; and The light emitting element includes an anode connected to the second terminal of the sixth transistor and a cathode connected to a line transmitting a second power supply voltage.

2. The pixel according to claim 1, wherein The second and third transistors are of a different type than the fifth and sixth transistors.

3. The pixel according to claim 1, wherein The second transistor and the third transistor are N-type metal oxide semiconductor transistors, and when the scan signal has a high level, the second transistor and the third transistor are turned on, and The fifth transistor and the sixth transistor are P-type metal oxide semiconductor transistors, and when the scan signal has a high level, the fifth transistor and the sixth transistor are turned off.

4. The pixel according to claim 1, wherein The second transistor and the third transistor are P-type metal oxide semiconductor transistors, and when the scan signal has a high level, the second transistor and the third transistor are turned off, and The fifth transistor and the sixth transistor are N-type metal oxide semiconductor transistors, and when the scan signal has a high level, the fifth transistor and the sixth transistor are turned on.

5. The pixel according to claim 1, wherein A reference voltage lower than the initialization voltage is transmitted to the second node through the data line and the second transistor to turn on the fourth transistor.

6. The pixel according to claim 1, wherein A data voltage is transmitted to the second node through the data line and the second transistor to turn off the fourth transistor.

7. A pixel of a display device, characterized in that: The pixels include: a capacitor connected between a line transmitting a first power supply voltage and the first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving a first scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving a second scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving the first scan signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving the second scan signal, a first terminal connected to the third node, and a second terminal; and The light emitting element includes an anode connected to the second terminal of the sixth transistor and a cathode connected to a line transmitting a second power supply voltage.

8. A display device, characterized in that: The display device includes: A display panel comprising a plurality of pixels, each of the plurality of pixels comprising: a capacitor connected between a line transmitting a first power supply voltage and the first node; a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a gate receiving a scan signal, a first terminal connected to the data line, and a second terminal connected to the second node; a third transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node; a fourth transistor including a gate connected to the second node, a first terminal connected to a line transmitting an initialization voltage, and a second terminal connected to the first node; a fifth transistor including a gate receiving the scan signal, a first terminal connected to the line transmitting the first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate receiving the scan signal, a first terminal connected to the third node, and a second terminal; and a light emitting element including an anode connected to the second terminal of the sixth transistor and a cathode connected to a line transmitting a second power supply voltage; a data driver connected to each of the plurality of pixels through the data lines; and The scan driver provides the scan signal to each of the plurality of pixels.

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