Driving chip of liquid crystal display device

Abstract

The utility model discloses a driving chip of a liquid crystal display device, which comprises a first pad area used for arranging an input pad; the second pad area is used for arranging an output pad; the first cascade pad area is used for arranging cascade pads; the second cascade pad area is used for arranging cascade pads; an expansion zone; the expansion region penetrates through the whole chip and is arranged between the first pad region and the second pad region; the first cascade pad region and the second cascade pad region are arranged at the two ends of the first pad region or / and the second pad region, and cascade pads arranged in the first cascade pad region and the second cascade pad region are aligned with the corresponding first pad region or / and the second pad region. According to the driving chip, the extension area, the first pad area and the second pad area which penetrate through the chip are arranged on the driving chip, and the cascade pads at the two ends are aligned with the first pad area or the second pad area, so that the wiring space is greatly increased, the wiring RC Loading is prevented from being influenced, and the signal transmission quality between the driving chips is ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of driver chips of liquid crystal displays, and in particular to a driver chip of a liquid crystal display device. Background Art

[0002] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is one of the most widely used flat panel displays. A TFT-LCD generally comprises a liquid crystal display panel, a gate driver circuit, and a data driver circuit. The LCD panel consists of a color filter substrate and a TFT array substrate, both of which are arranged in a cell-like configuration, with a liquid crystal layer sandwiched between them. The gate driver circuit and the data driver circuit are each connected to the TFT switching elements on the array substrate.

[0003] When the array substrate is working, the data line is used to transmit the video data signal in the data driver chip (IC) to the drain electrode of the TFT switching element, thereby controlling the voltage of the liquid crystal pixel electrode; the scan line is used to transmit the scan drive signal in the scan driver chip to the gate of the TFT switching element, thereby controlling the closing and opening of the TFT switching element.

[0004] When a liquid crystal display device is operating, for one frame of an image, the data driver chip transmits the video data signal to the drain electrode through the data line. The scan driver chip is then turned on in sequence according to the control of the gate shift signal (Clock Plus Vertical, abbreviated as CPV), inputting the scan drive signal to the scan lines row by row, causing the scan lines to turn on row by row. The data driver chip then stores the corresponding data voltage on the pixel electrode, forming grayscale voltages of various levels, thereby realizing the display of each frame of the image.

[0005] For some medium and large-sized TFT-LCDs, multiple chip ICs are usually used. Multiple chips are cascaded through wiring on the display panel. However, the unreasonable position of the cascade pads results in limited wiring space, increased RC loading of the wiring, affected signal transmission between chips, and thus reduced display quality. Utility Model Content

[0006] The pad layout of the existing driver chip of the thin film transistor liquid crystal display device is unreasonable, resulting in limited wiring space when the chips are cascaded. This not only increases the RC loading of the wiring, but also affects the signal transmission quality between chips.

[0007] To address the above issues, a driver chip for a liquid crystal display device is proposed. By providing an expansion area, a first pad area, and a second pad area that penetrate the chip on the driver chip, and aligning the cascade pads at both ends with the first pad area or the second pad area, the wiring space is greatly increased, the RC loading of the wiring is avoided, and the signal transmission quality between the driver chips is guaranteed.

[0008] A driver chip for a liquid crystal display device, comprising:

[0009] The first pad area is used to arrange the input pad;

[0010] The second pad area is used to arrange the output pad;

[0011] The first cascade pad area is used to arrange the cascade pad;

[0012] The second cascade pad area is used for arranging cascade pads;

[0013] expansion area;

[0014] The expansion area runs through the entire chip and is arranged between the first pad area and the second pad area;

[0015] The first cascade pad region and the second cascade pad region are arranged at both ends of the first pad region and / or the second pad region.

[0016] The cascade pads arranged in the first cascade pad region and the second cascade pad region are aligned with the corresponding first pad region and / or the second pad region.

[0017] In conjunction with the driver chip of the liquid crystal display device described in the present invention, in a first possible implementation manner, the cascade pad includes:

[0018] Multiple first cascade pads;

[0019] Multiple second cascade pads;

[0020] The plurality of first cascade pads and the plurality of second cascade pads are respectively arranged in the first cascade pad region and the second cascade pad region, and are respectively aligned with two ends of the first pad region.

[0021] In conjunction with the driver chip of the liquid crystal display device described in the present invention, in a second possible implementation, the cascade pad includes:

[0022] Multiple first cascade pads;

[0023] Multiple second cascade pads;

[0024] The plurality of first cascade pads and the plurality of second cascade pads are respectively arranged in the first cascade pad region and the second cascade pad region, and are respectively aligned with two ends of the second pad region.

[0025] In conjunction with the driver chip of the liquid crystal display device described in the present invention, in a third possible implementation, the cascade pad includes:

[0026] Multiple first cascade pads;

[0027] The plurality of first cascade pads include:

[0028] A first order cascade pad and a second order cascade pad;

[0029] The number of the first order of cascaded pads is greater than the number of the second order of cascaded pads;

[0030] A first number of cascade pads are aligned with the first pad region;

[0031] A second number of cascade pads are aligned with the second pad region.

[0032] In conjunction with the driver chip of the liquid crystal display device of the present invention, in a fourth possible implementation, the cascade pad includes:

[0033] Multiple first cascade pads;

[0034] The plurality of first cascade pads include:

[0035] A first order cascade pad and a second order cascade pad;

[0036] The number of the first order of cascaded pads is greater than the number of the second order of cascaded pads;

[0037] A first number of cascade pads are aligned with the second pad region;

[0038] A second number of cascade pads are aligned with the first pad region.

[0039] In conjunction with the driver chip of the liquid crystal display device of the present invention, in a fifth possible implementation, the cascade pad includes:

[0040] Multiple second cascade pads;

[0041] The plurality of second cascade pads include:

[0042] The third order cascade pad and the fourth order cascade pad;

[0043] The number of the third order of cascade pads is greater than the number of the fourth order of cascade pads;

[0044] A third number of cascade pads are aligned with the first pad region;

[0045] The fourth number of cascade pads is aligned with the second pad region.

[0046] In conjunction with the driver chip of the liquid crystal display device of the present invention, in a sixth possible implementation, the cascade pad includes:

[0047] Multiple second cascade pads;

[0048] The plurality of second cascade pads include:

[0049] The third order cascade pad and the fourth order cascade pad;

[0050] The number of the third order of cascade pads is greater than the number of the fourth order of cascade pads;

[0051] A third number of cascade pads are aligned with the second pad region;

[0052] The fourth number of cascade pads is aligned with the first pad region.

[0053] The driver chip for the liquid crystal display device according to the present invention is implemented by providing an expansion area, a first pad area, and a second pad area that penetrate the chip on the driver chip. The cascade pads at both ends are aligned with the first pad area or the second pad area, thereby greatly increasing wiring space, avoiding the impact on wiring RC loading, and ensuring the quality of signal transmission between the driver chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 This is a schematic diagram of the pad layout of the driver chip of Example 1 of the present utility model;

[0056] Figure 2 This is a schematic diagram of the pad layout of the driver chip of Example 3 of the present utility model;

[0057] Figure 3 This is a schematic diagram of the pad layout of the driver chip of Example 4 of the present utility model.

[0058] Components and their serial numbers:

[0059] 100——first pad area, 200——second pad area, 300——first cascade pad area, 400——second cascade pad area, 500——expansion area. DETAILED DESCRIPTION

[0060] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0062] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0063] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0065] The pad layout of the existing driver chip of the thin film transistor liquid crystal display device is unreasonable, resulting in limited wiring space when the chips are cascaded. This not only increases the RC loading of the wiring, but also affects the signal transmission quality between chips.

[0066] To address the above problems, a driver chip for a liquid crystal display device is proposed.

[0067] A driver chip for a liquid crystal display device, such as Figure 1 , Figure 1 Schematic diagram of the pad layout of the driver chip according to Example 1 of the present invention; it includes a first pad area 100, a second pad area 200, a first cascade pad area 300, a second cascade pad area 400, and an expansion area 500. The first pad area 100 is used to arrange input pads; the second pad area 200 is used to arrange output pads; the first cascade pad area 300 is used to arrange cascade pads; the second cascade pad area 400 is used to arrange cascade pads; the expansion area 500 runs through the entire chip and is arranged between the first pad area 100 and the second pad area 200 for wiring input pads or output pads; the first cascade pad area 300 and the second cascade pad area 400 are arranged at both ends of the first pad area 100 and / or the second pad area 200, and the cascade pads arranged in the first cascade pad area 300 and the second cascade pad area 400 are aligned with the corresponding first pad area 100 and / or the second pad area 200. By providing an extended area 500 that penetrates the chip, a first pad area 100, and a second pad area 200 on the driver chip, and aligning the cascade pads at both ends with the first pad area 100 or the second pad area 200, wiring space is greatly increased, RC loading of the wiring is avoided, and signal transmission quality between the driver chips is guaranteed.

[0068] Specifically, the cascade pads include multiple first cascade pads and multiple second cascade pads. The multiple first cascade pads and the multiple second cascade pads are respectively arranged in the first cascade pad region 300 and the second cascade pad region 400 and are aligned with both ends of the first pad region 100 .

[0069] The first cascade pad is used to cascade with the chip on one side, and the second cascade pad is used to cascade with the chip on the other side.

[0070] In this embodiment, all first cascade pads are aligned with the left end of the upper first pad region 100 , and all second cascade pads are aligned with the right end of the upper first pad region 100 .

[0071] In this embodiment, the cascade pads include multiple first cascade pads and multiple second cascade pads. The multiple first cascade pads and the multiple second cascade pads are respectively arranged in the first cascade pad region 300 and the second cascade pad region 400 and aligned with both ends of the second pad region 200 .

[0072] The first cascade pad is used to cascade with the chip on one side, and the second cascade pad is used to cascade with the chip on the other side.

[0073] In this embodiment, all first cascade pads are aligned with the left end of the lower second pad region 200 , and all second cascade pads are aligned with the right end of the lower second pad region 200 .

[0074] In this embodiment, if Figure 2 , Figure 2 This is a schematic diagram of the pad layout of the driver chip of Example 3 of the present invention; the cascade pad includes multiple first cascade pads; the multiple first cascade pads include a first number of cascade pads and a second number of cascade pads; the number of the first number of cascade pads is greater than the number of the second number of cascade pads; the first number of cascade pads is aligned with the first pad area 100; and the second number of cascade pads is aligned with the second pad area 200.

[0075] In this embodiment, the majority of first cascade pads located on the left end are aligned with the first pad region 100 , and the minority of first cascade pads are aligned with the second pad region 200 . For example, if there are six first cascade pads, four first cascade pads are aligned with the first pad region 100 , and two first cascade pads are aligned with the second pad region 200 .

[0076] In this embodiment, if Figure 3 , Figure 3 This is a schematic diagram of the pad layout of a driver chip according to Example 4 of the present invention. The cascade pads include a plurality of first cascade pads; the plurality of first cascade pads include a first number of cascade pads and a second number of cascade pads; the number of the first number of cascade pads is greater than the number of the second number of cascade pads; the first number of cascade pads is aligned with the second pad region 200; and the second number of cascade pads is aligned with the first pad region 100.

[0077] In this embodiment, the majority of first cascade pads located on the left end are aligned with the second pad region 200 , and a minority of first cascade pads are aligned with the first pad region 100 . For example, if there are six first cascade pads, four first cascade pads are aligned with the second pad region 200 , and two first cascade pads are aligned with one pad region.

[0078] In this embodiment, the cascade pads include a plurality of second cascade pads; the plurality of second cascade pads include: a third number of cascade pads and a fourth number of cascade pads; the number of the third number of cascade pads is greater than the number of the fourth number of cascade pads; the third number of cascade pads is aligned with the first pad region 100; and the fourth number of cascade pads is aligned with the second pad region 200.

[0079] In this embodiment, the majority of second cascade pads located on the right end are aligned with the first pad area 100 , and the minority of second cascade pads are aligned with the second pad area 200 . For example, if there are six second cascade pads, four second cascade pads are aligned with the first pad area 100 , and two second cascade pads are aligned with the second pad area 200 .

[0080] In this embodiment, the cascade pads include a plurality of second cascade pads; the plurality of second cascade pads include a third number of cascade pads and a fourth number of cascade pads; the number of the third number of cascade pads is greater than the number of the fourth number of cascade pads; the third number of cascade pads is aligned with the second pad region 200; and the fourth number of cascade pads is aligned with the first pad region 100.

[0081] In this embodiment, the majority of second cascade pads located on the right end are aligned with the second pad area 200 , and a minority of second cascade pads are aligned with the first pad area 100 . For example, if there are six second cascade pads, four second cascade pads are aligned with the second pad area 200 , and two second cascade pads are aligned with the first pad area 100 .

[0082] The driver chip of the liquid crystal display device of the present invention is provided with an extended area 500 that penetrates the chip, a first pad area 100, and a second pad area 200. The cascade pads at both ends are aligned with the first pad area 100 or the second pad area 200. This greatly increases wiring space, avoids affecting the RC loading of the wiring, and ensures the quality of signal transmission between the driver chips.

[0083] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A driver chip for a liquid crystal display device, comprising: The first pad area is used to arrange the input pad; The second pad area is used to arrange the output pad; The first cascade pad area is used to arrange the cascade pad; The second cascade pad area is used for arranging cascade pads; expansion area; The expansion area runs through the entire chip and is arranged between the first pad area and the second pad area; The first cascade pad region and the second cascade pad region are arranged at both ends of the first pad region and / or the second pad region. The cascade pads arranged in the first cascade pad region and the second cascade pad region are aligned with the corresponding first pad region and / or the second pad region.

2. The driving chip of the liquid crystal display device according to claim 1, wherein: The cascade pad includes: Multiple first cascade pads; Multiple second cascade pads; The plurality of first cascade pads and the plurality of second cascade pads are respectively arranged in the first cascade pad region and the second cascade pad region, and are respectively aligned with two ends of the first pad region.

3. The driver chip of the liquid crystal display device according to claim 1, wherein: The cascade pad includes: Multiple first cascade pads; Multiple second cascade pads; The plurality of first cascade pads and the plurality of second cascade pads are respectively arranged in the first cascade pad region and the second cascade pad region, and are respectively aligned with two ends of the second pad region.

4. The driver chip of the liquid crystal display device according to claim 1, wherein: The cascade pad includes: Multiple first cascade pads; The plurality of first cascade pads include: A first order cascade pad and a second order cascade pad; The number of the first order of cascaded pads is greater than the number of the second order of cascaded pads; A first number of cascade pads are aligned with the first pad region; A second number of cascade pads are aligned with the second pad region.

5. The driving chip of the liquid crystal display device according to claim 1, wherein: The cascade pad includes: Multiple first cascade pads; The plurality of first cascade pads include: A first order cascade pad and a second order cascade pad; The number of the first order of cascaded pads is greater than the number of the second order of cascaded pads; A first number of cascade pads are aligned with the second pad region; A second number of cascade pads are aligned with the first pad region.

6. The driving chip of the liquid crystal display device according to claim 1, wherein: The cascade pad includes: Multiple second cascade pads; The plurality of second cascade pads include: The third order cascade pad and the fourth order cascade pad; The number of the third order of cascade pads is greater than the number of the fourth order of cascade pads; A third number of cascade pads are aligned with the first pad region; The fourth number of cascade pads is aligned with the second pad region.

7. The driver chip of the liquid crystal display device according to claim 1, wherein: The cascade pad includes: Multiple second cascade pads; The plurality of second cascade pads include: The third order cascade pad and the fourth order cascade pad; The number of the third order of cascade pads is greater than the number of the fourth order of cascade pads; A third number of cascade pads are aligned with the second pad region; The fourth number of cascade pads is aligned with the first pad region.

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