Switching device and junction field effect transistor thereof

Abstract

The utility model provides a switching device and a junction field effect transistor thereof, the junction field effect transistor comprises a junction field effect transistor and a gate capacitor, the junction field effect transistor comprises a substrate, an epitaxial layer and two bottom gates formed in the epitaxial layer; the combined top gate comprises a top gate inner region and a top gate outer region, the top gate inner region is formed in the epitaxial layer from top to bottom, the top gate outer region surrounds the bottom surface and the side surface of the top gate inner region, and a gap is formed between the top gate outer region and the bottom gate; wherein the doping concentration of the top gate outer region is smaller than that of the top gate inner region; the gate electrode is located at the position above the top gate inner region, the contact between the gate electrode and the top gate inner region is ohmic contact, and correspondingly, the potential of the top gate inner region is equal to that of the gate electrode; the gate capacitor is connected in series between the gate electrode of the junction field effect transistor and an external control voltage circuit. The technical problem that the driving voltage of a traditional switching device is limited by a junction field effect transistor is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a switching device and a junction field effect transistor thereof. Background Art

[0002] CN 117637854 B is a vertical capacitance coupled gate controlled junction field effect transistor, such as Figure 1 As shown, the gate of the JFET is floated, and a metal-gate dielectric-semiconductor capacitor is fabricated above the top gate 1-8. After the device is fabricated, the metal-gate dielectric-semiconductor capacitor is fixed, making adjustment flexibility limited. Because there is no ohmic contact between the gate dielectric (i.e., dielectric layer 1-9) and the P-type semiconductor (top gate 1-8), a Schottky barrier exists, preventing the device from being turned off at high-temperature gate-source voltage Vgs = 0V. The device comprises a substrate 1-1, an epitaxial layer 1-2, a bottom gate 1-3, a second-doped source region 1-4, a first channel 1-5, a second channel 1-6, a first-doped source region 1-7, a top gate 1-8, a dielectric layer 1-9, a coupling capacitor top electrode 1-10, a source 1-12, and a drain 1-13.

[0003] Traditional junction field-effect transistors are limited by driving voltage, which is a technical problem that those skilled in the art urgently need to solve.

[0004] The above information disclosed in the Background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Utility Model Content

[0005] The embodiments of the present application provide a switching device and a junction field effect transistor thereof to solve the technical problem that the driving voltage of a conventional switching device is limited by its junction field effect transistor.

[0006] A switching device according to an embodiment of the present application includes a junction field effect transistor and a gate capacitor, wherein the junction field effect transistor includes:

[0007] a substrate of a first doping type and an epitaxial layer of the first doping type, the epitaxial layer being located above the substrate;

[0008] two bottom gates of the second doping type, formed in the epitaxial layer and spaced apart in a laterally spaced relationship;

[0009] a combined top gate of a second doping type, the top gate comprising a top gate inner region and a top gate outer region, the top gate inner region being formed from top to bottom within the epitaxial layer, the top gate outer region surrounding a bottom surface and side surfaces of the top gate inner region, and a gap being provided between the top gate outer region and the bottom gate; wherein a doping concentration of the top gate outer region is less than a doping concentration of the top gate inner region;

[0010] a gate electrode, located above the top gate inner region, wherein the contact between the gate electrode and the top gate inner region is an ohmic contact, and correspondingly, the potential of the top gate inner region is equal to the potential of the gate electrode;

[0011] The gate capacitor is connected in series between the gate electrode of the junction field effect transistor and an external control voltage circuit.

[0012] An embodiment of the present application also provides a junction field effect transistor of a switching device, which is suitable for the above-mentioned switching device.

[0013] The embodiments of the present application adopt the above technical solutions, which have the following technical effects:

[0014] In this application, the structure between the top gate outer region 82 and the bottom gate 3 forms a junction capacitance C formed by the semiconductor depletion region formed by these two parts. 半 With the gate capacitor 14 connected in series, two capacitors are connected in series. According to the principle of capacitor voltage division, the potential on the upper surface of the top gate outer region 82 can be adjusted by the size of the gate capacitor to achieve compatibility between the gate drive voltage (corresponding to the voltage of the top gate outer region 82) and the semiconductor device such as IGBT and / or MOFET drive voltage of 15V or 18V, which facilitates circuit design. The gate capacitor of the switching device of the embodiment of the present application can be flexibly configured with gate capacitors of different capacitance values ​​according to the use environment of the switching device, and is no longer subject to the junction field effect transistor itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic diagram of patent CN117637854B in the background art;

[0017] Figure 2-1 Schematic diagram of a first implementation of a junction field effect transistor according to an embodiment of the present application;

[0018] Figure 2-2 Schematic diagram of a second implementation of a junction field effect transistor according to an embodiment of the present application;

[0019] Figure 2-3 Schematic diagram of a third implementation of a junction field effect transistor according to an embodiment of the present application;

[0020] Figure 2-4 Schematic diagram of a fourth implementation of a junction field effect transistor according to an embodiment of the present application;

[0021] Figure 3Schematic diagram of the blocking voltage of a junction field effect transistor under normal temperature and high temperature conditions according to an embodiment of the present application.

[0022] Reference numerals:

[0023] In the background technology:

[0024] Substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel 1-5,

[0025] Channel 2 1-6, first doping type source region 1-7, top gate 1-8, dielectric layer 1-9,

[0026] Coupling capacitor upper electrode 1-10, source 1-12, drain 1-13;

[0027] In this application:

[0028] Substrate 1, epitaxial layer 2, bottom gate 3, second doping type source region 4, channel 1 5,

[0029] Channel 2 61, current spreading layer 62, first doping type source region 7,

[0030] Top gate inner region 81, top gate outer region 82,

[0031] Buffer layer 100 , gate electrode 11 , source 12 , drain 13 , gate capacitor 14 . DETAILED DESCRIPTION

[0032] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0033] Example 1

[0034] like Figure 2-1 , such as 2-2, Figure 2-3 and Figure 2-4 As shown, the switching device according to the embodiment of the present application includes a junction field effect transistor and a gate capacitor 14 .

[0035] like Figure 2-1 , such as 2-2, Figure 2-3 and Figure 2-4 As shown, the junction field effect transistor includes:

[0036] A substrate 1 of a first doping type and an epitaxial layer 2 of a first doping type, wherein the epitaxial layer 2 is located above the substrate 1;

[0037] Two bottom gates 3 of the second doping type are formed in the epitaxial layer and spaced apart in the lateral direction;

[0038] A second doping type combined top gate, the top gate comprising a top gate inner region 81 and a top gate outer region 82, the top gate inner region 81 being formed from top to bottom within the epitaxial layer, the top gate outer region 82 surrounding the bottom and side surfaces of the top gate inner region 81, and a gap being provided between the top gate outer region 82 and the bottom gate 3; wherein the doping concentration of the top gate outer region 82 is lower than the doping concentration of the top gate inner region 81, and the top gate is in a floating state;

[0039] The gate electrode 11 is located above the top gate inner region 81 and the contact between the gate electrode 11 and the top gate inner region 81 is an ohmic contact. Accordingly, the potential of the top gate inner region 81 is equal to the potential of the gate electrode 11 .

[0040] The gate electrode 11 is used to connect to a gate capacitor 14. For the junction field effect transistor of the embodiment of the present application, the gate capacitor 14 is an external gate capacitor. For the switch device of the embodiment of the present application, the gate capacitor 14 is part of the switch device.

[0041] In the junction field effect transistor of the embodiment of the present application, the top gate outer region 82 surrounds the bottom and side surfaces of the top gate inner region 81, and the doping concentration of the top gate outer region 82 is lower than the doping concentration of the top gate inner region 81, so that the potential difference of the top gate from the outer surface of the top gate outer region 82 to the top surface of the top gate inner region 81 is relatively slow.

[0042] In the field of semiconductors, under uniform doping conditions, the potential expression of x in a P-type doped region is The following relationship (1) is satisfied:

[0043]

[0044] Where, e is the electron charge, N a is the doping concentration of the P-type doped region, εs is the semiconductor dielectric constant, and x p is the position where the electric field E is zero.

[0045] From this we can see that in two P-type doping regions with different doping concentrations, if the electric field E of the two P-type doping regions is zero at the same position, which P-type doping region has the highest N? a The smaller the value, the electric potential at the same position (i.e. the same x) In this way, the flow channel for carriers increases, widening the process window of the junction field effect transistor.

[0046] Taking the junction field effect transistor of the embodiment of the present application as an NMOS transistor as an example, when the upper electrode of the gate capacitor 14 is connected to a positive voltage (such as 15V), and the source of the junction field effect transistor is grounded, and the drain is connected to a positive drain voltage, an electric field is generated between the drain and the source, thereby generating a conduction current, and the direction of the current is as follows: Figure 2-4 shown.

[0047] When the bias voltage of the top electrode of the gate capacitor 14 is less than or equal to 0V, the potential of the top gate inner region 81 is less than or equal to 0V, and the top gate outer region 82 and the channel (at Figure 2-2 、 Figure 2-3 and Figure 2-4 Middle finger channel 15, in Figure 2-1 The PN junction formed by the middle finger epitaxial layer (located between the top gate outer region 82 and the bottom gate 3) is reverse biased, the channel is pinched off, and the junction field effect transistor of the present application is turned off.

[0048] In addition, simulations show that the on-resistance Ron,sp of the junction field-effect transistor of the embodiment of the present application under high temperature conditions is within three times that of normal temperature, and is compatible with the application of existing SiC MOSFETs. That is, the application scenarios of the junction field-effect transistor of the embodiment of the present application are highly compatible with the existing technology and have strong versatility.

[0049] At the same time, the contact between the gate electrode 11 and the top gate inner region 81 is an ohmic contact. When the top gate outer region 82 is reverse biased at high temperature, the top gate outer region 82 is in contact with the channel (at Figure 2-2 、 Figure 2-3 and Figure 2-4 Middle finger groove 15, in Figure 2-1 The holes generated by the PN junction formed by the middle-finger epitaxial layer (located between the top-gate outer region 82 and the bottom gate 3) flow into the top gate and out of the ohmic-contact gate electrode 11. This does not cause the floating top gate to be unable to conduct holes and thus raise the top gate potential. Therefore, the device can be turned off normally regardless of high or low temperatures, with a gate-source voltage of Vgs = 0.

[0050] In practice, the gate capacitor 14 is connected in series between the gate electrode 11 of the junction field effect transistor and an external control voltage circuit, wherein the external control voltage circuit is used to provide a control voltage for the switching device.

[0051] The principle of voltage division of capacitors in series is as follows:

[0052] Capacitor voltage Vc=I·Xc,

[0053] Capacitive reactance Xc=1 / 2πfC,

[0054] Where I is the current in the series capacitor loop, f is the frequency of the AC current, and C is the capacitance.

[0055] In this application, the structure between the top gate outer region 82 and the bottom gate 3 forms a junction capacitance C formed by the semiconductor depletion region formed by these two parts. 半 The gate capacitor 14, connected in series with the external capacitor, achieves a series connection of two capacitors. Based on the principle of capacitive voltage division, the potential on the upper surface of the top gate outer region 82 can be adjusted by the size of the gate capacitor to achieve compatibility between the gate drive voltage (corresponding to the voltage of the top gate outer region 82) and the 15V or 18V drive voltage of semiconductor devices such as IGBTs and / or MOSFETs, facilitating circuit design.

[0056] In the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention, the voltage applied by the external gate circuit to the top gate of the JFET region 1 passes through the structure between the top gate external region 82 and the bottom gate 3, and the junction capacitance C formed by the semiconductor depletion region formed by these two parts is formed. 半 The gate capacitor 14 is coupled to the gate electrode 11 in a manner of being coupled in series with the external gate capacitor 14 to control the on and off of the transistor.

[0057] In conjunction with the gate capacitor 14, the size of the gate capacitor 14 is used to adjust the potential at the gate electrode 11 so as to achieve compatibility between the gate drive voltage (corresponding to the voltage of the top gate outer region 82) and the semiconductor device drive voltage of 15V or 18V such as IGBT and / or MOFET, providing convenience for circuit design.

[0058] In implementation, such as Figure 2-1 , such as 2-2, Figure 2-3 and Figure 2-4 As shown, the top gate outer region 82 is U-shaped, the inner bottom of the top gate outer region 82 is wrapped around the bottom surface of the top gate inner region 81 , and the inner wall of the top gate outer region 82 is wrapped around the side surface of the top gate inner region 81 .

[0059] In this way, the top gate outer region 82 wraps the bottom and side surfaces of the top gate inner region 81, so that both the bottom and side surfaces of the top gate inner region 81 have the top gate outer region 82 with a slower potential change, making the overall process window of the top gate larger.

[0060] Specifically, the top gate inner region 81 is heavily doped.

[0061] The heavily doped top gate inner region 81 prevents the top gate from punching through.

[0062] In practice, the doping concentration of the top gate outer region 82 is 1 to 2 orders of magnitude lower than the doping concentration of the top gate inner region 81 .

[0063] In practice, the doping concentration of the top gate outer region 82 is in the range of greater than or equal to 2×10 17 cm -3 Less than or equal to 5×10 18 cm -3The doping concentration of the top gate inner region 81 is greater than or equal to 1×10 19 cm -3 Less than or equal to 4×10 20 cm -3 .

[0064] In practice, the thickness of the bottom of the top gate outer region 82 ranges from 0.02 μm to 0.2 μm, and the thickness of the sidewall of the top gate outer region 82 ranges from 0.02 μm to 0.2 μm.

[0065] The thickness of the top gate inner region 81 ranges from 0.02 μm to equal to 0.1 μm.

[0066] The doping concentration and thickness of the top gate inner region 81 meet the above value range requirements to prevent the depletion region on the surface of the top gate inner region 81 from being connected during blocking, resulting in a low withstand voltage. In other words, the depletion region on the surface of the top gate inner region 81 is disconnected, thus meeting the blocking withstand voltage requirement.

[0067] The doping concentration, bottom thickness and sidewall thickness of the top gate outer region 82 meet the above value range requirements in order to widen the process window of the top gate and prevent the process from failing to achieve device performance.

[0068] The first implementation method, such as Figure 2-1 As shown, the JFET region 1 is specifically formed by the top gate, the portion of the epitaxial layer located between the top gate and the bottom gate 3, and the bottom gate 3;

[0069] The two bottom gates 3 and the portion of the epitaxial layer located between the bottom gates 3 form a second JFET region.

[0070] The second implementation method is Figure 2-2 As shown, the junction field effect transistor also includes:

[0071] A first doping type channel 5 is formed between the top gate and the bottom gate 3, and the top gate is located above the first channel;

[0072] The JFET region 1 is specifically formed by a top gate, a channel 1 5, and a bottom gate 3;

[0073] The second JFET region is specifically formed by two bottom gates 3 and a portion of the epitaxial layer located between the bottom gates 3 .

[0074] The third implementation method, such as Figure 2-3 As shown, the junction field effect transistor also includes:

[0075] A first doping type channel 5 is formed between the top gate and the bottom gate 3, and the top gate is located above the first channel;

[0076] A second channel 61 of the first doping type is formed between the two bottom gates;

[0077] The JFET region 1 is specifically formed by a top gate, a channel 1 5 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 and a channel 2 61 .

[0078] The third implementation method, such as Figure 2-4 As shown, the junction field effect transistor also includes:

[0079] A first doping type channel 5 is formed between the top gate and the bottom gate 3, and the top gate is located above the first channel;

[0080] A second channel 61 of the first doping type is formed between the two bottom gates;

[0081] A current spreading layer 62 of the first doping type is formed in the epitaxial layer 2 below the bottom gate 3 and the second channel 61;

[0082] The JFET region 1 is specifically formed by a top gate, a channel 1 5 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 , a channel 2 61 , and a current spreading layer 62 .

[0083] In implementation, such as Figure 2-1 , such as 2-2, Figure 2-3 and Figure 2-4 As shown, the junction field effect transistor also includes:

[0084] a drain electrode 13, arranged on the lower surface of the substrate;

[0085] Two first doping type source regions 7 are respectively located on the two bottom gates, and the two first doping type source regions 7 are connected to a portion located between the top gate and the bottom gate 3;

[0086] Two source electrodes 12 , the source electrodes 12 on the same side are connected to the first doping type source region 7 ;

[0087] Two second doping type source regions 4 are respectively arranged on both sides of the two bottom gates 3, and the second doping type source region 4 on the same side is connected to the bottom gate 3; the source electrode is located on the junction of the first doping type source region 7 and the second doping type source region 4 on the same side, and the source electrode is connected to the first doping type source region 7 and the second doping type source region 4 on the same side;

[0088] A gate electrode 11 is formed on the top gate 81;

[0089] The buffer layer 100 is formed between the substrate 1 and the epitaxial layer 2 .

[0090] Specifically, by controlling the doping of the bottom gate 3 of the second doping type and the top gate of the second doping type, when the voltage on the coupling capacitor 14 is zero, the region sandwiched by the bottom gate 3 and the top gate is in a depletion state, and the junction field effect transistor is a normally-off device;

[0091] Alternatively, by controlling the doping of the second doping type bottom gate 3 and the second doping type top gate, when the voltage on the coupling capacitor 14 is zero, the region sandwiched by the bottom gate 3 and the top gate is in a conducting state, and the junction field effect transistor is a normally-on device.

[0092] Figure 3 This is a schematic diagram of the blocking voltage of the junction field effect transistor of the embodiment of the present application at room temperature and high temperature. Figure 3 In the graph, the horizontal axis is the drain voltage in volts, and the vertical axis is the drain current in amperes.

[0093] like Figure 3 As shown, when Vgs = 0V, the junction field effect transistor is at room temperature (corresponding to T = 300K):

[0094] When the drain voltage is less than 1800V, the drain current is always zero. When the drain voltage increases to 1800V, the drain current is larger, that is, the withstand voltage of the junction field effect transistor is 1800V.

[0095] That is when avalanche breakdown occurs.

[0096] like Figure 3 As shown, when Vgs = 0V, the junction field effect transistor is under high temperature conditions (corresponding to T = 450K):

[0097] When the drain voltage is less than 1990V, when the drain voltage increases to 1990V, the drain current is large, that is, the withstand voltage of the junction field effect transistor is 1990V;

[0098] The junction field effect transistor can be turned off normally at room temperature (corresponding to T=300K) and at high temperature (corresponding to T=450K).

[0099] The substrate 1, the epitaxial layer 2, the portion between the bottom gate 3, and the portion between the top gate and the bottom gate 3 form an internal conduction path from the drain to the two source electrodes. The internal conduction paths are all away from the area with low mobility on the device surface. The internal conduction path of the junction field effect transistor of the embodiment of the present application is located as a whole inside the field effect transistor, and the internal conduction paths are all away from the area with low mobility on the device surface. That is, the internal conduction paths are all away from the surface of the semiconductor material, and are internally conductive, avoiding the problem of low surface mobility. Therefore, the carriers are kept in a state of high mobility and drift velocity, the junction field effect transistor saturation current Idsat is large, the junction field effect transistor characteristic on-resistance Ron,sp is small, and the junction field effect transistor has better short-circuit resistance.

[0100] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0101] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0102] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0104] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0105] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A switch device, characterized in that: The invention comprises a junction field effect transistor and a gate capacitor (14), wherein the junction field effect transistor comprises: A substrate (1) of a first doping type and an epitaxial layer (2) of the first doping type, wherein the epitaxial layer (2) is located above the substrate (1); Two bottom gates (3) of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction; A combined top gate of a second doping type, the top gate comprising a top gate inner region (81) and a top gate outer region (82), the top gate inner region (81) being formed from top to bottom in the epitaxial layer, the top gate outer region (82) surrounding the bottom surface and side surfaces of the top gate inner region (81), and a gap being provided between the top gate outer region (82) and the bottom gate (3); wherein the doping concentration of the top gate outer region (82) is less than the doping concentration of the top gate inner region (81); A gate electrode (11) is located above the top gate inner region (81), and the contact between the gate electrode (11) and the top gate inner region (81) is an ohmic contact, and correspondingly, the potential of the top gate inner region (81) is equal to the potential of the gate electrode (11); The gate capacitor (14) is connected in series between the gate electrode (11) of the junction field effect transistor and an external control voltage circuit.

2. A junction field effect transistor, characterized in that include: A substrate (1) of a first doping type and an epitaxial layer (2) of the first doping type, wherein the epitaxial layer (2) is located above the substrate (1); Two bottom gates (3) of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction; A combined top gate of a second doping type, the top gate comprising a top gate inner region (81) and a top gate outer region (82), the top gate inner region (81) being formed from top to bottom in the epitaxial layer, the top gate outer region (82) surrounding the bottom surface and side surfaces of the top gate inner region (81), and a gap being provided between the top gate outer region (82) and the bottom gate (3); wherein the doping concentration of the top gate outer region (82) is less than the doping concentration of the top gate inner region (81); The gate electrode (11) is located above the top gate inner region (81), and the contact between the gate electrode (11) and the top gate inner region (81) is an ohmic contact. Accordingly, the potential of the top gate inner region (81) is equal to the potential of the gate electrode (11).

3. The junction field effect transistor according to claim 2, wherein: The top gate outer region (82) is U-shaped, the inner bottom of the top gate outer region (82) is wrapped around the bottom surface of the top gate inner region (81), and the inner wall of the top gate outer region (82) is wrapped around the side surface of the top gate inner region (81).

4. The junction field effect transistor according to claim 3, wherein The thickness of the bottom of the top gate outer region (82) is in the range of greater than or equal to 0.02 μm and less than or equal to 0.2 μm, and the thickness of the sidewall of the top gate outer region (82) is in the range of greater than or equal to 0.02 μm and less than or equal to 0.2 μm; The thickness of the top gate inner region (81) ranges from 0.02 μm to equal to 0.1 μm.

5. The junction field effect transistor according to claim 2, wherein: Also includes: A first doping type channel (5) is formed in a portion between the top gate and the bottom gate (3), wherein the top gate is located above the channel (1); The JFET region 1 is formed by a top gate, a channel 1 (5), and a bottom gate (3), and the JFET region 2 is formed by two bottom gates (3) and a portion of the epitaxial layer located between the bottom gates (3).

6. The junction field effect transistor according to claim 2, wherein: Also includes: A channel 1 (5) of a first doping type is formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; A second channel (61) of the first doping type is formed between the two bottom gates; The JFET region 1 is formed by a top gate, a channel 1 (5), and a bottom gate (3), and the JFET region 2 is formed by two bottom gates (3) and a channel 2 (61).

7. The junction field effect transistor according to claim 2, wherein: Also includes: A channel 1 (5) of a first doping type is formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; A second channel (61) of the first doping type is formed between the two bottom gates; A current spreading layer (62) of a first doping type is formed in the epitaxial layer (2) below the bottom gate (3) and the second channel (61); The JFET region 1 is formed by a top gate, a channel 1 (5), and a bottom gate (3), and the JFET region 2 is formed by two bottom gates (3), a channel 2 (61), and a current expansion layer (62).

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