Calibration circuit and electronic equipment

Abstract

A calibration circuit and an electronic device belong to the technical field of detection, the calibration circuit is connected with a differential probe, and a sampling circuit performs voltage sampling on an output signal to output a sampling signal; the control circuit outputs a first control signal according to the sampling signal; the direct current bias calibration circuit outputs a first adjusting voltage according to the first control signal; the signal conditioning circuit is further configured to perform direct current bias compensation on the single-ended signal based on the first adjusting voltage so as to output an output signal; therefore, the direct-current bias of the whole system returns to zero, the dependence of system errors on the precision of resistors, capacitors and active devices is reduced, and the accuracy of measurement results is improved.

Description

Technical Field

[0001] The present application belongs to the field of detection technology, and in particular relates to a calibration circuit and electronic equipment. Background Art

[0002] Active high-voltage differential probes, essential tools for measuring high-voltage signals, typically incorporate differential amplifier circuits, attenuation circuits, and gain adjustment mechanisms to accurately capture signals and maintain good common-mode rejection. However, these designs often rely heavily on the precise matching and characteristics of resistors, capacitors, and active components such as operational amplifiers.

[0003] The main problem with existing active high-voltage differential probes is the lack of an effective automatic correction mechanism for system errors. These errors rely heavily on the precise matching and characteristics of resistors, capacitors, and active components. Specifically, the output offset voltage of active components can cause DC bias, affecting the accuracy of measurement results. Utility Model Content

[0004] The purpose of this application is to provide a calibration circuit and electronic equipment to solve the problem that the system error in the existing active high-voltage differential probe is too dependent on the precise matching and characteristics of resistors, capacitors, and active devices, and the output offset voltage of the active device will cause DC bias, affecting the accuracy of the measurement results.

[0005] An embodiment of the present application provides a calibration circuit connected to a differential probe, wherein the differential probe includes a voltage divider and attenuation circuit, an impedance conversion circuit, a differential operation circuit, and a signal conditioning circuit connected in sequence. The voltage divider and attenuation circuit receives a signal to be measured and divides the signal to be measured to output a first differential signal. The impedance conversion circuit is configured to enhance the first differential signal to output a second differential signal. The differential operation circuit is configured to convert the second differential signal into a single-ended signal. The signal conditioning circuit is configured to perform gain adjustment on the single-ended signal to output an output signal. The calibration circuit includes:

[0006] a sampling circuit, connected to the signal conditioning circuit, and configured to perform voltage sampling on the output signal to output a sampling signal;

[0007] a control circuit connected to the sampling circuit and configured to output a first control signal according to the sampling signal;

[0008] a DC bias calibration circuit, connected to the signal conditioning circuit and the control circuit, and configured to output a first regulated voltage according to the first control signal;

[0009] The signal conditioning circuit is further configured to perform DC offset compensation on the single-ended signal based on the first regulation voltage to output the output signal.

[0010] In one embodiment, the control circuit is further configured to output a second control signal according to the sampling signal; and the calibration circuit further includes:

[0011] The common mode rejection ratio calibration circuit is connected to the voltage divider attenuation circuit, the impedance conversion circuit, and the control circuit, and is configured to adjust the first differential signal based on the second control signal to output the adjusted first differential signal.

[0012] In one embodiment, the common mode rejection ratio calibration circuit includes a first digital programmable potentiometer and a first digital programmable capacitor and a second digital programmable capacitor;

[0013] The second control signal includes three sub-second control signals;

[0014] The first end of the first digital programmable potentiometer, the second end of the first digital programmable potentiometer, the first end of the first digital programmable capacitor, and the first end of the second digital programmable capacitor collectively serve as the first differential signal input end and the adjusted first differential signal output end of the common-mode rejection ratio calibration circuit, and are connected to the voltage divider attenuation circuit and the impedance conversion circuit to input the first differential signal and output the adjusted first differential signal. The control end of the first digital programmable potentiometer serves as the first sub-second control signal input end of the common-mode rejection ratio calibration circuit, and is connected to the control circuit to receive the first sub-second control signal. The control end of the first digital programmable capacitor serves as the second sub-second control signal input end of the common-mode rejection ratio calibration circuit, and is connected to the control circuit to receive the second sub-second control signal. The control end of the second digital programmable capacitor serves as the third sub-second control signal input end of the common-mode rejection ratio calibration circuit, and is connected to the control circuit to receive the third sub-second control signal. The middle tap end of the first digital programmable potentiometer, the second end of the first digital programmable capacitor, and the second end of the second digital programmable capacitor are connected to the power ground.

[0015] In one embodiment, the control circuit is further configured to output a third control signal according to the sampling signal; and further includes:

[0016] an attenuation ratio calibration circuit, connected to the signal conditioning circuit and the control circuit, and configured to output a second regulated voltage based on the third control signal;

[0017] The signal conditioning circuit is specifically configured to adjust its own amplification ratio based on the second regulation voltage, and perform DC offset compensation on the single-ended signal based on the first regulation voltage to output the output signal.

[0018] In one embodiment, the attenuation ratio calibration circuit includes a first programmable resistor and an eighth resistor;

[0019] The control end of the first programmable resistor serves as the third control signal input end of the attenuation ratio calibration circuit and is connected to the control circuit to input the third control signal; the first end of the first programmable resistor and the first end of the eighth resistor jointly serve as the second adjustment voltage output end of the attenuation ratio calibration circuit and are connected to the signal conditioning circuit to output the second adjustment voltage; the second end of the first programmable resistor and the second end of the eighth resistor are connected to the power ground.

[0020] In one embodiment, the calibration circuit further comprises:

[0021] a mode switching circuit, connected to the control circuit and configured to output a mode switching signal according to a user operation;

[0022] The control circuit is further configured to output a switch control signal in response to the mode switching signal;

[0023] The switch circuit is connected to the signal conditioning circuit and the sampling circuit, and is configured to transmit the output signal to the sampling circuit based on the switch control signal.

[0024] In one embodiment, the DC bias calibration circuit includes a second digital programmable potentiometer and a first operational amplifier;

[0025] The control end of the second digital programmable potentiometer serves as the first control signal input end of the DC bias calibration circuit and is connected to the control circuit to receive the first control signal; the first end of the second digital programmable potentiometer is connected to the first positive power supply, and the second end of the second digital programmable potentiometer is connected to the first negative power supply; the center tap end of the second digital programmable potentiometer is connected to the positive input end of the first operational amplifier, and the negative input end of the first operational amplifier and the output end of the first operational amplifier jointly serve as the first adjustment voltage output end of the DC bias calibration circuit and are connected to the signal conditioning circuit to output the first adjustment voltage.

[0026] In one embodiment, the voltage divider attenuation circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0027] The first end of the first capacitor and the first end of the first resistor jointly serve as the positive signal-to-be-tested input end of the voltage divider and attenuation circuit to input the positive signal-to-be-tested; the first end of the third capacitor and the first end of the third resistor jointly serve as the negative signal-to-be-tested input end of the voltage divider and attenuation circuit to input the negative signal-to-be-tested; the second end of the first capacitor and the second end of the first resistor, the first end of the second capacitor, the first end of the second resistor, the second end of the third resistor, the first end of the fourth resistor, the second end of the third capacitor and the first end of the fourth capacitor jointly serve as the first differential signal output end of the voltage divider and attenuation circuit, and are connected to the impedance conversion circuit to output the first differential signal; the second end of the third capacitor is connected to the second end of the third resistor, the first end of the fourth capacitor and the first end of the fourth resistor, and the second end of the second capacitor, the second end of the second resistor, the second end of the fourth capacitor and the second end of the fourth resistor are connected to the power ground.

[0028] In one embodiment, the signal conditioning circuit includes a second operational amplifier, a fifth resistor, a sixth resistor, and a seventh resistor;

[0029] The first end of the fifth resistor serves as the first regulation voltage input end of the signal conditioning circuit and is connected to the DC bias calibration circuit to input the first regulation voltage; the first end of the sixth resistor serves as the single-ended signal input end of the signal conditioning circuit and is connected to the differential operational circuit to input the single-ended signal; the second end of the fifth resistor is connected to the first end of the seventh resistor and the negative input end of the second operational amplifier, and the second end of the sixth resistor is connected to the positive input end of the second operational amplifier. The second end of the seventh resistor and the output end of the second operational amplifier serve together as the output signal output end of the signal conditioning circuit and are connected to the sampling circuit to output the output signal.

[0030] An embodiment of the present application further provides an electronic device, which includes the above-mentioned calibration circuit.

[0031] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the control circuit outputs a first control signal to the DC bias calibration circuit according to the sampling signal, the DC bias calibration circuit outputs a first adjustment voltage according to the first control signal, and the signal conditioning circuit performs DC bias compensation on the single-ended signal based on the first adjustment voltage, thereby returning the DC bias of the entire system to zero, reducing the dependence of the system error on the accuracy of resistors, capacitors, and active devices, and improving the accuracy of the measurement results. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical application in the embodiments of the present application, the following will briefly introduce the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 A schematic diagram of a calibration circuit according to an embodiment of the present application;

[0034] Figure 2 Another structural diagram of a calibration circuit provided in one embodiment of the present application;

[0035] Figure 3 Another structural diagram of a calibration circuit provided in one embodiment of the present application;

[0036] Figure 4 Another structural diagram of a calibration circuit provided in one embodiment of the present application;

[0037] Figure 5 A partial exemplary circuit schematic diagram of a calibration circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0042] Figure 1 A schematic diagram of the structure of a calibration circuit provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0043] The above-mentioned calibration circuit is connected to the differential probe, which includes a voltage divider and attenuation circuit 91, an impedance conversion circuit 92, a differential operation circuit 93 and a signal conditioning circuit 94 connected in sequence. The voltage divider and attenuation circuit 91 is connected to the signal to be measured and divides the voltage of the signal to be measured to output a first differential signal; the impedance conversion circuit 92 is configured to enhance the first differential signal to output a second differential signal; the differential operation circuit 93 is configured to convert the second differential signal into a single-ended signal; the signal conditioning circuit 94 is configured to perform gain adjustment on the single-ended signal to output an output signal; the calibration circuit includes a sampling circuit 10, a control circuit 20, and a DC bias calibration circuit 30.

[0044] The sampling circuit 10 is connected to the signal conditioning circuit 94 and is configured to perform voltage sampling on the output signal to output a sampled signal.

[0045] The control circuit 20 is connected to the sampling circuit 10 and configured to output a first control signal according to the sampling signal.

[0046] The DC offset calibration circuit 30 is connected to the signal conditioning circuit 94 and the control circuit 20 , and is configured to output a first regulated voltage according to a first control signal.

[0047] The signal conditioning circuit 94 is further configured to perform DC offset compensation on the single-ended signal based on the first regulated voltage to output an output signal.

[0048] It can be understood that the DC offset calibration circuit 30 is used to compensate for the output offset voltage of the active devices in the signal conditioning circuit 94 so as to return the DC offset of the output signal to zero.

[0049] In a specific implementation, the signal conditioning circuit 94 can output the output signal to an oscilloscope, so that the user can directly observe the waveform of the output signal, thereby improving the convenience of calibration.

[0050] The automatic compensation mechanism combining software and hardware greatly improves calibration efficiency and operational convenience.

[0051] In the calibration mode, the standard source outputs the signal to be measured. When performing DC bias calibration, the control circuit 20 outputs a first control signal to the DC bias calibration circuit 30 according to the sampling signal. The DC bias calibration circuit 30 outputs a first adjustment voltage according to the first control signal. The signal conditioning circuit 94 performs DC bias compensation on the single-ended signal based on the first adjustment voltage until the sampling signal voltage approaches zero, thereby reducing the DC bias of the output signal output by the signal conditioning circuit 94, reducing the dependence of the system error on the accuracy of resistors, capacitors, and active devices, and improving the accuracy of the measurement results.

[0052] For example, when there is no calibration circuit, only by selecting resistors and capacitors with a precision of 0.1% can the measurement error be guaranteed to be within 1%, and the consistency between different machines is poor.

[0053] After adding the calibration circuit, resistors and capacitors with 5% accuracy are selected. After calibration, the measurement error can be controlled within 1%, and different machines maintain good consistency after calibration.

[0054] By way of example and not limitation, Figure 2 As shown, the control circuit 20 is further configured to output a second control signal based on the sampled signal. The calibration circuit also includes a common-mode rejection ratio calibration circuit 40, which is connected to the voltage divider attenuation circuit 91, the impedance conversion circuit 92, and the control circuit 20 and is configured to adjust the first differential signal based on the second control signal to output the adjusted first differential signal.

[0055] In actual use, due to the precision errors of resistors, capacitors and active devices, the bridge arms on both sides of the voltage divider attenuation circuit 91 may be unbalanced, thereby reducing the common mode rejection ratio and introducing common mode interference.

[0056] In the calibration mode, the standard source outputs the signal to be measured. When the common-mode rejection ratio is calibrated, the control circuit 20 outputs a second control signal to the common-mode rejection ratio calibration circuit 40 according to the sampling signal. The common-mode rejection ratio calibration circuit 40 adjusts the first differential signal based on the second control signal until the sampling signal voltage approaches zero. At this time, the two bridge arms in the voltage divider attenuation circuit 91 reach balance, and the common-mode rejection ratio reaches the maximum, thereby reducing the system error.

[0057] The common mode rejection ratio calibration circuit 40 effectively compensates for the imbalance between the two sides of the voltage divider attenuation circuit 91, significantly improves the common mode rejection ratio, and reduces the influence of common mode interference on the measurement result.

[0058] By way of example and not limitation, Figure 3 As shown, the control circuit 20 is further configured to output a third control signal according to the sampling signal; and further includes an attenuation ratio calibration circuit 50 connected to the signal conditioning circuit 94 and the control circuit 20, configured to output a second adjustment voltage based on the third control signal.

[0059] The signal conditioning circuit 94 is specifically configured to adjust its own amplification ratio based on the second adjustment voltage, and perform DC offset compensation on the single-ended signal based on the first adjustment voltage to output an output signal.

[0060] In actual use, the resistance error and the capacitance error in the voltage divider attenuation circuit 91 and the signal conditioning circuit 94 may cause the attenuation ratio of the differential probe to deviate from the expected value, resulting in measurement error.

[0061] In the calibration mode, the standard source outputs the signal to be measured. When the attenuation ratio calibration is performed, the control circuit 20 obtains the deviation between the measured attenuation ratio and the preset value based on the sampling signal, and outputs a third control signal based on the above deviation. The attenuation ratio calibration circuit 50 outputs a second adjustment voltage based on the third control signal until the sampling signal voltage reaches the preset value, thereby making the attenuation ratio of the differential probe more accurate and reducing the system error.

[0062] For example, when measuring a known 1kHz, 53.5Vpp sinusoidal signal, the measured signal amplitude is 51.5Vpp, and the attenuation ratio deviation is 3.7%. After calibration using the attenuation ratio calibration circuit 50, the same signal is measured again, and the measurement result is 53.2Vpp. The attenuation ratio deviation is reduced to 0.56%, thereby greatly improving the accuracy and reliability of the measurement.

[0063] The attenuation ratio calibration circuit 50 adjusts the parameters of the signal conditioning circuit 94 so that the overall attenuation ratio reaches a desired value, thereby improving the measurement accuracy of the probe.

[0064] By way of example and not limitation, Figure 4 As shown, the calibration circuit further includes a mode switching circuit 60 and a switch circuit 70 .

[0065] The mode switching circuit 60 is connected to the control circuit 20 and is configured to output a mode switching signal according to a user operation.

[0066] The control circuit 20 is further configured to output a switch control signal in response to the mode switching signal.

[0067] The switch circuit 70 is connected to the signal conditioning circuit 94 and the sampling circuit 10 , and is configured to transmit the output signal to the sampling circuit 10 based on the switch control signal.

[0068] The switch circuit 70 may include a relay.

[0069] In a specific implementation, the user switches to measurement mode or calibration mode via mode switching circuit 60. In measurement mode, control circuit 20 stops calibration, switch circuit 70 is disconnected, and the differential probe is used for normal measurement. In calibration mode, control circuit 20 performs calibration, switch circuit 70 is turned on, sampling circuit 10 samples the output signal, and the sampled signal is fed back to control circuit 20. The differential probe is used only for calibration.

[0070] The mode switching circuit 60 and the switch circuit 70 enable switching between the measurement mode and the calibration mode, thereby simplifying the calibration process and eliminating the need for the user to expend significant manpower and resources on manual calibration of the differential probe.

[0071] Figure 5 A partial exemplary circuit structure of a calibration circuit provided in an embodiment of the present application is shown. For ease of illustration, only the portion related to the embodiment of the present application is shown, as detailed below:

[0072] The voltage divider attenuation circuit 91 includes a first resistor R1 , a second resistor R2 , a third resistor R3 , a fourth resistor R4 , a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , and a fourth capacitor C4 .

[0073] The signal to be measured includes a positive signal to be measured and a negative signal to be measured.

[0074] The first end of the first capacitor C1 and the first end of the first resistor R1 jointly serve as the positive signal-to-be-tested input end of the voltage divider and attenuation circuit 91 to input the positive signal-to-be-tested; the first end of the third capacitor C3 and the first end of the third resistor R3 jointly serve as the negative signal-to-be-tested input end of the voltage divider and attenuation circuit 91 to input the negative signal-to-be-tested; the second end of the first capacitor C1 and the second end of the first resistor R1, the first end of the second capacitor C2, the first end of the second resistor R2, the second end of the third resistor R3, the first end of the fourth resistor R4, the second end of the third capacitor C3, and the first end of the fourth capacitor C4 jointly serve as the first differential signal output end of the voltage divider and attenuation circuit 91 and are connected to the impedance conversion circuit 92 to output the first differential signal; the second end of the third capacitor C3 is connected to the second end of the third resistor R3, the first end of the fourth capacitor C4, and the first end of the fourth resistor R4, and the second end of the second capacitor C2, the second end of the second resistor R2, the second end of the fourth capacitor C4, and the second end of the fourth resistor R4 are connected to the power ground.

[0075] The common mode rejection ratio calibration circuit 40 includes a first digital programmable potentiometer RP1 , a first digital programmable capacitor C5 , and a second digital programmable capacitor C6 .

[0076] The second control signal includes three sub-second control signals.

[0077] The first end of the first digital programmable potentiometer RP1, the second end of the first digital programmable potentiometer RP1, the first end of the first digital programmable capacitor C5, and the first end of the second digital programmable capacitor C6 serve together as the first differential signal input end and the adjusted first differential signal output end of the common mode rejection ratio calibration circuit 40, and are connected to the voltage divider attenuation circuit 91 and the impedance conversion circuit 92 to input the first differential signal and output the adjusted first differential signal. The control end of the first digital programmable potentiometer RP1 serves as the first sub-second control signal input end of the common mode rejection ratio calibration circuit 40, and is connected to the control circuit 92. The control circuit 20 is connected to receive the first sub-second control signal; the control end of the first digital programmable capacitor C5 serves as the second sub-second control signal input end of the common-mode rejection ratio calibration circuit 40, and is connected to the control circuit 20 to receive the second sub-second control signal; the control end of the second digital programmable capacitor C6 serves as the third sub-second control signal input end of the common-mode rejection ratio calibration circuit 40, and is connected to the control circuit 20 to receive the third sub-second control signal; the middle tap end of the first digital programmable potentiometer RP1, the second end of the first digital programmable capacitor C5, and the second end of the second digital programmable capacitor C6 are connected to the power ground.

[0078] In the voltage divider attenuation circuit 91, the first capacitor C1 and the first resistor R1 form a positive high-voltage arm, the second resistor R2 and the second capacitor C2 form a positive low-voltage arm, the third capacitor C3 and the third resistor R3 form a negative high-voltage arm, and the fourth resistor R4 and the fourth capacitor C4 form a negative low-voltage arm. The conditions for symmetry of the two bridge arms are:

[0079] R1 / R2=R3 / R4=C2 / C1=C4 / C3

[0080] The balance depends mainly on the accuracy of each resistor and capacitor.

[0081] Assume that the resistance of the first digital programmable potentiometer RP1 is divided into two parts: the resistance from the first end of the first digital programmable potentiometer RP1 to the middle tap end of the first digital programmable potentiometer RP1 is RP1+, and the resistance from the second end of the first digital programmable potentiometer RP1 to the middle tap end of the first digital programmable potentiometer RP1 is RP1-. In this case, the condition for the symmetry of the two bridge arms is:

[0082] R1 / (R2 / / RP1+)=R3 / (R4 / / RP1-)=(C2+C5) / C1=(C4+C6) / C3

[0083] Therefore, by adjusting the first digital programmable potentiometer RP1 and the first digital programmable capacitor C5 and the second digital programmable capacitor C6 to make the above balance condition meet, the common mode rejection ratio of the voltage divider attenuation circuit 91 can be calibrated.

[0084] The circuit has low cost, simple implementation and significant effect.

[0085] The signal conditioning circuit 94 includes a second operational amplifier M2 , a fifth resistor R5 , a sixth resistor R6 , and a seventh resistor R7 .

[0086] The first end of the fifth resistor R5 serves as the first adjustment voltage input end of the signal conditioning circuit 94 and is connected to the DC bias calibration circuit 30 to input the first adjustment voltage; the first end of the sixth resistor R6 serves as the single-ended signal input end of the signal conditioning circuit 94 and is connected to the differential operation circuit 93 to input the single-ended signal; the second end of the fifth resistor R5 is connected to the first end of the seventh resistor R7 and the negative input end of the second operational amplifier M2, the second end of the sixth resistor R6 is connected to the positive input end of the second operational amplifier M2, and the second end of the seventh resistor R7 and the output end of the second operational amplifier M2 serve together as the output signal output end of the signal conditioning circuit 94 and are connected to the sampling circuit 10 to output the output signal.

[0087] The DC offset calibration circuit 30 includes a second digital programmable potentiometer RP2 and a first operational amplifier M1 .

[0088] The control end of the second digital programmable potentiometer RP2 serves as the first control signal input end of the DC bias calibration circuit 30, and is connected to the control circuit 20 to receive the first control signal; the first end of the second digital programmable potentiometer RP2 is connected to the first positive power supply, and the second end of the second digital programmable potentiometer RP2 is connected to the first negative power supply; the middle tap end of the second digital programmable potentiometer RP2 is connected to the positive input end of the first operational amplifier M1, and the negative electrode of the first operational amplifier M1 and the output end of the first operational amplifier M1 jointly serve as the first adjustment voltage output end of the DC bias calibration circuit 30, and are connected to the signal conditioning circuit 94 to output the first adjustment voltage.

[0089] It can be understood that the first operational amplifier M1 constitutes a voltage follower.

[0090] The control circuit 20 can output a variable mV-level DC voltage by adjusting the parameters of the second digital programmable potentiometer RP2, and improve the driving capability through the voltage follower. The first operational amplifier M1 outputs a variable mV-level first adjustment voltage, thereby providing a variable DC input voltage to the signal conditioning circuit 94 to compensate for the DC bias generated by the active device.

[0091] The attenuation ratio calibration circuit 50 includes a first programmable resistor RH1 and an eighth resistor R8 .

[0092] The control end of the first programmable resistor RH1 serves as the third control signal input end of the attenuation ratio calibration circuit 50, and is connected to the control circuit 20 to input the third control signal; the first end of the first programmable resistor RH1 and the first end of the eighth resistor R8 jointly serve as the second adjustment voltage output end of the attenuation ratio calibration circuit 50, and are connected to the signal conditioning circuit 94 to output the second adjustment voltage; the second end of the first programmable resistor RH1 and the second end of the eighth resistor R8 are connected to the power ground.

[0093] Assuming that the single-ended signal voltage output by the differential operation circuit 93 is V1 and the first adjustment voltage output by the DC offset calibration circuit 30 is V2, the amplification ratio of the signal conditioning circuit 94 is

[0094] A0={(1+R7 / R5)*[(RH1 / / R8) / (R6+RH1 / / R8)]*V1-(1+R7 / R5)*V2} / V1

[0095] Therefore, by adjusting the resistance value of RH1, the amplification ratio of the signal conditioning circuit 94 can be adjusted, thereby adjusting the attenuation ratio of the differential probe.

[0096] The circuit has low cost, simple implementation and significant effect.

[0097] The following is combined with the working principle Figure 5 As shown for further explanation:

[0098] During calibration, the mode switching circuit 60 outputs a mode switching signal to the control circuit 20 according to the user operation, switches the mode according to the user operation, and switches the calibration circuit to the calibration mode. At this time, the control circuit 20 outputs a switch control signal to turn on the switch circuit 70, so that the sampling circuit 10 is connected to the output end of the differential probe. First, the first standard source is connected. The control circuit 20 responds to the mode switching signal and outputs a switch control signal to the switch circuit 70. The switch circuit 70 transmits the output signal to the sampling circuit 10 based on the switch control signal. The sampling circuit 10 samples the voltage of the output signal to output the sampling signal to the control circuit 20. The control circuit 20 outputs a first control signal to the control end of the second digital programmable potentiometer RP2 according to the sampling signal. The second digital programmable potentiometer RP2 outputs a DC voltage from the middle tap end of the second digital programmable potentiometer RP2 to the positive input end of the first operational amplifier M1 according to the first control signal. The driving capability of the DC voltage is improved by the first operational amplifier M1, and the first adjustment voltage is output from the negative electrode of the first operational amplifier M1 and the output end of the first operational amplifier M1 to the first end of the fifth resistor R5; the first standard source outputs the positive signal to be measured to the first end of the first capacitor C1 and the first end of the first resistor R1, and outputs the negative signal to be measured to the first end of the third capacitor C3 and the first end of the third resistor R3. The first resistor R1, the second The first resistor R2, the third resistor R3, the fourth resistor R4, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 divide the measured signal, and output a first differential signal from the second end of the first capacitor C1 and the second end of the first resistor R1, the first end of the second capacitor C2, the first end of the second resistor R2, the second end of the third resistor R3, the first end of the fourth resistor R4, the second end of the third capacitor C3, and the first end of the fourth capacitor C4 to the impedance conversion circuit 92. The impedance conversion circuit 92 improves the driving capability of the first differential signal to output a second differential signal to the differential operation circuit 93. The differential operation circuit 93 performs a differential operation on the second differential signal, converts the second differential signal into a single-ended signal, and outputs it to the first end of the sixth resistor R6. The second operational amplifier M2 performs DC offset compensation on the differential operation circuit 93 and the signal conditioning circuit 94 based on the first adjustment voltage. The output voltage is fed back to the control circuit 20 through the sampling circuit 10. The control circuit 20 adjusts the first adjustment voltage until the output signal voltage is zero, thereby completing the DC offset calibration.

[0099] After completing the DC bias calibration, a second standard source is connected. The first differential signal is input to the first end of the first digital programmable potentiometer RP1, the second end of the first digital programmable potentiometer RP1, the first end of the first digital programmable capacitor C5, and the first end of the second digital programmable capacitor C6. The control circuit 20 outputs a first sub-second control signal to the control end of the first digital programmable potentiometer RP1 to adjust the parameter of the first digital programmable potentiometer RP1, a second sub-second control signal to the control end of the first digital programmable capacitor C5 to adjust the parameter of the first digital programmable capacitor C5, and a third sub-second control signal to the control end of the second digital programmable capacitor C6 to adjust the parameter of the second digital programmable capacitor C6, thereby adjusting the first differential signal. The first end of the first digital programmable potentiometer RP1, the second end of the first digital programmable potentiometer RP1, the first end of the first digital programmable capacitor C5, and the first end of the second digital programmable capacitor C6 output the adjusted first differential signal to the impedance conversion circuit 92 until the output signal voltage reaches zero, completing the common-mode rejection ratio calibration.

[0100] After completing the common-mode rejection ratio calibration, the third standard source is connected, and the control circuit 20 outputs a third control signal to the control end of the first programmable resistor RH1 according to the sampling signal to adjust the resistance value of the first programmable resistor RH1. The first programmable resistor RH1 and the eighth resistor R8 are connected in parallel and then divided by the sixth resistor R6, thereby outputting a second adjustment voltage from the first end of the first programmable resistor RH1 and the first end of the eighth resistor R8 to the positive input end of the second operational amplifier M2. The signal conditioning circuit 94 adjusts its own amplification ratio based on the change in the resistance value of the first programmable resistor RH1, thereby adjusting the attenuation ratio of the entire system until the output signal voltage reaches the preset value, completing the attenuation ratio calibration.

[0101] After calibration is complete, close calibration mode.

[0102] An embodiment of the present application further provides an electronic device, which includes the above-mentioned calibration circuit.

[0103] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0104] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A calibration circuit connected to a differential probe, the differential probe comprising a voltage divider attenuation circuit, an impedance conversion circuit, a differential operation circuit, and a signal conditioning circuit connected in sequence, the voltage divider attenuation circuit receiving a signal to be measured and performing voltage division on the signal to be measured to output a first differential signal; the impedance conversion circuit is configured to enhance the first differential signal to output a second differential signal; the differential operation circuit is configured to convert the second differential signal into a single-ended signal; and the signal conditioning circuit is configured to perform gain adjustment on the single-ended signal to output an output signal; characterized in that: include: a sampling circuit, connected to the signal conditioning circuit, and configured to perform voltage sampling on the output signal to output a sampling signal; a control circuit connected to the sampling circuit and configured to output a first control signal according to the sampling signal; a DC bias calibration circuit, connected to the signal conditioning circuit and the control circuit, and configured to output a first regulated voltage according to the first control signal; The signal conditioning circuit is further configured to perform DC offset compensation on the single-ended signal based on the first regulation voltage to output the output signal.

2. The calibration circuit according to claim 1, wherein: The control circuit is further configured to output a second control signal according to the sampling signal; and the calibration circuit further includes: The common mode rejection ratio calibration circuit is connected to the voltage divider attenuation circuit, the impedance conversion circuit, and the control circuit, and is configured to adjust the first differential signal based on the second control signal to output the adjusted first differential signal.

3. The calibration circuit according to claim 2, wherein: The common mode rejection ratio calibration circuit includes a first digital programmable potentiometer, a first digital programmable capacitor, and a second digital programmable capacitor; The second control signal includes three sub-second control signals; The first end of the first digital programmable potentiometer, the second end of the first digital programmable potentiometer, the first end of the first digital programmable capacitor, and the first end of the second digital programmable capacitor collectively serve as the first differential signal input end and the adjusted first differential signal output end of the common-mode rejection ratio calibration circuit, and are connected to the voltage divider attenuation circuit and the impedance conversion circuit to input the first differential signal and output the adjusted first differential signal. The control end of the first digital programmable potentiometer serves as the first sub-second control signal input end of the common-mode rejection ratio calibration circuit, and is connected to the control circuit to receive the first sub-second control signal. The control end of the first digital programmable capacitor serves as the second sub-second control signal input end of the common-mode rejection ratio calibration circuit, and is connected to the control circuit to receive the second sub-second control signal. The control end of the second digital programmable capacitor serves as the third sub-second control signal input end of the common-mode rejection ratio calibration circuit, and is connected to the control circuit to receive the third sub-second control signal. The middle tap end of the first digital programmable potentiometer, the second end of the first digital programmable capacitor, and the second end of the second digital programmable capacitor are connected to the power ground.

4. The calibration circuit according to claim 1, wherein: The control circuit is further configured to output a third control signal according to the sampling signal; and further includes: an attenuation ratio calibration circuit, connected to the signal conditioning circuit and the control circuit, and configured to output a second regulated voltage based on the third control signal; The signal conditioning circuit is specifically configured to adjust its own amplification ratio based on the second regulation voltage, and perform DC offset compensation on the single-ended signal based on the first regulation voltage to output the output signal.

5. The calibration circuit according to claim 4, wherein: The attenuation ratio calibration circuit includes a first programmable resistor and an eighth resistor; The control end of the first programmable resistor serves as the third control signal input end of the attenuation ratio calibration circuit and is connected to the control circuit to input the third control signal; the first end of the first programmable resistor and the first end of the eighth resistor jointly serve as the second adjustment voltage output end of the attenuation ratio calibration circuit and are connected to the signal conditioning circuit to output the second adjustment voltage; the second end of the first programmable resistor and the second end of the eighth resistor are connected to the power ground.

6. The calibration circuit according to claim 1, wherein: Also includes: a mode switching circuit, connected to the control circuit and configured to output a mode switching signal according to a user operation; The control circuit is further configured to output a switch control signal in response to the mode switching signal; The switch circuit is connected to the signal conditioning circuit and the sampling circuit, and is configured to transmit the output signal to the sampling circuit based on the switch control signal.

7. The calibration circuit according to claim 1, wherein: The DC bias calibration circuit includes a second digital programmable potentiometer and a first operational amplifier; The control end of the second digital programmable potentiometer serves as the first control signal input end of the DC bias calibration circuit and is connected to the control circuit to receive the first control signal; the first end of the second digital programmable potentiometer is connected to the first positive power supply, and the second end of the second digital programmable potentiometer is connected to the first negative power supply; the center tap end of the second digital programmable potentiometer is connected to the positive input end of the first operational amplifier, and the negative input end of the first operational amplifier and the output end of the first operational amplifier jointly serve as the first adjustment voltage output end of the DC bias calibration circuit and are connected to the signal conditioning circuit to output the first adjustment voltage.

8. The calibration circuit according to claim 1, wherein: The voltage divider attenuation circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The signal to be tested includes a positive signal to be tested and a negative signal to be tested; The first end of the first capacitor and the first end of the first resistor jointly serve as the positive signal-to-be-tested input end of the voltage divider and attenuation circuit to input the positive signal-to-be-tested; the first end of the third capacitor and the first end of the third resistor jointly serve as the negative signal-to-be-tested input end of the voltage divider and attenuation circuit to input the negative signal-to-be-tested; the second end of the first capacitor and the second end of the first resistor, the first end of the second capacitor, the first end of the second resistor, the second end of the third resistor, the first end of the fourth resistor, the second end of the third capacitor and the first end of the fourth capacitor jointly serve as the first differential signal output end of the voltage divider and attenuation circuit, and are connected to the impedance conversion circuit to output the first differential signal; the second end of the third capacitor is connected to the second end of the third resistor, the first end of the fourth capacitor and the first end of the fourth resistor, and the second end of the second capacitor, the second end of the second resistor, the second end of the fourth capacitor and the second end of the fourth resistor are connected to the power ground.

9. The calibration circuit according to claim 1, wherein: The signal conditioning circuit includes a second operational amplifier, a fifth resistor, a sixth resistor, and a seventh resistor; The first end of the fifth resistor serves as the first regulation voltage input end of the signal conditioning circuit and is connected to the DC bias calibration circuit to input the first regulation voltage; the first end of the sixth resistor serves as the single-ended signal input end of the signal conditioning circuit and is connected to the differential operational circuit to input the single-ended signal; the second end of the fifth resistor is connected to the first end of the seventh resistor and the negative input end of the second operational amplifier, and the second end of the sixth resistor is connected to the positive input end of the second operational amplifier. The second end of the seventh resistor and the output end of the second operational amplifier serve together as the output signal output end of the signal conditioning circuit and are connected to the sampling circuit to output the output signal.

10. An electronic device, characterized in that: Comprising the calibration circuit according to any one of claims 1 to 9.

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