Display device

Abstract

The display device includes: a pixel circuit layer on a substrate; a light emitting element on the pixel circuit layer and included in the first sub-pixel, the second sub-pixel, and the third sub-pixel; a light scattering layer on the light emitting element; a light conversion pattern on the light scattering layer and including color conversion particles; and a color filter layer on the light conversion pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0011137 filed on January 24, 2024, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices and organic light emitting display devices has increased. Utility Model Content

[0005] Embodiments of the present disclosure provide a display device with improved light efficiency.

[0006] According to an embodiment of the present disclosure, a display device may include: a pixel circuit layer on a substrate; a light-emitting element on the pixel circuit layer, wherein the light-emitting element may be included in a first sub-pixel, a second sub-pixel, and a third sub-pixel, respectively; a light-scattering layer on the light-emitting element; a light-conversion pattern on the light-scattering layer, the light-conversion pattern including color-conversion particles; and a color filter layer on the light-conversion pattern.

[0007] In an embodiment, the light emitting element may emit blue light.

[0008] In an embodiment, the light scattering layer may include light scattering particles that scatter blue light.

[0009] In an embodiment, the light scattering particles may have a size in a range from about 100 nm to about 400 nm.

[0010] In an embodiment, the color conversion particles may include at least one of quantum dots having a core-shell structure, quantum rods having a core-shell structure, and quadrupod quantum dots having a core-shell structure.

[0011] In embodiments, the color conversion particles may include nanophosphors.

[0012] In an embodiment, the light conversion pattern may include first, second, and third light conversion patterns, each including first color conversion particles for converting blue light into red light and second color conversion particles for converting blue light into green light.

[0013] In an embodiment, the color filter layer may include a first color filter overlapping the first light conversion pattern in a plan view, a second color filter overlapping the second light conversion pattern in a plan view, and a third color filter overlapping the third light conversion pattern in a plan view, wherein the first color filter transmits red light, the second color filter transmits green light, and the third color filter transmits blue light.

[0014] In an embodiment, the color filter layer may include a first color filter overlapping the first light conversion pattern in a plan view, a second color filter overlapping the second light conversion pattern in a plan view, and a third color filter overlapping the third light conversion pattern in a plan view, wherein the first color filter transmits yellow light, the second color filter transmits yellow light, and the third color filter transmits blue light.

[0015] In an embodiment, the light conversion pattern may include a first light conversion pattern, a second light conversion pattern, and a third light conversion pattern, wherein the first light conversion pattern includes first color conversion particles for converting blue light into red light, the second light conversion pattern includes second color conversion particles for converting blue light into green light, and the third light conversion pattern includes light scattering particles.

[0016] In an embodiment, the color filter layer may include a first color filter overlapping the first light conversion pattern in a plan view, a second color filter overlapping the second light conversion pattern in a plan view, and a third color filter overlapping the third light conversion pattern in a plan view, wherein the first color filter transmits red light, the second color filter transmits green light, and the third color filter transmits blue light.

[0017] In an embodiment, each of the light emitting elements may include a first semiconductor layer including an n-type dopant, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer, wherein the second semiconductor layer includes a p-type dopant.

[0018] In an embodiment, each of the light emitting elements may include an anode, a light emitting structure including at least one organic light emitting layer, and a cathode disposed on the light emitting structure, wherein the light emitting structure overlaps the anode in a plan view and the cathode overlaps the anode in a plan view.

[0019] In an embodiment, the display device may further include a low-refractive layer disposed on the light conversion pattern.

[0020] In an embodiment, the display device may further include a bank separating the light scattering layer, the light conversion pattern, and the low refractive layer.

[0021] In an embodiment, the surface of the bank may have an uneven structure.

[0022] In an embodiment, the display device may further include a reflective layer disposed on the top and side surfaces of the bank.

[0023] In an embodiment, the light scattering layer may have a fine pattern.

[0024] In an embodiment, the display device may further include a capping layer disposed between the light scattering layer and the light conversion pattern.

[0025] In an embodiment, the light scattering layer may have a lattice structure including air gaps. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It shows Figure 1 A block diagram of an embodiment of one of the sub-pixels shown in FIG.

[0029] Figure 3 It shows Figure 1 A plan view of an embodiment of a display panel is shown in FIG.

[0030] Figure 4 It shows Figure 3 Schematic cross-sectional view of an embodiment of a display panel shown in .

[0031] Figure 5 It shows Figure 3 A plan view of an embodiment of one of the pixels shown in FIG.

[0032] Figure 6 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0033] Figure 7 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0034] Figure 8 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0035] Figure 9 According to an embodiment of the present disclosure, Figure 8Schematic cross-sectional view of a light emitting structure in one of the first to third light emitting elements shown in .

[0036] Figure 10 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0037] Figure 11 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0038] Figure 12 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0039] Figure 13 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0040] Figure 14 is a schematic block diagram illustrating an embodiment of a display system.

[0041] Figures 15 to 18 The embodiment according to the present disclosure is shown Figure 14 A perspective view of an application of the display system is shown in FIG. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the parts used to understand the operation according to the present disclosure are described, and the description of other parts is omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the embodiments described herein, but can be implemented in various different forms. More specifically, the embodiments described herein are provided to thoroughly and completely describe the disclosure and to fully convey the ideas of the present disclosure to those of ordinary skill in the art.

[0043] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements. Furthermore, when an element is referred to as being "in contact with" or "in contact with" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element, or "indirectly in contact with" the other element. The technical terms used herein are for the purpose of illustrating particular embodiments only and are not intended to limit the embodiments.

[0044] As used herein, the terms "one", "a", and "the" are intended to include the plural form, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, integral bodies, steps, operations, elements, parts, and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts, and / or their groups. It will be understood that for the purposes of this disclosure, "at least one of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, or two or more items in X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purposes of this disclosure, "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, or two or more items in X, Y, and Z (e.g., XYZ, XY, YZ, XZ). In the specification and claims, for purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or."

[0045] It will be understood that although the terms "first", "second" etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. In view of the measurement discussed and the error associated with the measurement of a specific amount (that is, the limitation of the measurement system), as used herein, "about" or "approximately" include the value and mean within the acceptable deviation range of the specific value determined by those of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10% or ± 5% of the value.

[0046] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "up," "above," "high," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would then be oriented as being "above" the other elements or features. Thus, the exemplary term "below" can encompass both orientations of above and below. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0047] In addition, embodiments of the present disclosure are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to represent the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0048] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0049] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0051] refer to Figure 1 , the display device DD may include a display panel DP, a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0052] The display panel DP may include subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0053] The sub-pixels SP may generate light of two or more colors. For example, each of the sub-pixels SP may generate light of red, green, blue, cyan, magenta, yellow, white, etc.

[0054] Two or more sub-pixels among the sub-pixels SP may constitute a pixel PXL. For example, the pixel PXL may include: Figure 1 Thus, the pixel PXL may emit light of various colors having various brightnesses according to a combination of light emitted from the sub-pixels included in the pixel PXL.

[0055] The gate driver 120 may be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0056] The gate driver 120 may be provided on one side of the display panel DP. However, embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically divided, and the drivers may be provided on one side of the display panel DP and on the other side of the display panel DP opposite to the one side. Therefore, in some embodiments, the gate driver 120 may be provided at the periphery of the display panel DP in various forms.

[0057] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction via the first to nth data lines DL1 to DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse signal, a source shift clock signal, a source output enable signal, and the like.

[0058] The data driver 130 may receive a voltage from the voltage generator 140. The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using the received voltage. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the first to n-th data lines DL1 to DLn. Accordingly, the corresponding subpixels SP may generate light corresponding to the data signal. As a result, an image may be displayed on the display panel DP.

[0059] In an implementation, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0060] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to components of the display device DD. The voltage generator 140 may generate the plurality of voltages by receiving an input voltage from outside the display device DD and regulating the received voltage.

[0061] The voltage generator 140 may generate a first power voltage and a second power voltage. The generated first power voltage and the second power voltage may be provided to the subpixel SP via the power line PL. In other embodiments, at least one of the first power voltage and the second power voltage may be provided from outside the display device DD.

[0062] In an embodiment, the voltage generator 140 may provide various voltages and / or signals. For example, the voltage generator 140 may provide one or more initialization voltages applied to the sub-pixel SP. For example, in a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate a reference voltage and transmit the reference voltage to the data driver 130. For example, in a display operation for displaying an image on the display panel DP, a common pixel control signal may be applied to the sub-pixel SP, and the voltage generator 140 may generate a pixel control signal. In an embodiment, the voltage generator 140 may provide a pixel control signal to the sub-pixel SP through the pixel control line PXCL. In Figure 1 , the pixel control line PXCL is shown to be connected between the voltage generator 140 and the display panel DP. However, embodiments are not limited thereto. For example, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. Pixel control signals may be transmitted from the gate driver 120 to the subpixels SP via the pixel control line PXCL.

[0063] The controller 150 may control the overall operation of the display device DD. The controller 150 may receive input image data IMG and a corresponding control signal CTRL from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0064] The controller 150 may convert the input image data IMG into a format suitable for the display device DD or the display panel DP, thereby outputting the image data DATA. In an embodiment, the controller 150 may align the input image data IMG into sub-pixels SP in a row unit, thereby outputting the image data DATA.

[0065] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on an integrated circuit. Figure 1 As shown in FIG, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 may be functionally divided into components of one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0066] Figure 2 It shows Figure 1 A block diagram of an embodiment of one of the sub-pixels shown in FIG. Figure 2In the figure, it is schematically shown that Figure 1 The sub-pixel SPij arranged on the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP shown in .

[0067] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0068] The light emitting element LD may be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be connected to Figure 1 , to receive a first power voltage. The second power voltage node VSSN may be connected to another of the power lines PL to receive a second power voltage. The first power voltage may have a voltage level higher than that of the second power voltage.

[0069] The light-emitting element LD may be connected between the anode AE ​​and the cathode CE. The anode AE ​​may be connected to a first power supply voltage node VDDN via a sub-pixel circuit SPC. For example, the anode AE ​​may be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode CE may be connected to a second power supply voltage node VSSN. The light-emitting element LD may be configured to emit light in response to a current flowing from the anode AE ​​to the cathode CE.

[0070] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first to m-th gate lines GL1 to GLm shown in FIG. Figure 1 In response to the gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC can control the light emitting element LD to emit light according to the data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to Figure 1 The sub-pixel circuit SPC may also control the light emitting element LD in response to a control signal received through the pixel control line PXCL.

[0071] For these operations, the sub-pixel circuit SPC may include circuit elements such as a transistor and one or more capacitors.

[0072] The sub-pixel circuit SPC may include a complementary metal oxide silicon (CMOS) circuit. For example, the transistors of the sub-pixel circuit SPC may include a P-type transistor and an N-type transistor. In an embodiment, the transistors of the sub-pixel circuit SPC may include a metal oxide silicon field effect transistor (MOSFET). In an embodiment, the transistors of the sub-pixel circuit SPC may include at least one of an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, and the like.

[0073] Figure 3 It shows Figure 1 A plan view of an embodiment of a display panel is shown in FIG.

[0074] refer to Figure 3 The display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed at the periphery of the display area DA.

[0075] The display panel DP may include subpixels SP in the display area DA. The subpixels SP may be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the subpixels SP may be arranged in a matrix along the first direction DR1 and the second direction DR2. In another embodiment, the subpixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. In some embodiments, the arrangement of the subpixels SP may vary. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0076] Two or more sub-pixels among the sub-pixels SP may constitute one pixel PXL. Figure 3 , the pixel PXL is shown to include three sub-pixels SP1 to SP3. However, the embodiment is not limited thereto. For example, the pixel PXL may include two sub-pixels. Hereinafter, for ease of description, an embodiment in which the pixel PXL includes first to third sub-pixels SP1 to SP3 is described.

[0077] Each of the first to third sub-pixels SP1 to SP3 can generate light of one of various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for the sake of clarity and simplicity of description, an embodiment is described in which the first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0078] Each of the first to third subpixels SP1 to SP3 may include at least one light-emitting element configured to generate light. In an embodiment, the light-emitting elements of the first to third subpixels SP1 to SP3 may generate light of the same color. For example, the light-emitting elements of the first to third subpixels SP1 to SP3 may generate blue light.

[0079] A self-luminous display panel such as a light emitting diode display panel (LED display panel) using micrometer-sized or nanometer-sized light emitting diodes as light emitting elements and an organic light emitting display panel (OLED panel) using organic light emitting diodes as light emitting elements may be used as the display panel DP.

[0080] Components for controlling the sub-pixels SP may be provided in the non-display area NDA. Lines connected to the sub-pixels SP (eg, Figure 1 The first to m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power lines PL, and the pixel control lines PXCL shown in FIG. 5 may be disposed in the non-display area NDA.

[0081] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 shown in FIG may be disposed in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 may be disposed in the non-display area NDA. The data driver 130, the voltage generator 140, and the controller 150 may be implemented in a region different from the display panel DP. Figure 1 , and the driver integrated circuit DIC may be connected to lines disposed in the non-display area NDA. In other embodiments, the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 may be implemented in an integrated circuit different from the display panel DP.

[0082] The display area DA may have various shapes in a plan view. The display area DA may have a closed loop shape including linear edges and / or curved edges. For example, the display area DA may have shapes such as a polygon, a circle, a semicircle, and an ellipse.

[0083] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a rounded display surface at least in part. In an embodiment, the display panel DP may be bendable, foldable, or rollable. The substrate of the display panel DP may include a flexible material.

[0084] Figure 4 It shows Figure 3 Schematic cross-sectional view of an embodiment of a display panel shown in .

[0085] refer to Figure 4 The display panel DP may include a substrate SUB, and a pixel circuit layer PCL, a display panel layer DPL, and a light conversion layer LCL sequentially stacked on the substrate SUB in a third direction DR3 crossing the first direction DR1 and the second direction DR2.

[0086] The substrate SUB may be made of an insulating material such as glass or resin. For example, the substrate SUB may include a glass substrate. In another embodiment, the substrate SUB may include a polyimide (PI) substrate. In yet another embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process.

[0087] In an embodiment, the substrate SUB may be made of a flexible material that is bendable or foldable and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the embodiment is not limited thereto.

[0088] The pixel circuit layer PCL may be disposed on the substrate SUB. The pixel circuit layer PCL may include an insulating layer and a semiconductor pattern and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as a circuit element, a line, or the like.

[0089] The circuit elements of the pixel circuit layer PCL can be formed Figure 3 The sub-pixel circuit SPC of each of the sub-pixels SP shown in FIG. Figure 2 ). In other words, the circuit elements of the pixel circuit layer PCL may be configured as transistors and one or more capacitors of the sub-pixel circuit SPC.

[0090] The lines of the pixel circuit layer PCL may include lines connected to each of the sub-pixels SP. The lines of the pixel circuit layer PCL may include various signal lines and / or various voltage lines for driving the display panel layer DPL.

[0091] The display panel layer DPL may be disposed on the pixel circuit layer PCL and may include light emitting elements of the sub-pixels SP.

[0092] The light conversion layer (LCL) may be disposed on the display panel layer (DPL). The light conversion layer (LCL) may include a light conversion pattern comprising color conversion particles and / or light scattering particles. For example, the color conversion particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display panel layer (DPL). In embodiments, the light conversion pattern may be omitted.

[0093] The light conversion layer LCL may further include a color filter layer including a color filter. The color filter may selectively transmit light having a specific wavelength (or a specific color). In an embodiment, the color filter layer may be omitted.

[0094] A window for protecting the exposed surface (or top surface) of the display panel DP may be provided on the light conversion layer LCL. The window may protect the display panel DP from external impacts. The window may be bonded to the light conversion layer LCL by an optically transparent adhesive (or cohesive) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. Such a multilayer structure may be formed by a continuous process or a bonding process using an adhesive layer. The entire window or a portion of the window may be flexible.

[0095] Figure 5 It shows Figure 3 A plan view of an embodiment of one of the pixels shown in FIG.

[0096] refer to Figure 5 , the pixel PXL may include first to third subpixels SP1 to SP3. The first to third subpixels SP1 to SP3 may be arranged in a first direction DR1. However, the arrangement of the pixels PXL is not limited thereto, and in some embodiments, the arrangement of the pixels PXL may be variously modified. For example, the first to third subpixels SP1 to SP3 may be arranged in a zigzag pattern.

[0097] The first to third anodes AE1 to AE3 may be provided in the first to third sub-pixels SP1 to SP3, respectively. The first anode AE1 may be provided to be connected to the sub-pixel circuit SPC (see Figure 2 ) of the anode AE ​​(see Figure 2 The second anode AE2 may be provided to be connected to the anode AE ​​of the sub-pixel circuit SPC of the second sub-pixel SP2. The third anode AE3 may be provided to be connected to the anode AE ​​of the sub-pixel circuit SPC of the third sub-pixel SP3.

[0098] One or more first light-emitting elements LD1, one or more second light-emitting elements LD2, and one or more third light-emitting elements LD3 may be disposed on first to third anodes AE1 to AE3, respectively. The first light-emitting element LD1 may be connected to the first anode AE1. The second light-emitting element LD2 may be connected to the second anode AE2. The third light-emitting element LD3 may be connected to the third anode AE3. When multiple light-emitting elements are disposed in each subpixel, each anode may have a shape extending in a direction such as the second direction DR2, and the light-emitting elements connected to the anodes may be arranged in the same direction.

[0099] The first light emitting element LD1 included in the first sub-pixel SP1 may be provided as Figure 2 The second light emitting element LD2 included in the second sub-pixel SP2 may be set to Figure 2 The third light emitting element LD3 included in the third sub-pixel SP3 may be set to Figure 2 In the case where a plurality of light emitting elements are provided in one sub-pixel, the light emitting elements may be connected in parallel between the anode and the cathode to be provided as Figure 2 The light emitting element LD shown in FIG.

[0100] The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be inorganic light emitting diodes including an inorganic light emitting material. However, the embodiment is not limited thereto. For example, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be organic light emitting diodes.

[0101] Figure 6 According to the embodiment of the present disclosure Figure 5 Schematic cross-sectional view of a pixel taken along line XX′ shown in FIG.

[0102] refer to Figure 5 and Figure 6 , the pixel circuit layer PCL, the display panel layer DPL and the light conversion layer LCL may be sequentially disposed on the substrate SUB.

[0103] The pixel circuit layer PCL may include an insulating layer, a semiconductor pattern, and a conductive pattern stacked on a substrate SUB. The insulating layer may include a buffer layer BFL, one or more interlayer insulating layers ILD, and one or more passivation layers PSV1 and PSV2. The semiconductor pattern and the conductive pattern may be located between the insulating layers. The conductive pattern may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0104] As reference Figure 2As described above, the sub-pixel circuit SPC of each of the first to third sub-pixels SP1 to SP3 (see Figure 2 ) may include transistors and one or more capacitors. The semiconductor pattern and the conductive pattern of the pixel circuit layer PCL may form the transistors and capacitors of the sub-pixel circuit SPC. The conductive pattern of the pixel circuit layer PCL may also form lines, such as Figure 1 1 to the m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power lines PL, and the pixel control lines PXCL are shown in FIG.

[0105] The buffer layer BFL may be provided on the surface of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into circuit elements and lines included in the pixel circuit layer PCL. The buffer layer BFL may include an inorganic insulating layer including an inorganic material. In an embodiment, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x ) of at least one of the metal oxides of . The buffer layer BFL can be provided as a single layer or multiple layers. In the case where the buffer layer BFL is provided as a multilayer, the layers of the multilayer can be formed of the same material or of different materials.

[0106] In an embodiment, one or more barrier layers may be disposed between the substrate SUB and the buffer layer BFL. Each of the barrier layers may include polyimide.

[0107] The first to third transistors T_SP1 to T_SP3, respectively corresponding to the first to third subpixels SP1 to SP3, may be disposed on the buffer layer BFL. The first transistor T_SP1 may be one of the transistors of the subpixel circuit SPC included in the first subpixel SP1. The second transistor T_SP2 may be one of the transistors of the subpixel circuit SPC included in the second subpixel SP2. The third transistor T_SP3 may be one of the transistors of the subpixel circuit SPC included in the third subpixel SP3. Each of the first to third transistors T_SP1 to T_SP3 may be a transistor connected to an anode of the transistor of the corresponding subpixel.

[0108] The first transistor T_SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 may be one of a source electrode and a drain electrode, and the second terminal ET2 may be the other of the source electrode and the drain electrode. For example, the first terminal ET1 may be a source electrode, and the second terminal ET2 may be a drain electrode.

[0109] The semiconductor pattern SCP may be disposed on the buffer layer BFL. The semiconductor pattern SCP may include a first contact region in contact with the first terminal ET1 and a second contact region in contact with the second terminal ET2. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the first transistor T_SP1 in a plan view (in the third direction DR3). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities. For example, p-type impurities may be used as the impurities, but embodiments are not limited thereto.

[0110] The semiconductor pattern SCP may include one of various types of semiconductors, for example, one of an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature polycrystalline silicon semiconductor, and an oxide semiconductor.

[0111] Sequentially stacked interlayer insulating layers ILD may be disposed on the semiconductor pattern SCP. The interlayer insulating layers ILD may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers ILD may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x ) of at least one of metal oxides. However, the interlayer insulating layer ILD is not limited thereto. For example, one of the interlayer insulating layers ILD may include an organic insulating layer including an organic material.

[0112] The interlayer insulating layer ILD may electrically separate the conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layer ILD. For example, the interlayer insulating layer ILD may include a gate insulating layer GI disposed on the semiconductor pattern SCP. The gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE, such that the gate electrode GE is spaced apart from the semiconductor pattern SCP. In embodiments, the gate insulating layer GI may be disposed entirely over the semiconductor pattern SCP and the buffer layer BFL to cover the semiconductor pattern SCP and the buffer layer BFL. As the number of layers required in the conductive and / or semiconductor patterns increases, the number of interlayer insulating layers ILD may increase.

[0113] The gate electrode GE may be disposed on the gate insulating layer GI. In a plan view, the gate electrode GE may overlap the channel region of the semiconductor pattern SCP. The gate electrode GE may be provided as a single layer including at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In an embodiment, the gate electrode GE may be provided as a multilayer including at least one of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0114] The first terminal ET1 and the second terminal ET2 may be disposed on the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 may contact the semiconductor pattern SCP through a contact hole passing through the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 may contact the first contact region and the second contact region of the semiconductor pattern SCP, respectively. Each of the first terminal ET1 and the second terminal ET2 may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0115] Although the first terminal ET1 and the second terminal ET2 are shown as being electrically connected to separate electrodes of the semiconductor pattern SCP, embodiments are not limited thereto. In some embodiments, the first terminal ET1 may be a first contact region adjacent to one side of the channel region of the semiconductor pattern SCP, and the second terminal ET2 may be a second contact region adjacent to the other side of the channel region of the semiconductor pattern SCP. The first terminal ET1 may be electrically connected to the first light emitting element LD1 via a connection device, such as a bridge electrode provided on at least one of the interlayer insulating layers ILD.

[0116] In an embodiment, the first transistor T_SP1 may be configured as a low-temperature polysilicon transistor. However, the embodiment is not limited thereto. For example, the first transistor T_SP1 may be configured as an oxide semiconductor transistor. In an embodiment, the sub-pixel circuit of each sub-pixel may include transistors of different types. For example, the first transistor T_SP1 may be configured as a low-temperature polysilicon transistor, and another transistor of the first sub-pixel SP1 may be configured as an oxide semiconductor transistor. The oxide semiconductor of the corresponding oxide semiconductor transistor may be disposed on one of the interlayer insulating layers ILD, rather than on the insulating layer of the semiconductor pattern SCP on which the first transistor T_SP1 is disposed.

[0117] The embodiment in which the first transistor T_SP1 is a transistor having a top-gate structure is described. However, the embodiment is not limited thereto. For example, the first transistor T_SP1 may be a transistor having a bottom-gate structure. The structure of the first transistor T_SP1 may be variously modified.

[0118] Each of the second transistor T_SP2 and the third transistor T_SP3 may be configured identically to the first transistor T_SP1. Hereinafter, overlapping descriptions will be omitted.

[0119] At least a portion of various lines of the display panel DP and / or the display device DD may also be disposed on the interlayer insulating layer ILD.

[0120] The first passivation layer PSV1 may be disposed on the first to third transistors T_SP1 to T_SP3. The passivation layer may be a protective layer or a via layer. The first passivation layer PSV1 may protect components disposed thereunder and provide a flat top surface.

[0121] The first to third connection patterns CP1 to CP3 may be disposed on the first passivation layer PSV1. The first to third connection patterns CP1 to CP3 may be connected to the first terminals ET1 of the first to third transistors T_SP1 to T_SP3, respectively, while passing through the first passivation layer PSV1. The first to third connection patterns CP1 to CP3 may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0122] At least a portion of various lines of the display panel DP and / or the display device DD may also be disposed on the first passivation layer PSV1 .

[0123] The second passivation layer PSV2 may be disposed on the first to third connection patterns CP1 to CP3 and the first passivation layer PSV1. The second passivation layer PSV2 may protect components disposed thereunder and provide a flat top surface.

[0124] Each of the first passivation layer PSV1 and the second passivation layer PSV2 may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x The organic insulating layer may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0125] One of the interlayer insulating layers ILD and the first and second passivation layers PSV1 and PSV2 may include the same material, but the embodiment is not limited thereto. Each of the first and second passivation layers PSV1 and PSV2 may be provided as a single layer or multiple layers.

[0126] The display panel layer DPL may be disposed on the second passivation layer PSV2 and may include first to third anodes AE1 to AE3, a first bank BNK1, first to third light emitting elements LD1 to LD3, an overcoat OCL, a cathode CE, and a first capping layer CPL1. Figure 6 The first to third light emitting elements LD1 to LD3 shown in FIG. 1 may be configured with light emitting diodes of a micrometer scale or a nanometer scale.

[0127] On the pixel circuit layer PCL, first to third anodes AE1 to AE3 may be disposed in first to third sub-pixels SP1 to SP3 , respectively.

[0128] The first anode AE1 can be electrically connected to the first connection pattern CP1 via a contact hole passing through the second passivation layer PSV2. The second anode AE2 can be electrically connected to the second connection pattern CP2 via another contact hole passing through the second passivation layer PSV2. The third anode AE3 can be electrically connected to the third connection pattern CP3 via another contact hole passing through the second passivation layer PSV2. Thus, the first to third anodes AE1 to AE3 can be electrically connected to the first to third transistors T_SP1 to T_SP3, respectively.

[0129] The first bank BNK1 may be provided on the first to third anodes AE1 to AE3. The first bank BNK1 may include a first opening OP1 that exposes portions of the first to third anodes AE1 to AE3 in a plan view. The first to third light-emitting elements LD1 to LD3 may be provided in the first opening OP1 of the first bank BNK1. Thus, the first bank BNK1 may be provided as a pixel-defining layer defining a region in which the first to third light-emitting elements LD1 to LD3 are located.

[0130] The first bank BNK1 may include a light-blocking material to prevent light from mixing between adjacent sub-pixels. In an embodiment, the first bank BNK1 may include an organic material. For example, the first bank BNK1 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. To further improve luminous efficiency, a reflective layer including a reflective material may be provided on a side surface of the first bank BNK1 adjacent to the first opening OP1.

[0131] The first to third light emitting elements LD1 to LD3 may be disposed on the first to third anodes AE1 to AE3, respectively. The first to third light emitting elements LD1 to LD3 may be bonded to the first to third anodes AE1 to AE3, respectively.

[0132] The first light-emitting element LD1 may include a bonding electrode BDE, a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an auxiliary layer 14. The first light-emitting element LD1 may be implemented as a vertical light-emitting stacked structure in which the bonding electrode BDE, the second semiconductor layer 13, the active layer 12, the first semiconductor layer 11, and the auxiliary layer 14 are sequentially stacked in the third direction DR3. However, embodiments are not limited thereto. For example, the first light-emitting element LD1 may be implemented as a flip-chip light-emitting element or a lateral chip light-emitting element.

[0133] The first semiconductor layer 11 may provide electrons to the active layer 12. The first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto, and various materials may constitute the first semiconductor layer 11. In an embodiment, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). In some embodiments, the first semiconductor layer 11 and the auxiliary layer 14 together may constitute an n-type semiconductor layer.

[0134] The active layer 12 may be provided on the first semiconductor layer 11 and is a region where electrons and holes recombine. Since electrons and holes can recombine in the active layer 12, light having an energy level changed to a low energy level and a wavelength corresponding to the low energy level can be generated. The active layer 12 may be formed as a single quantum well structure or a multi-quantum well structure. In the case where the active layer 12 is formed as a multi-quantum well structure, units including a barrier layer, a strain enhancement layer, and a well layer may be repeatedly stacked on each other to form the active layer 12. However, the embodiment of the active layer 12 is not limited thereto.

[0135] The second semiconductor layer 13 may be disposed on the active layer 12 and provide holes to the active layer 12. The second semiconductor layer 13 may include a semiconductor layer of a different type from that of the first semiconductor layer 11. In an embodiment, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba). However, the material constituting the second semiconductor layer 13 is not limited thereto, and various materials may constitute the second semiconductor layer 13. For example, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0136] The bonding electrode BDE may be electrically connected to the second semiconductor layer 13. The bonding electrode BDE may include a eutectic metal.

[0137] The auxiliary layer 14 may include a gallium nitride (GaN) semiconductor material that is not doped with impurities. In some embodiments, the auxiliary layer 14 and the first semiconductor layer 11 together may constitute an n-type semiconductor layer.

[0138] The first light-emitting element LD1 may further include an insulating film 15 covering the outer peripheral surface of the vertical light-emitting stacked structure. The insulating film 15 may prevent electrical short circuits that may occur when the active layer 12 contacts another conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 15 may include a transparent insulating material. The insulating film 15 may be configured to expose the bottom surface of the bonding electrode BDE opposite the second semiconductor layer 13. In addition, the insulating film 15 may be configured to expose the top surface of the auxiliary layer 14 to be in contact with the cathode CE.

[0139] The bottom surface of the bonding electrode BDE may be connected to the first anode AE1. The top surface of the auxiliary layer 14 may be connected to the cathode CE. Therefore, the first light emitting element LD1 may be electrically connected between the first anode AE1 and the cathode CE.

[0140] In an embodiment, a reflective electrode may be provided between the bonding electrode BDE and the second semiconductor layer 13. Light emitted from the first light-emitting element LD1 can be efficiently output toward the light conversion layer LCL. The reflective electrode may be configured with a conductive material having a predetermined or selectable reflectivity. The conductive material may include an opaque metal. The opaque metal may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of the reflective electrode is not limited thereto.

[0141] Each of the second light emitting element LD2 and the third light emitting element LD3 may be configured identically to the first light emitting element LD1 .

[0142] An overcoat layer (OCL) may be disposed in the first opening OP1 in which the first to third light-emitting elements LD1 to LD3 are disposed. The overcoat layer (OCL) may secure the first to third light-emitting elements LD1 to LD3, which are bonded to the first to third anodes AE1 to AE3, so that they do not move. Furthermore, the overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign matter, such as dust or moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy resin, but embodiments are not limited thereto.

[0143] The cathode CE may be disposed on the first to third light emitting elements LD1 to LD3. The cathode CE may be completely disposed on the first bank BNK1, the first to third light emitting elements LD1 to LD3, and the overcoat layer OCL. The cathode CE may be in contact with the auxiliary layer 14 of each of the first to third light emitting elements LD1 to LD3. The cathode CE may be electrically connected to Figure 2 The second power supply voltage node VSSN is shown in FIG. The second power supply voltage applied to the second power supply voltage node VSSN may be transferred to the first to third light emitting elements LD1 to LD3 through the cathode CE.

[0144] The cathode CE may be substantially transparent or translucent to meet a predetermined or selectable light transmittance. In an embodiment, the cathode CE may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the cathode CE is not limited thereto.

[0145] The first capping layer CPL1 may be disposed on the cathode CE. The first capping layer CPL1 may protect components disposed below the first capping layer CPL1, such as the cathode CE and the first to third light emitting elements LD1 to LD3, from external moisture, humidity, etc. The first capping layer CPL1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x However, the material of the first capping layer CPL1 is not limited thereto.

[0146] The light conversion layer LCL may be disposed on the first capping layer CPL1 and may include a second bank BNK2, a reflective layer RFL, a light scattering layer SCL, first to third light conversion patterns CCP1 to CCP3, a low refractive layer LRL, a second capping layer CPL2, and a color filter layer CFL.

[0147] The second bank BNK2 may be disposed on the first capping layer CPL1. The second bank BNK2 may overlap the first bank BNK1 in a plan view. The second bank BNK2 may have a second opening OP2 that overlaps the first opening OP1 in a plan view. The second bank BNK2 may separate the light scattering layer SCL, the low-refractive layer LRL, and the first to third light conversion patterns CCP1 to CCP3 corresponding to the first to third sub-pixels SP1 to SP3.

[0148] The second bank BNK2 may include a light blocking material to prevent light from mixing between adjacent pixels and between the first to third sub-pixels SP1 to SP3. In an embodiment, the second bank BNK2 may include an organic material. For example, the second bank BNK2 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0149] The reflective layer RFL may be disposed on the side surface and top surface of the second bank BNK2 adjacent to the second opening OP2. The reflective layer RFL may be configured to reflect incident light and thus improve luminous efficiency. The reflective layer RFL may include a material suitable for reflecting light. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, embodiments are not limited thereto.

[0150] The emission area EMA and the non-emission area NEMA of the first to third subpixels SP1 to SP3 may be defined by the second bank BNK2. The area overlapping the second bank BNK2 in a plan view may correspond to the non-emission area NEMA. The area overlapping the second opening OP2 of the second bank BNK2 may correspond to the emission area EMA.

[0151] On the first capping layer CPL1 , a light scattering layer SCL may be disposed in the second opening OP2 .

[0152] In an embodiment, the light scattering layer SCL can scatter incident light, thereby outputting the incident light in a Lambertian manner. Light emitted while passing through the light scattering layer SCL can have a Lambertian distribution. For example, blue light emitted from the first to third light-emitting elements LD1 to LD3 and incident on the light scattering layer SCL can be output in a Lambertian manner via the light scattering layer SCL. The light scattering layer SCL can scatter light emitted from the first to third light-emitting elements LD1 to LD3, which are point light sources at the micrometer or nanometer scale, to form a surface light source. As a result, diffuse reflection (or scattering) and recycling of blue light can effectively occur in the first to third light conversion patterns CCP1 to CCP3, thereby improving the light conversion efficiency of the first and second color conversion particles QD1 and QD2. For example, the light scattering layer SCL can increase the optical path of blue light at a high resolution (e.g., 2000 ppi or higher), thereby effectively inducing diffuse reflection and recycling of blue light.

[0153] The light scattering layer (SCL) may include light scattering particles (SCT). For example, the light scattering particles (SCT) may include at least one of silicon dioxide, titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc peroxide (ZnO2), tin oxide (SnO2), antimony oxide (Sb2O3), and indium tin oxide (ITO). The light scattering particles (SCT) may have a size suitable for outputting incident light in a Lambertian form. For example, the size of the light scattering particles (SCT) may be in the range of approximately 100 nm to approximately 400 nm.

[0154] On the light scattering layer SCL, first to third light conversion patterns CCP1 to CCP3 may be disposed in the second openings OP2 .

[0155] The first to third light conversion patterns CCP1 to CCP3 may include color conversion particles and light scattering particles. The color conversion particles may change the wavelength of incident light, thereby converting the incident light into light of another color. In addition, the color conversion particles may scatter the incident light. The light scattering particles may scatter the incident light.

[0156] In an embodiment, the color conversion particles may include at least one of quantum dots having a core-shell structure, quantum rods having a core-shell structure, and quadruped quantum dots having a core-shell structure. The core may include at least one of CdSe, CdS, CdTe, ZnS, ZnSe, ZnTe, CdSeTe, CdZnS, CdSeS, PbSe, PbS, PbTe, AgInZnS, HgS, HgSe, HgTe, GaN, GaP, GaAs, InP, InZnP, InGaP, InGaN InAs, AgInGaS, CuInGaS, and ZnO. The shell may include at least one of CdS, CdSe, CdTe, CdO, ZnS, ZnSe, ZnTe, ZnO, InP, InS, GaP, GaN, GaO, InZnP, InGaP, InGaN, InZnSCdSe, PbS, TiO, SrSe, and HgSe.

[0157] In an embodiment, the color conversion particles may include nanophosphors. The nanophosphors may be configured with an inorganic material. For example, the nanophosphors may include at least one of garnet, silicate, sulfide, nitrogen oxide, nitride, and aluminate. For example, the nanophosphors may include Y3Al5O 12 :Ce 3+ (YAG:Ce), Tb3Al5O 12 :Ce 3+ (TAG:Ce), (Sr,Ba,Ca)2SiO4:Eu 2+ , (Sr,Ba,Ca,Mg,Zn)2Si(OD)4:Eu 2+ (D=F, Cl, S, N or Br), Ba2MgSi2O7:Eu 2 + 、Ba2SiO4:Eu 2+ 、Ca3(Sc,Mg)2Si3O 12 :Ce 3+ 、(Ca,Sr)S:Eu 2+ 、(Sr,Ca)Ga2S4:Eu 2+ 、SrSi2O2N2:Eu 2+ 、SiAlON:Ce 3+ 、β-SiAlON:Eu 2+ 、Ca-α-SiAlON:Eu 2+ 、Ba3Si6O 12 N2:Eu 2+ 、CaAlSiN3:Eu 2+ 、(Sr,Ca)AlSiN3:Eu 2+ 、Sr2Si5N8:Eu2+ 、(Sr,Ba)Al2O4:Eu 2+ 、(Mg,Sr)Al2O4:Eu 2+ and BaMg2Al 16 O 27 :Eu 2+ At least one of .

[0158] In an embodiment, the first to third light-emitting elements LD1 to LD3 may emit blue light. In an embodiment, the first to third light-conversion patterns CCP1 to CCP3 may be configured with substantially the same material. For example, the first light-conversion pattern CCP1 may include first color-conversion particles QD1 for converting blue light into red light, second color-conversion particles QD2 for converting blue light into green light, and light-scattering particles. In an embodiment, the second light-conversion pattern CCP2 may include first color-conversion particles QD1 for converting blue light into red light, second color-conversion particles QD2 for converting blue light into green light, and light-scattering particles. In an embodiment, the third light-conversion pattern CCP3 may include first color-conversion particles QD1 for converting blue light into red light, second color-conversion particles QD2 for converting blue light into green light, and light-scattering particles.

[0159] Thus, the first to third light conversion patterns CCP1 to CCP3 can emit light of the same color. For example, white light can be emitted from the first to third light conversion patterns CCP1 to CCP3. The white light emitted from the first to third light conversion patterns CCP1 to CCP3 can be emitted as red light, green light, and blue light while passing through the first to third color filters CF1 to CF3 of the color filter layer CFL. Therefore, the first to third subpixels SP1 to SP3 can be set as red subpixels, green subpixels, and blue subpixels, respectively.

[0160] On the first to third light conversion patterns CCP1 to CCP3 , the low refractive layer LRL may be disposed in the second opening OP2 .

[0161] In an embodiment, the low-refractive layer LRL may have a refractive index lower than that of each of the first to third light conversion patterns CCP1 to CCP3 and the first to third color filters CF1 to CF3. The low-refractive layer LRL may be configured to refract or totally reflect light according to the incident angle of the corresponding light. The low-refractive layer LRL may provide the light that has passed through the first to third light conversion patterns CCP1 to CCP3 back to the first to third light conversion patterns CCP1 to CCP3. Thus, the light conversion efficiency of the first to third light conversion patterns CCP1 to CCP3 may be improved. The low-refractive layer LRL may have a thickness in a range of approximately 0.5 μm to approximately 1 μm.

[0162] The second capping layer CPL2 may be disposed on the low refractive layer LRL. The second capping layer CPL2 may be completely disposed on the low refractive layer LRL and the reflective layer RFL. The second capping layer CPL2 may protect components disposed below the second capping layer CPL2, such as the low refractive layer LRL and the first to third light conversion patterns CCP1 to CCP3, from external moisture, humidity, and the like. The second capping layer CPL2 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x However, the material of the second capping layer CPL2 is not limited thereto.

[0163] A color filter layer CFL may be disposed on the second capping layer CPL2. The color filter layer CFL may include first to third color filters CF1 to CF3 and a light blocking pattern LBP. The first to third color filters CF1 to CF3 may overlap with the first to third light conversion patterns CCP1 to CCP3, respectively, in a plan view. Each of the first to third color filters CF1 to CF3 may selectively transmit light within a desired wavelength range.

[0164] In an embodiment, the first color filter CF1 may selectively transmit red light. In an embodiment, the second color filter CF2 may selectively transmit green light. In an embodiment, the third color filter CF3 may selectively transmit blue light. In an embodiment, the first and second color filters CF1 and CF2 may reflect blue light. Therefore, the light conversion efficiency of the first to third light conversion patterns CCP1 to CCP3 can be improved by recycling blue light. However, embodiments are not limited thereto. For example, the first and second color filters CF1 and CF2 may selectively transmit yellow light, and the third color filter CF3 may selectively transmit blue light.

[0165] A light-blocking pattern LBP may be disposed between color filters CF1 to CF3. An emission area (or light-emitting area) EMA and a non-emission area NEMA of the first to third subpixels SP1 to SP3 may be defined by the light-blocking pattern LBP. A region corresponding to the light-blocking pattern LBP may correspond to the non-emission area NEMA. A region that does not overlap with the light-blocking pattern LBP in a plan view may correspond to the emission area EMA.

[0166] In an embodiment, the light-blocking pattern LBP may include at least one of various light-blocking materials. In an embodiment, each of the light-blocking patterns LBP may be configured as a multilayer structure in which at least two color filters among the first to third color filters CF1 to CF3 overlap each other in a plan view. For example, each of the light-blocking patterns LBP may be formed as the first to third color filters CF1 to CF3 overlapping each other. For example, the light-blocking pattern between the first and second color filters CF1 and CF2 among the light-blocking patterns LBP may be formed as a multilayer structure in which the first and second color filters CF1 and CF2 overlap each other, and the light-blocking pattern between the second and third color filters CF2 and CF3 among the light-blocking patterns LBP may be formed as a multilayer structure in which the second and third color filters CF2 and CF3 overlap each other. For example, the light-blocking pattern between the first and third color filters CF1 and CF3 of adjacent pixels may be formed as a multilayer structure in which the first and third color filters CF1 and CF3 overlap each other. Therefore, each of the first to third color filters CF1 to CF3 may extend to the non-emission area NEMA to form the light blocking pattern LBP.

[0167] Figure 7 According to the embodiment of the present disclosure Figure 5 A schematic cross-sectional view of a pixel taken along line XX' shown in FIG. Figure 7 , will simplify or omit Figure 6 A description of those overlapping parts shown in .

[0168] refer to Figure 7 , the first to third light-emitting elements LD1 to LD3 may emit blue light. In embodiments, the first to third light conversion patterns CCP1 to CCP3 may be configured with different materials. For example, the first light conversion pattern CCP1 may include light-scattering particles and first color conversion particles QD1 for converting blue light into red light. For example, the second light conversion pattern CCP2 may include light-scattering particles and second color conversion particles QD2 for converting blue light into green light. For example, the third light conversion pattern CCP3 may include light-scattering particles SCT. For example, the light-scattering particles SCT may scatter blue light.

[0169] Thus, different colors of light can be emitted from the first to third light conversion patterns CCP1 to CCP3. For example, light of a color obtained by mixing red and blue can be emitted from the first light conversion pattern CCP1. For example, light of a color obtained by mixing green and blue can be emitted from the second light conversion pattern CCP2. For example, blue light can be emitted from the third light conversion pattern CCP3. The different colors of light emitted from the first to third light conversion patterns CCP1 to CCP3 can be emitted as red light, green light, and blue light, respectively, while passing through the first to third color filters CF1 to CF3 of the color filter layer CFL. Therefore, the first to third subpixels SP1 to SP3 can be configured as red subpixels, green subpixels, and blue subpixels, respectively.

[0170] Figure 8 According to the embodiment of the present disclosure Figure 5 A schematic cross-sectional view of a pixel taken along line XX' shown in FIG. Figure 8 , will simplify or omit Figure 6 A description of those overlapping parts shown in .

[0171] refer to Figure 8 , the display panel layer DPL may include first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, a cathode electrode CE, and a first capping layer CPL1 . Figure 8 Each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 may be configured as an organic light emitting diode.

[0172] The pixel defining layer PDL may include a first opening OP1 exposing portions of the first to third anodes AE1 to AE3 in a plan view. The pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked in sequence, and each of the first to third inorganic insulating layers may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. However, embodiments are not limited thereto. The first to third inorganic insulating layers may have a stepped cross-section in a region adjacent to the first opening OP1.

[0173] The partition may be provided in a boundary region between adjacent sub-pixels. The partition may form a discontinuity in the light emitting structure EMS in the boundary region. For example, the light emitting structure EMS may be cut or bent by the partition in the boundary region.

[0174] The spacer may be provided in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more grooves TRCH1 and TRCH2 as spacers. In an embodiment, the one or more grooves TRCH1 and TRCH2 may pass through the pixel defining layer PDL and partially pass through the second passivation layer PSV2. In an embodiment, the one or more grooves TRCH1 and TRCH2 may pass through the pixel defining layer PDL and the second passivation layer PSV2 and partially pass through the first passivation layer PSV1. In an embodiment, the one or more grooves TRCH1 and TRCH2 may at least partially pass through the second passivation layer PSV2 and / or the first passivation layer PSV1, and a portion of the pixel defining layer PDL may be provided in the one or more grooves TRCH1 and TRCH2.

[0175] The pixel defining layer PDL may include two trenches TRCH1 and TRCH2 in the boundary region. However, embodiments are not limited thereto. For example, the pixel defining layer PDL may include one trench in the boundary region. In another embodiment, the pixel defining layer PDL may include three or more trenches in the boundary region.

[0176] Due to the first and second trenches TRCH1 and TRCH2, discontinuities such as first and second gaps VD1 and VD2 may be formed in the boundary region of the light emitting structure EMS. Some of the multiple layers stacked in the light emitting structure EMS may be cut or bent by the first and second gaps VD1 and VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be cut by the first and second gaps VD1 and VD2. Therefore, due to the first and second trenches TRCH1 and TRCH2, portions of the light emitting structure EMS included in the first to third subpixels SP1 to SP3 may be at least partially separated from each other.

[0177] exist Figure 8 , the first void VD1 and the second void VD2 are shown formed in the light emitting structure EMS in the boundary region. However, the embodiment is not limited thereto. For example, a concave valley may be formed in the light emitting structure EMS in the boundary region. The discontinuity formed in the light emitting structure EMS may be variously changed depending on the shape of the first trench TRCH1 and the second trench TRCH2.

[0178] The light emitting structure EMS may be provided on the first to third anodes AE1 to AE3 exposed by the first opening OP1 of the pixel defining layer PDL. In an embodiment, the light emitting structure EMS may be formed by a process such as vacuum deposition or inkjet printing. The light emitting structure EMS may fill the first opening OP1 of the pixel defining layer PDL and may be provided entirely throughout the first to third sub-pixels SP1 to SP3. As described above, the light emitting structure EMS may be partially cut or bent by the partition in the boundary area. Therefore, in the display panel DP (see Figure 3 ), the magnitude of current leaking from each of the first to third sub-pixels SP1 to SP3 to adjacent sub-pixels through the layers included in the light emitting structure EMS can be reduced. Therefore, the first to third light emitting elements LD1 to LD3 can operate with relatively high reliability.

[0179] The cathode CE may be disposed above the light emitting structure EMS. The cathode CE may be commonly disposed in the first to third subpixels SP1 to SP3. The cathode CE may function as a half mirror that allows light emitted from the light emitting structure EMS to partially transmit therethrough and partially reflect therefrom.

[0180] The first anode AE1, the portion of the light emitting structure EMS overlapping with the first anode AE1, and the portion of the cathode CE overlapping with the first anode AE1 may constitute a first light emitting element LD1. The second anode AE2, the portion of the light emitting structure EMS overlapping with the second anode AE2, and the portion of the cathode CE overlapping with the second anode AE2 may constitute a second light emitting element LD2. The third anode AE3, the portion of the light emitting structure EMS overlapping with the third anode AE3, and the portion of the cathode CE overlapping with the third anode AE3 may constitute a third light emitting element LD3.

[0181] The first capping layer CPL1 may be disposed on the cathode electrode CE. The first capping layer CPL1 may serve as an encapsulation layer that prevents oxygen and / or moisture from penetrating into the display panel layer DPL.

[0182] Figure 9 According to an embodiment of the present disclosure, Figure 8 Schematic cross-sectional view of a light emitting structure in one of the first to third light emitting elements shown in .

[0183] refer to Figure 9 , the light emitting structure EMS may have a series structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked. The light emitting structure EMS may have a series structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked. Figure 8 Each of the first to third light emitting elements LD1 to LD3 shown in FIG is configured substantially identically.

[0184] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2. In an embodiment, the second light-emitting layer EML2 may be an organic light-emitting layer including an organic material.

[0185] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer. In an embodiment, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0186] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer. In an embodiment, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may further include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0187] A connection layer, which may be provided in the form of a charge generation layer CGL, may be provided between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-type dopant layer and an n-type dopant layer. For example, the p-type dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-type dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, embodiments are not limited thereto.

[0188] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of the same color. For example, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate blue light. However, the embodiment is not limited thereto. For example, one of the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate blue light, and the other of the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of a color different from blue.

[0189] and Figure 9 Unlike that shown in FIG, in another embodiment, the light emitting structure EMS may include one light emitting unit in each of the first to third light emitting elements LD1 to LD3. The light emitting units included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of the same color. For example, the light emitting units of the first to third light emitting elements LD1 to LD3 may emit blue light. The light emitting units of the first to third sub-pixels SP1 to SP3 may be separated from each other, and the separated light emitting units may be disposed in the first opening OP1 of the pixel defining layer PDL.

[0190] Figure 10 According to the embodiment of the present disclosure Figure 5 A schematic cross-sectional view of a pixel taken along line XX' shown in FIG. Figure 10 , will simplify or omit Figure 6 A description of those overlapping parts shown in .

[0191] refer to Figure 10 , the first to third light-emitting elements LD1 to LD3 may emit blue light. In embodiments, the first to third light conversion patterns CCP1 to CCP3 may be configured with different materials. For example, the first light conversion pattern CCP1 may include light-scattering particles and first color conversion particles QD1 for converting blue light into red light. For example, the second light conversion pattern CCP2 may include light-scattering particles and second color conversion particles QD2 for converting blue light into green light. For example, the third light conversion pattern CCP3 may include light-scattering particles SCT. For example, the light-scattering particles SCT may scatter blue light.

[0192] Thus, different colors of light can be emitted from the first to third light conversion patterns CCP1 to CCP3. For example, light of a color obtained by mixing red and blue can be emitted from the first light conversion pattern CCP1. For example, light of a color obtained by mixing green and blue can be emitted from the second light conversion pattern CCP2. For example, blue light can be emitted from the third light conversion pattern CCP3. The different colors of light emitted from the first to third light conversion patterns CCP1 to CCP3 can be emitted as red light, green light, and blue light, respectively, while passing through the first to third color filters CF1 to CF3 of the color filter layer CFL. Therefore, the first to third subpixels SP1 to SP3 can be configured as red subpixels, green subpixels, and blue subpixels, respectively.

[0193] Figure 11 According to the embodiment of the present disclosure Figure 5 A schematic cross-sectional view of a pixel taken along line XX' shown in FIG. Figure 11 , will simplify or omit Figure 6 A description of those overlapping parts shown in .

[0194] refer to Figure 11 , the surface of the second bank BNK2' may have an uneven structure. For example, the side surface of the second bank BNK2' may have an uneven structure. The uneven structure may be formed into various shapes such as a triangular pyramid, a quadrangular pyramid, a trapezoid, and a hemisphere in a cross-sectional view. Similar to the second bank BNK2', the reflective layer RFL' provided on the side surface of the second bank BNK2' may have an uneven structure. The uneven structure may cause diffuse reflection and recycling of the blue light emitted from the first light-emitting element LD1 to the third light-emitting element LD3. Therefore, the emission (or leakage) of the blue light in the first light conversion pattern CCP1 and the second light conversion pattern CCP2 may be reduced, and the light conversion efficiency of the first color conversion particles QD1 and the second color conversion particles QD2 may be improved.

[0195] Figure 11 The uneven structure of the second bank BNK2' and the reflective layer RFL' shown in FIG. Figure 7 、 Figure 8 、 Figure 10 、 Figure 11 and Figure 12 The embodiment shown in .

[0196] Figure 12 According to the embodiment of the present disclosure Figure 5 A schematic cross-sectional view of a pixel taken along line XX' shown in FIG. Figure 12 , will simplify or omit Figure 6 A description of those overlapping parts shown in .

[0197] refer to Figure 12 The light scattering layer SCL' may have a fine pattern configured with light scattering particles SCT. For example, the fine pattern may be formed into various shapes such as a cylinder, a hemisphere, a pyramid, and a quadrilateral column in a cross-sectional view. The fine pattern may have a size suitable for the blue light emitted from the first to third light-emitting elements LD1 to LD3 to be output in a Lambertian form. For example, the size of the fine pattern may be larger than approximately 1 / 4 of the wavelength of the blue light emitted from the first to third light-emitting elements LD1 to LD3, and smaller than the wavelength of the blue light emitted from the first to third light-emitting elements LD1 to LD3. The number of fine patterns formed in the light scattering layer SCL' is not particularly limited.

[0198] The light scattering layer SCL' having a fine pattern can be formed by a nanoimprint process. For example, light scattering particles SCT can be coated on the first capping layer CPL1 in the second opening OP2 and stamped using a mold having a shape corresponding to the fine pattern. The mold may include an ultraviolet curable resin such as polydimethylsiloxane (PDMS). Subsequently, after irradiating ultraviolet light, the mold can be removed, thereby forming a light scattering layer SCL' having a fine pattern. However, the embodiment is not limited thereto.

[0199] Figure 12 The light scattering layer SCL' with fine patterns shown in FIG can be applied to Figure 7 、 Figure 8 、 Figure 10 and Figure 11 The embodiment shown in .

[0200] Figure 13 According to the embodiment of the present disclosure Figure 5 A schematic cross-sectional view of a pixel taken along line XX' shown in FIG. Figure 13 , will simplify or omit Figure 6 A description of those overlapping parts shown in .

[0201] refer to Figure 13A light scattering layer SCL" may be disposed on the cathode CE. The light scattering layer SCL" may have a lattice structure including air gaps AG. The lattice structure may include a base material containing light scattering particles SCT and air gaps AG corresponding to openings filled with air. For example, the air gaps AG may be formed in various shapes such as cylinders, hemispheres, pyramids, and quadrilateral pillars in a cross-sectional view. The air gaps AG may be formed at positions overlapping with the first to third light conversion patterns CCP1 to CCP3 in a plan view. Each of the air gaps AG may have a size suitable for blue light to be output in a Lambertian manner. For example, the size of the air gaps AG may be larger than approximately ¼ of the wavelength of the blue light emitted from the first to third light-emitting elements LD1 to LD3 and smaller than the wavelength of the blue light emitted from the first to third light-emitting elements LD1 to LD3. The number of air gaps AG formed in the light scattering layer SCL" having a lattice structure is not particularly limited. The light scattering layer SCL" having a lattice structure may be formed by the nanoimprint process described above, but embodiments of the present disclosure are not limited thereto.

[0202] Figure 13 The light scattering layer SCL having a lattice structure shown in FIG can be applied to Figure 7 、 Figure 8 、 Figure 10 and Figure 11 The embodiment shown in .

[0203] The first capping layer CPL1 may be disposed on the light scattering layer SCL″. The first capping layer CPL1 may prevent oxygen, moisture, etc. from penetrating into the display panel layer DPL.

[0204] Figure 14 is a schematic block diagram illustrating an embodiment of a display system.

[0205] refer to Figure 14 , the display system 1000 may include a processor 1100 and a display device 1200 .

[0206] The processor 1100 can perform various tasks and various calculations. In an embodiment, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system to control the components of the display system 1000.

[0207] The processor 1100 may send image data IMG and a control signal CTRL to the display device 1200. The display device 1200 may display an image based on the image data IMG and the control signal CTRL. The display device 1200 may be configured to communicate with the reference signal IMG. Figure 1The image data IMG and the control signal CTRL can be set to Figure 1 The input image data IMG and control signal CTRL are shown in FIG.

[0208] The display system 1000 may include a computing system for providing an image display function, such as a smartwatch, a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, a car display, smart glass, a portable multimedia player (PMP), a navigation system, or an ultra-mobile computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0209] Figures 15 to 18 The embodiment according to the present disclosure is shown Figure 14 A perspective view of an application of the display system is shown in FIG.

[0210] refer to Figure 15 , Figure 14 The display system 1000 shown in can be applied to a smart watch 2000 including a display portion 2100 and a band portion 2200 .

[0211] Smartwatch 2000 may be a wearable electronic device. For example, smartwatch 2000 may have a structure in which a band portion 2200 is mounted on a user's wrist. Display system 1000 and / or display device 1200 may be applied to display portion 2100, thereby providing image data including time information to the user.

[0212] refer to Figure 16 , Figure 14 The display system 1000 shown in FIG. 1 may be applied to a car display system 3000. The car display system 3000 may include a computing system provided at the interior / exterior of a vehicle to provide image data.

[0213] For example, the display system 1000 and / or the display device 1200 can be applied to at least one of an infotainment panel 3100, an instrument panel 3200, a co-pilot display 3300, a head-up display 3400, a side-view mirror display 3500, and a rear seat display 3600 provided in a vehicle.

[0214] refer to Figure 17 , Figure 14 The display system 1000 shown in FIG can be applied to smart glasses 4000. The smart glasses 4000 can be a wearable electronic device that can be worn on the user's face. For example, the smart glasses 4000 can be a wearable device for augmented reality (AR).

[0215] Smart glasses 4000 may include a frame 4100 and a lens portion 4200. The frame 4100 may include a housing 4110 supporting the lens portion 4200 and leg portions 4120 for allowing a user to wear the smart glasses 4000. The leg portions 4120 may be connected to the housing 4110 by a hinge so as to be folded or unfolded relative to the housing 4110.

[0216] A battery, a touch panel, a microphone, a camera, and the like may be built into the frame 4100. In an embodiment, a projector for outputting light, a processor for controlling a light signal, and the like may be built into the frame 4100.

[0217] The lens portion 4200 may be an optical member that allows light to be transmitted therethrough or allows light to be reflected therefrom. For example, the lens portion 4200 may include glass, a transparent synthetic resin, or the like.

[0218] In order to enable the user's eyes to recognize visual information, the lens portion 4200 can allow an image caused by the light signal transmitted from the projector of the frame 4100 to be reflected by the rear surface of the lens portion 4200 (e.g., the surface facing the user's eyes). For example, the user can recognize information including time, date, etc. displayed on the lens portion 4200. The projector and / or the lens portion 4200 can be a display device. The display device 1200 can be applied to the projector and / or the lens portion 4200.

[0219] refer to Figure 18 , Figure 14 The display system 1000 shown in FIG. 1 can be applied to a head-mounted display device 5000 .

[0220] The head-mounted display device 5000 may be a wearable electronic device worn on the user's head. For example, the head-mounted display device 5000 may be a wearable device for virtual reality (VR) or mixed reality (MR).

[0221] The head-mounted display device 5000 may include a headband 5100 and a display housing 5200. The headband 5100 may be connected to the display housing 5200. The headband 5100 may include horizontal and / or vertical straps for securing the head-mounted display device 5000 to the user's head. The horizontal straps may be configured to wrap around the sides of the user's head, and the vertical straps may be configured to wrap around the top of the user's head. However, embodiments are not limited thereto. For example, the headband 5100 may be implemented in the form of eyeglass frames, a helmet, or the like.

[0222] The display accommodating housing 5200 may accommodate the display system 1000 and / or the display device 1200 .

[0223] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0224] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are intended to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the scope of equivalents are included in the scope of this disclosure.

Claims

1. A display device, characterized in that include: a pixel circuit layer on the substrate; a light-emitting element on the pixel circuit layer, wherein the light-emitting element is included in the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively; a light scattering layer on the light emitting element; a light conversion pattern on the light scattering layer, the light conversion pattern comprising color conversion particles; and A color filter layer is on the light conversion pattern.

2. The display device according to claim 1, wherein The light emitting element emits blue light.

3. The display device according to claim 2, wherein: The light scattering layer includes light scattering particles that scatter the blue light.

4. The display device according to claim 3, wherein: The light scattering particles have a size in the range of 100 nm to 400 nm.

5. The display device according to claim 3, wherein The light conversion patterns include first, second, and third light conversion patterns, each including first color conversion particles for converting the blue light into red light and second color conversion particles for converting the blue light into green light.

6. The display device according to claim 3, wherein: The light conversion pattern includes: a first light conversion pattern comprising first color conversion particles that convert the blue light into red light; a second light conversion pattern including second color conversion particles that convert the blue light into green light; and The third light conversion pattern includes the light scattering particles.

7. The display device according to claim 1, wherein Also includes: a low-refractive layer on the light-converting pattern; as well as A bank separates the light scattering layer, the light conversion pattern, and the low-refractive layer.

8. The display device according to claim 7, wherein: The surface of the bank has an uneven structure.

9. The display device according to claim 2, wherein: The light scattering layer has a fine pattern.

10. The display device according to claim 2, wherein Also includes: a capping layer disposed between the light scattering layer and the light conversion pattern, and Wherein, the light scattering layer has a lattice structure including air gaps.

Images