Direct current bus voltage sensing circuit

Abstract

The utility model belongs to the technical field of voltage signal sensors, and particularly discloses a direct current bus voltage sensing circuit which comprises an MOS tube Q3 and an MOS tube Q4, the grid electrode of the MOS tube Q4 is connected with a VDCEN port through a resistor R51, a power supply 3.3 V is connected with the grid electrode of the MOS tube Q4 through a resistor R52, the source electrode of the MOS tube Q4 is grounded, a power supply 15V is connected with the drain electrode of the MOS tube Q4 through a resistor R48, the grid electrode of the MOS tube Q3 is connected with the drain electrode of the MOS tube Q4, and the grid electrode of the MOS tube Q3 is connected with the drain electrode of the MOS tube Q4. And the source electrode of the MOS tube Q3 outputs a VDCAD port. According to the utility model, the drain electrode of the MOS tube Q3 is electrified through the power supply voltage VBUS, the MOS tube Q3 is conducted, and the power supply voltage of the power supply voltage VBUS is effectively reduced through the resistance network, so that the power supply voltage is adaptive to the MOS tube Q3, the MOS tube Q3 is convenient to conduct a low-voltage signal, and a rectified voltage signal is convenient to convert into a low-voltage signal realized by the low-cost resistance network.

Description

Technical Field

[0001] The utility model belongs to the technical field of voltage signal sensors, in particular to a DC bus voltage sensing circuit. Background Art

[0002] The voltage signal sensor uses the law of voltage change to measure voltage. According to the characteristics of voltage change, it is used to measure the current, voltage and waveform between each part of the voltage signal, and convert these signals into electrical signals and send them to signal processing.

[0003] When a voltage signal sensor is used to transmit a voltage signal, the voltage signal is transmitted through the voltage signal sensor due to the different voltages in the circuit.

[0004] Therefore, it is necessary to invent a DC bus voltage sensing circuit to solve the above problems. Utility Model Content

[0005] In view of the above problems, the present invention provides a DC bus voltage sensing circuit to solve the problems raised in the above background technology.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a DC bus voltage sensing circuit, comprising a MOS transistor Q3 and a MOS transistor Q4, wherein the gate of the MOS transistor Q4 is connected to the VDC_EN port via a resistor R51, and a 3.3V power supply is connected to the gate of the MOS transistor Q4 via a resistor R52. The source of the MOS transistor Q4 is grounded, and a 15V power supply is connected to the drain of the MOS transistor Q4 via a resistor R48. The gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4, and the source of the MOS transistor Q3 outputs the VDC_AD port.

[0007] Furthermore, the source of the MOS transistor Q3 is grounded via a resistor R53.

[0008] Furthermore, a capacitor C45 is connected in parallel to the resistor R53.

[0009] Furthermore, the MOS transistor Q3 and the MOS transistor Q4 are both configured as N-type MOS transistors.

[0010] Furthermore, the drain of the MOS transistor Q3 is connected to the power supply voltage VBUS through the resistor R47 , the resistor R46 and the resistor R45 .

[0011] Furthermore, the resistance values ​​of the resistor R47 , the resistor R46 and the resistor R45 are the same, and the resistor R47 , the resistor R46 and the resistor R45 form a resistor network.

[0012] Furthermore, the rectified voltage signal is transmitted to the gate of the MOS tube Q4 through the VDC_EN port.

[0013] Technical effects and advantages of this utility model:

[0014] 1. The utility model energizes the drain of the MOS tube Q3 through the power supply voltage VBUS, and the MOS tube Q3 is turned on. The resistor network effectively reduces the power supply voltage of the power supply voltage VBUS, so that the power supply voltage adapts to the MOS tube Q3, facilitates the MOS tube Q3 to conduct low-voltage signals, and facilitates the conversion of the rectified voltage signal into a low-voltage signal realized by the low-cost resistor network. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a DC bus voltage sensing circuit diagram of an embodiment of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments.

[0017] The utility model provides a DC bus voltage sensing circuit, such as Figure 1 As shown, the circuit includes a MOS transistor Q3 and a MOS transistor Q4. The gate of MOS transistor Q4 is connected to the VDC_EN port via a resistor R51, and a 3.3V power supply is connected to the gate of MOS transistor Q4 via a resistor R52. The source of MOS transistor Q4 is grounded, and a 15V power supply is connected to the drain of MOS transistor Q4 via a resistor R48. The gate of MOS transistor Q3 is connected to the drain of MOS transistor Q4, and the source of MOS transistor Q3 outputs the VDC_AD port. The rectified voltage signal is transmitted to the gate of MOS transistor Q4 via the VDC_EN port. The 15V power supply provides energy to MOS transistor Q4 via resistor R48, turning on MOS transistor Q4. The 3.3V power supply is output through the gate of MOS transistor Q4, effectively reducing the supply voltage. The VDC_EN port is used to transmit a control signal to activate or disable the conduction of MOS transistor Q4, making the entire circuit more efficient and secure when transmitting data.

[0018] The source of the MOS transistor Q3 is grounded via a resistor R53. A capacitor C45 is connected in parallel to the resistor R53. Capacitor C45 and resistor R53 protect the source of the MOS transistor Q3, preventing excessive voltage fluctuations at the output of the MOS transistor Q3 and facilitating protection of the MOS transistor Q3.

[0019] The MOS transistor Q3 and the MOS transistor Q4 are both configured as N-type MOS transistors.

[0020] exist Figure 1In the embodiment, the drain of the MOS transistor Q3 is connected to the supply voltage VBUS via resistors R47, R46, and R45. Resistors R47, R46, and R45 have the same resistance value, and the resistors R47, R46, and R45 form a resistor network. The supply voltage VBUS energizes the drain of the MOS transistor Q3 through resistors R45, R46, and R47, turning on the MOS transistor Q3. The resistor network effectively reduces the supply voltage of the supply voltage VBUS, adapting the supply voltage to the MOS transistor Q3, facilitating the MOS transistor Q3 to conduct low-voltage signals and facilitating the conversion of the rectified voltage signal into a low-voltage signal implemented by the low-cost resistor network.

[0021] Working principle of this utility model:

[0022] Reference Figure 1 As shown, the rectified voltage signal is transmitted to the gate of the MOS tube Q4 through the VDC_EN port. The power supply 15V supplies energy to the MOS tube Q4 through the resistor R48, so that the MOS tube Q4 is turned on and the power supply 3.3V is output through the gate of the MOS tube Q4, thereby effectively reducing the supply voltage.

[0023] The supply voltage VBUS energizes the drain of the MOS transistor Q3 through the resistors R45, R46, and R47. The MOS transistor Q3 is turned on, and the resistor network effectively reduces the supply voltage of the supply voltage VBUS, so that the supply voltage adapts to the MOS transistor Q3, making it easier for the MOS transistor Q3 to turn on the low-voltage signal, and conveniently converting the rectified voltage signal into a low-voltage signal implemented by the low-cost resistor network.

[0024] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same.

Claims

1. A DC bus voltage sensing circuit, characterized in that: The circuit includes a MOS transistor Q3 and a MOS transistor Q4. The gate of the MOS transistor Q4 is connected to the VDC_EN port via a resistor R51, and a 3.3V power supply is connected to the gate of the MOS transistor Q4 via a resistor R52. The source of the MOS transistor Q4 is grounded. The 15V power supply is connected to the drain of the MOS transistor Q4 via a resistor R48. The gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4. The source of the MOS transistor Q3 outputs the VDC_AD port.

2. The DC bus voltage sensing circuit according to claim 1, wherein: The source of the MOS transistor Q3 is grounded via a resistor R53.

3. The DC bus voltage sensing circuit according to claim 2, wherein: The resistor R53 is connected in parallel with a capacitor C45 .

4. The DC bus voltage sensing circuit according to claim 1, wherein: The MOS transistor Q3 and the MOS transistor Q4 are both configured as N-type MOS transistors.

5. The DC bus voltage sensing circuit according to claim 1, wherein: The drain of the MOS transistor Q3 is connected to the power supply voltage VBUS through the resistors R47 , R46 and R45 .

6. The DC bus voltage sensing circuit according to claim 5, characterized in that: The resistors R47 , R46 and R45 have the same resistance value, and form a resistor network.

7. The DC bus voltage sensing circuit according to claim 1, wherein: The rectified voltage signal is transmitted to the gate of the MOS tube Q4 through the VDC_EN port.

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