Display device

Abstract

A display device is provided. The display device includes: a first active pattern disposed on a substrate; a first data line disposed on the first active pattern and electrically connected to the first active pattern; a first pixel electrode disposed on the first data line, electrically connected to the first active pattern, at least partially overlapping the first data line in a plan view, and shielding the first data line; and a common electrode disposed on the first pixel electrode.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device for providing visual information. Background Art

[0002] With the development of information technology, the importance of display devices as a medium connecting users and information is becoming increasingly apparent. Consequently, the use of display devices such as liquid crystal displays, organic light-emitting displays, and plasma displays is increasing. For example, a display device may include one or more pixels, each of which includes at least one transistor, at least one capacitor, and at least one light-emitting diode. Utility Model Content

[0003] The embodiment provides a display device with improved display quality.

[0004] The technical objectives to be achieved by the present disclosure are not limited to those described herein, and those skilled in the art will clearly understand other technical objectives not mentioned herein from the description of the present disclosure.

[0005] A display device according to an embodiment of the present disclosure may include: a first active pattern, which is arranged on a substrate; a first data line, which is arranged on the first active pattern and electrically connected to the first active pattern; a first pixel electrode, which is arranged on the first data line, electrically connected to the first active pattern, at least partially overlaps with the first data line in a plan view, and shields the first data line; and a common electrode, which is arranged on the first pixel electrode.

[0006] In an embodiment, the display device may further include: a second active pattern arranged on the substrate; a second data line arranged on the second active pattern, spaced apart from the first data line in the first direction, and electrically connected to the second active pattern; and a second pixel electrode arranged on the second data line, electrically connected to the second active pattern, at least partially overlapping with the second data line in a plan view, and shielding the second data line. The first pixel electrode and the second pixel electrode may be provided in a stripe structure.

[0007] In an embodiment, the first pixel electrode and the second pixel electrode may be arranged in a stripe structure in the first direction.

[0008] In an embodiment, each of the first pixel electrode and the second pixel electrode may have a long width in a second direction intersecting the first direction.

[0009] In an embodiment, the common electrode may be a plate electrode.

[0010] In an embodiment, the first and second data lines may extend in a second direction intersecting the first direction.

[0011] In an embodiment, the display device may further include: a driving voltage line, the driving voltage line electrically connected to the first pixel electrode and the second pixel electrode; a first common voltage line, the first common voltage line electrically connected to the common electrode and extending in the first direction; and a second common voltage line, the second common voltage line electrically connected to the common electrode and extending in the second direction.

[0012] A display device according to another embodiment of the present disclosure may include: a first active pattern, the first active pattern being arranged on a substrate; a first data line, the first data line being arranged on the first active pattern and electrically connected to the first active pattern; a first shielding portion, the first shielding portion being arranged on the first data line, at least partially overlapping with the first data line in a plan view, and shielding the first data line; and a common electrode, the common electrode being arranged on the first shielding portion.

[0013] In an embodiment, the display device may further include: a second active pattern, the second active pattern being arranged on the substrate; a second data line, the second data line being arranged on the second active pattern, spaced apart from the first data line in the first direction, and electrically connected to the second active pattern; and a second shielding portion, the second shielding portion being arranged on the second active pattern, at least partially overlapping with the second data line in a plan view, and shielding the second data line.

[0014] In an embodiment, the display device may further include: a first pixel electrode arranged on the first data line and electrically connected to the first active pattern; and a second pixel electrode arranged on the second data line and electrically connected to the second active pattern. The first pixel electrode and the second pixel electrode may be arranged in a stripe structure.

[0015] In an embodiment, the first pixel electrode and the second pixel electrode may be arranged in a stripe structure in the first direction.

[0016] In an embodiment, each of the first pixel electrode and the second pixel electrode may have a long width in a second direction intersecting the first direction.

[0017] In an embodiment, the first pixel electrode may overlap at least a portion of the first data line in a plan view and shield the first data line.

[0018] In an embodiment, the first data line, the first pixel electrode, the first shielding portion, and the common electrode may overlap with each other.

[0019] In an embodiment, the second pixel electrode may overlap at least a portion of the second data line in a plan view and shield the second data line.

[0020] In an embodiment, the first and second data lines may extend in a second direction intersecting the first direction.

[0021] In an embodiment, the first shielding portion may be disposed under the first pixel electrode in a cross-sectional view.

[0022] In an embodiment, the second shielding portion may be disposed under the second pixel electrode in a cross-sectional view.

[0023] In an embodiment, the display device may further include a pixel defining layer disposed between the first pixel electrode and the second pixel electrode, and the first shielding portion may be disposed on the pixel defining layer.

[0024] In an embodiment, the display device may further include a pixel defining layer disposed between the first pixel electrode and the second pixel electrode, and the second shielding portion may be disposed on the pixel defining layer.

[0025] Therefore, by arranging the pixel electrode between the data line and the common electrode, the data line, the common electrode and the pixel electrode can overlap in a plan view. The pixel electrode can prevent parasitic capacitors from being formed between the common electrode and the data line and can improve problems such as crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification and together with the description, illustrate embodiments of the disclosure.

[0027] Figure 1 is a schematic perspective view showing a display device according to an embodiment of the present disclosure.

[0028] Figure 2 Is used to illustrate Figure 1 Schematic diagram of the display device shown in .

[0029] Figure 3 It is used to describe the Figure 2 Schematic diagram of the equivalent circuit of a pixel in a display device.

[0030] Figure 4 is a schematic cross-sectional view illustrating each pixel of a display device according to an embodiment of the present disclosure.

[0031] Figure 5 yes Figure 2 Schematic enlarged plan view of area A.

[0032] Figure 6Is set in Figure 2 Schematic enlarged plan view of some of the pixels in the display panel.

[0033] Figure 7 is shown along Figure 5 Schematic cross-sectional view of the embodiment taken along line II'.

[0034] Figure 8 is shown along Figure 5 A schematic cross-sectional view of another embodiment taken along line II'.

[0035] Figure 9 is shown along Figure 5 A schematic cross-sectional view of yet another embodiment taken along line II'. DETAILED DESCRIPTION

[0036] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0037] In this specification, a plane may be defined by a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1. Alternatively, the third direction D3 may be a normal direction to the plane. That is, the third direction D3 may be perpendicular to the plane formed by the first direction D1 and the second direction D2.

[0038] When an element is referred to as being "on," "connected to," or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to the other element, or intervening elements or layers may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, no intervening elements or layers may be present. For purposes of this disclosure, the term "connected" may refer to being physically connected, electrically connected, and / or fluidically connected, with or without intervening elements.

[0039] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless expressly defined as such herein.

[0040] Figure 1 is a schematic perspective view showing a display device according to an embodiment of the present disclosure.

[0041] refer to Figure 1, the display device DD may include a display area DA and a peripheral area SA. The display area DA may be surrounded by the peripheral area SA.

[0042] The display area DA may be an area that can display an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area SA may be an area that does not display an image. However, the embodiments of the present disclosure are not limited thereto, and at least a portion of the peripheral area SA may display an image.

[0043] The display area DA can display one or more images IM. A user can receive information from the display device DD through the images IM.

[0044] Figure 2 Is used to illustrate Figure 1 Schematic diagram of the display device shown in .

[0045] refer to Figure 2 , the display device DD may include a display panel PNL, a data driver DIC, data lines DL, a gate driver GIC, gate lines GL, a control part TC, and a power supply part PS.

[0046] One or more pixel areas PA may be located on the display panel PNL. The pixel areas PA may be repeatedly arranged in a matrix in a first direction D1 and / or a second direction D2 in a plan view. For example, the pixel area PA may include a first pixel area PA1 and a second pixel area PA2 spaced apart from the first pixel area PA1 in the first direction D1. Each of the pixel areas PA may be divided into a repeating structure, and does not mean a break in the structure.

[0047] The first pixel PX1 may be arranged in the first pixel area PA1, and the second pixel PX2 may be arranged in the second pixel area PA2. The first pixel PX1 and the second pixel PX2 may be adjacent to each other along the first direction D1. The first pixel PX1 and the second pixel PX2 may emit red light, green light, and blue light, respectively. However, embodiments of the present disclosure are not limited thereto. The first pixel area PA1 and the second pixel area PA2 may emit a combination of red light, green light, and blue light.

[0048] The data driver DIC may be arranged to be spaced apart from the display panel PNL in the second direction D2. The data driver DIC may supply data signals to the data lines DL in response to data control signals provided from the control unit TC. The data lines DL may be arranged to be spaced apart in the first direction D1 and may transmit data signals to the pixels PX1 and PX2.

[0049] The gate driver GIC may be arranged to be spaced apart from the display panel PNL in a direction opposite to the first direction D1. The gate driver GIC may supply a gate signal to the gate line GL in response to a gate control signal provided from the control unit TC. The gate lines GL may be arranged to be spaced apart in a second direction D2 and may transmit gate signals to the pixels PX1 and PX2.

[0050] The power supply portion PS may be arranged to be spaced apart from the display panel PNL in a direction opposite to the second direction D2. The power supply portion PS may supply power voltages to the pixels PX1 and PX2 of the display panel PNL. For example, the power supply portion PS may supply a driving voltage ELVDD and / or a common voltage ELVSS to the pixels PX1 and PX2.

[0051] Figure 3 It is used to describe the Figure 2 Schematic diagram of the equivalent circuit of a pixel in a display device.

[0052] refer to Figure 3 , each of the pixels PX1 and PX2 may include first, second and third transistors T1, T2 and T3, a capacitor CST and a light emitting diode LED.

[0053] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to the second electrode of the capacitor CST. The first electrode of the first transistor T1 may be connected to the second electrode of the third transistor T3. A driving voltage ELVDD may be applied to the second electrode of the first transistor T1.

[0054] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor T2 may be connected to the first gate line GL1. The first electrode of the second transistor T2 may be connected to the gate electrode of the first transistor T1. The second electrode of the second transistor T2 may be connected to the data line DL.

[0055] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor T3 may be connected to the second gate line GL2. The sensing line SSL may be connected to the first electrode of the third transistor T3. The second electrode of the third transistor T3 may be connected to the first electrode of the first transistor T1.

[0056] The capacitor CST may include a first electrode and a second electrode. The first electrode of the capacitor CST may be connected to the second electrode of the third transistor T3. The second electrode of the capacitor CST may be connected to the gate electrode of the first transistor T1.

[0057] The light emitting diode LED may include a first electrode and a second electrode. The first electrode of the light emitting diode LED may be connected to the first electrode of the first transistor T1. The second electrode of the light emitting diode LED may be connected to the common voltage ELVSS.

[0058] Figure 4 is a schematic cross-sectional view illustrating each pixel of a display device according to an embodiment of the present disclosure.

[0059] refer to Figure 1 and Figure 4 The pixel PX may include a substrate SUB, a buffer layer BF, a gate insulating layer GI, a transistor TR, an interlayer insulating layer IL, a connection electrode CNE, a first via layer VIA1, a second via layer VIA2, a light emitting diode LED, a pixel defining layer PDL, and an encapsulation layer ENC.

[0060] The transistor TR may include an active layer (or active pattern) ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting diode LED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0061] The substrate SUB may include, for example, a glass substrate, a metal substrate, a plastic substrate, etc. However, the embodiments of the present disclosure are not limited thereto, and the substrate SUB may be an inorganic layer, an organic layer, or a composite material layer.

[0062] The buffer layer BF may be disposed on the substrate SUB. The buffer layer BF may prevent impurities such as oxygen and moisture from penetrating into the elements located on the upper portion of the substrate SUB. The buffer layer BF may include, for example, an inorganic insulating material. In an embodiment, the buffer layer BF may be completely formed on the substrate SUB. Figure 1 In the display area DA and the peripheral area SA.

[0063] The active layer ACT may be disposed on the buffer layer BF. The active layer ACT may include, for example, an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like. For example, the oxide semiconductor may include at least one oxide selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. The active layer ACT may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0064] The gate insulating layer GI may be disposed on the buffer layer BF. Specifically, the gate insulating layer GI may cover (or overlap) the active layer ACT on the buffer layer BF. The gate insulating layer GI may include an inorganic insulating material. In an embodiment, the gate insulating layer GI may be formed entirely in the display area DA and the peripheral area SA.

[0065] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the channel region of the active layer ACT. The gate electrode GE may include a conductive material such as metal, alloy, conductive metal nitride, conductive metal oxide, or a transparent conductive material. Examples of conductive materials that can be used for the gate electrode GE include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum, alloys containing silver, alloys containing copper, alloys containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), and indium zinc oxide (IZO). These can be used alone or in combination with each other. Alternatively, the gate electrode GE can have a single-layer structure or a multi-layer structure including one or more conductive layers.

[0066] The interlayer insulating layer IL may be disposed on the gate electrode GE. The interlayer insulating layer IL may cover (or overlap) the gate electrode GE on the gate insulating layer GI. The interlayer insulating layer IL may include an inorganic insulating material. In an embodiment, the interlayer insulating layer IL may be completely disposed in the display area DA and the peripheral area SA.

[0067] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer IL. The source electrode SE and the drain electrode DE may be connected to the active layer ACT, respectively. Each of the source electrode SE and the drain electrode DE may include a conductive material.

[0068] The first via layer VIA1 may be disposed on the source electrode SE and the drain electrode DE. The first via layer VIA1 may cover the source electrode SE and the drain electrode DE on the interlayer insulating layer IL. The first via layer VIA1 may include, for example, an organic insulating material. In an embodiment, the first via layer VIA1 may be formed only in the display area DA and a portion of the peripheral area SA adjacent to the display area DA.

[0069] The connection electrode CNE may be disposed on the first via layer VIA1. The connection electrode CNE may transmit a signal from the transistor TR to the light-emitting diode LED. The connection electrode CNE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. However, embodiments of the present disclosure are not limited thereto.

[0070] The second via layer VIA2 may be disposed on the connection electrode CNE. The second via layer VIA2 and the first via layer VIA1 may include substantially the same material.

[0071] The pixel electrode PE may be disposed on the second through-hole layer VIA2. The pixel electrode PE may include a conductive material. The pixel electrode PE may be connected to the drain electrode DE through the connection electrode CNE formed in the first through-hole layer VIA1. Therefore, the pixel electrode PE may be electrically connected to the transistor TR.

[0072] The pixel defining layer PDL may be disposed on the pixel electrode PE. The pixel defining layer PDL may expose at least a portion of the pixel electrode PE. The pixel defining layer PDL may include an inorganic insulating material and / or an organic insulating material.

[0073] The light-emitting layer EL may be disposed on the pixel electrode PE. The light-emitting layer EL may be disposed between pixel-defining layers PDL. Specifically, the light-emitting layer EL may be disposed in an opening defined by the pixel-defining layer PDL. The light-emitting layer EL may include at least one of an organic light-emitting material and quantum dots. However, embodiments of the present disclosure are not limited thereto.

[0074] The common electrode CE may be disposed on the light emitting layer EL. The common electrode CE may also be disposed on the pixel defining layer PDL. The common electrode CE may include a conductive material. For example, the common electrode CE may transmit a common voltage ELVSS (see Figure 3 ).

[0075] In an embodiment, the common electrode CE may be a plate electrode covering (or overlapping) the entire display area DA. For example, the common electrode CE may be an electrode arranged in the first direction D1 and the second direction D2 and electrically connected.

[0076] The encapsulation layer ENC may be arranged on the common electrode CE. The encapsulation layer ENC may include at least one inorganic encapsulation layer and / or at least one organic encapsulation layer. In an embodiment, the inorganic encapsulation layer and the organic encapsulation layer may be arranged alternately.

[0077] For example, the organic encapsulation layer may include a cured polymer such as polyacrylate, epoxy resin, or silicone resin. For example, the inorganic encapsulation layer may include silicon oxide, silicon nitride, silicon carbide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0078] Figure 5 yes Figure 2 Schematic enlarged plan view of area A. Figure 6 Is set in Figure 2 Schematic enlarged plan view of some of the pixels in the display panel. Specifically, Figure 6 is included in Figure 5 Schematic enlarged plan view of a pixel of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the metal wire. For example, Figure 6 It is a plan view specifically showing the arrangement of pixel electrodes, metal wiring, etc.

[0079] refer to Figure 2 、 Figure 5 and Figure 6 , the first pixel electrode PE1 and the second pixel electrode PE2 may be respectively arranged in the first pixel area PA1 and the second pixel area PA2 at intervals in the first direction D1.

[0080] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may have a strip structure in the first direction D1. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may be arranged side by side along the first direction D1. Optionally, the third pixel electrode PE3 may be arranged side by side along the first direction D1. Figure 6 In the case of being arranged as shown in , similar to the first pixel electrode PE1 and the second pixel electrode PE2 , the third pixel electrode PE3 may be provided in a stripe structure in the first direction D1 .

[0081] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may have a rectangular shape. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may have a rectangular shape having a long width in the second direction D2. However, the embodiments of the present disclosure are not limited thereto. The first pixel electrode PE1 and the second pixel electrode PE2 may have various shapes such as a diamond shape or a circle.

[0082] The data line DL may be arranged below each of the first pixel electrode PE1 and the second pixel electrode PE2. For example, the first data line DL1 may be arranged below the first pixel electrode PE1, and the second data line DL2 may be arranged below the second pixel electrode PE2. For example, the first pixel electrode PE1 may overlap with the first data line DL1 in a plan view, and the second pixel electrode PE2 may overlap with the second data line DL2 in a plan view.

[0083] In an embodiment, the first data line DL1 and the second data line DL2 may extend in the second direction D2. For example, the first data line DL1 and the second data line DL2 may extend in a direction in which the pixel electrodes PE1 and PE2 have a long width. However, the embodiments of the present disclosure are not limited thereto.

[0084] In an embodiment, the first pixel electrode PE1 may at least partially overlap the first data line DL1 in a plan view. For example, the first pixel electrode PE1 may be arranged to overlap the first data line DL1 and the common electrode CE (see FIG. 1 ) in a plan view. Figure 4 ) overlaps between the first pixel electrode PE1 and the first data line DL1. Therefore, the first pixel electrode PE1 can prevent a parasitic capacitor from being formed between the first data line DL1 and the common electrode (eg, Figure 4 Between the common electrodes CE).

[0085] In an embodiment, the second pixel electrode PE2 may at least partially overlap the second data line DL2 in a plan view. For example, the second pixel electrode PE2 may be arranged to overlap between the second data line DL2 and the common electrode CE in a plan view, and the second pixel electrode PE2 may shield the second data line DL2. Therefore, the second pixel electrode PE2 may prevent a parasitic capacitor from being formed between the second data line DL2 and the common electrode (e.g., Figure 4 Between the common electrodes CE).

[0086] A first common voltage line DSL1 extending in a first direction D1 and a second common voltage line DSL2 extending in a second direction D2 may be arranged below each of the first pixel electrode PE1 and the second pixel electrode PE2. For example, the first common voltage line DSL1 and the second common voltage line DSL2 may be arranged in a grid structure along the first direction D1 and the second direction D2, respectively. The first common voltage line DSL1 and the second common voltage line DSL2 may be electrically connected. The first common voltage line DSL1 and the second common voltage line DSL2 may be electrically connected to a common electrode (e.g., Figure 4 The common electrode CE in the circuit).

[0087] In an embodiment, the number of first common voltage lines DSL1 may be greater than the number of second common voltage lines DSL2. For example, the first common voltage lines DSL1 and the second common voltage lines DSL2 may be arranged at a ratio of 2: 1. However, the embodiments of the present disclosure are not limited thereto.

[0088] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may be electrically connected to the first common voltage line DSL1 and the second common voltage line DSL2 , and a common voltage (eg, ELVSS) may be applied.

[0089] A driving voltage line DVL extending in the second direction D2 may be further disposed under each of the first pixel electrode PE1 and the second pixel electrode PE2. The driving voltage line DVL may extend in the second direction D2.

[0090] In an embodiment, the first common voltage line DSL1, the second common voltage line DSL2, and the driving voltage line DVL may have a mesh structure. By arranging the first common voltage line DSL1, the second common voltage line DSL2, and the driving voltage line DVL in a mesh structure and increasing the number of first common voltage lines DSL1 to be greater than the number of driving voltage lines DVL, the resistance of the first common voltage line DSL1 can be reduced, and the occurrence of crosstalk can be reduced. For example, the first common voltage line DSL1 and the driving voltage line DVL can be arranged in a ratio of approximately 2:1 or 3:1. However, embodiments of the present disclosure are not limited thereto.

[0091] Figure 7 is shown along Figure 5 For example, Figure 7 shows a view taken along the first direction D1 Figure 5 The cross-sectional view of the first pixel electrode PE1 in the first direction D1 can also be the same as the cross-sectional view of the second pixel electrode PE2 in the first direction D1. Figure 7 The cross-sectional view shown in is the same. Figure 7 The figure mainly shows the first data line DL1 , the first pixel electrode PE1 and the common electrode CE.

[0092] refer to Figure 7 , the first data line DL1 may be disposed in the first via layer VIA1. Specifically, the first data line DL1 may be disposed on the interlayer insulating layer IL. The first via layer VIA1 may be disposed on the interlayer insulating layer IL and may cover the first data line DL1.

[0093] In an embodiment, the first data line DL1 may overlap with the first pixel electrode PE1 in a plan view. Specifically, the first pixel electrode PE1 may be arranged between the first data line DL1 and the common electrode CE in a cross-sectional view. Therefore, a parasitic capacitor may be prevented from being formed between the first data line DL1 and the common electrode CE. For example, since the first data line DL1 and the common electrode CE are shielded by the first pixel electrode PE1, the data signal may be prevented from being distorted by the common voltage ELVSS (see FIG. 1 ). Figure 3 ) between them.

[0094] Figure 8 is shown along Figure 5 A schematic cross-sectional view of another embodiment taken along line II', and Figure 9 is shown along Figure 5 A schematic cross-sectional view of another embodiment of the present invention is taken along line II'. For example, Figure 8 and Figure 9 The cross-sectional view of the first pixel electrode PE1 taken in the first direction D1 is shown. The cross-sectional view of the second pixel electrode PE2 taken in the first direction D1 can also be the same as Figure 8 and Figure 9 Therefore, Figure 8 and Figure 9 The first shielding portion SH1 described in the embodiment may be substantially the same as the second shielding portion obtained when the second pixel electrode PE2 is intercepted in the first direction D1. For example, the shielding portion may include the first shielding portion SH1 and the second shielding portion.

[0095] refer to Figure 8 and Figure 9 , the first pixel PE1 may include a first shielding portion SH1 in a cross-section. The first shielding portion SH1 may be arranged between the first data line DL1 and the common electrode CE in a cross-sectional view. For example, the first shielding portion SH1 may be arranged to overlap the first data line DL1 and / or the common electrode CE in a plan view. For example, the shielding portion may include the first shielding portion SH1 and / or the second shielding portion. The shielding portion may include a metal material and / or an inorganic material.

[0096] In an embodiment, the first shielding portion SH1 may overlap the first data line DL1, the first pixel electrode PE1, and the common electrode CE in a plan view. Similarly, the second shielding portion may overlap the second data line (eg, Figure 5 The second data line DL2 in the second pixel electrode PE2 (see Figure 5 ) overlaps with the common electrode CE.

[0097] In an embodiment, Figure 8 As shown in FIG, the first shielding portion SH1 may be arranged in the second through-hole layer VIA2. Specifically, the first shielding portion SH1 may be arranged on the first through-hole layer VIA1, and the second through-hole layer VIA2 may cover the first shielding portion SH1. That is, each of the first shielding portion SH1 and the second shielding portion may be arranged below the first pixel electrode PE1 and the second pixel electrode PE2. Since the first shielding portion SH1 is arranged in the second through-hole layer VIA2 to shield the first data line DL1 and the common electrode CE, a parasitic capacitor can be prevented from being formed between the first data line DL1 and the common electrode CE.

[0098] In an embodiment, Figure 9As shown in , the first shielding portion SH1 may be arranged on the pixel defining layer PDL. Specifically, in a cross-sectional view, the first shielding portion SH1 may be arranged between the pixel defining layer PDL and the common electrode CE. For example, the first shielding portion SH1 may at least partially overlap with the first data line DL1 and / or the common electrode CE in a plan view. Since the first shielding portion SH1 is arranged on the pixel defining layer PDL to shield the first data line DL1 and the common electrode CE, a parasitic capacitor may be prevented from being formed between the first data line DL1 and the common electrode CE.

[0099] like Figures 1 to 9 As can be seen in FIG, by arranging the pixel electrode PE between the data line DL and the common electrode CE, the data line DL, the common electrode CE, and the pixel electrode PE can overlap in a plan view. The pixel electrode PE can prevent parasitic capacitors from being formed between the common electrode CE and the data line DL, thereby improving problems such as crosstalk.

[0100] The present disclosure can be applied to display devices and electronic devices including display devices. For example, the present disclosure can be applied to high-resolution smartphones, mobile phones, smart tablets, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, laptop computers, etc.

[0101] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0102] The embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure but to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims and should be interpreted as all technical spirits within the equivalent scope are included within the scope of this disclosure.

Claims

1. A display device, characterized in that: include: a first active pattern disposed on a substrate; a first data line disposed on the first active pattern and electrically connected to the first active pattern; a first pixel electrode, the first pixel electrode being arranged on the first data line, being electrically connected to the first active pattern, at least partially overlapping the first data line in a plan view, and shielding the first data line; as well as A common electrode is disposed on the first pixel electrode.

2. The display device according to claim 1, wherein Further including: a second active pattern disposed on the substrate; a second data line disposed on the second active pattern, spaced apart from the first data line in a first direction, and electrically connected to the second active pattern; as well as a second pixel electrode, the second pixel electrode being arranged on the second data line, being electrically connected to the second active pattern, at least partially overlapping the second data line in a plan view, and shielding the second data line, The first pixel electrode and the second pixel electrode are arranged in a stripe structure.

3. The display device according to claim 2, wherein: Further including: a driving voltage line electrically connected to the first pixel electrode and the second pixel electrode; a first common voltage line electrically connected to the common electrode and extending in the first direction; as well as A second common voltage line is electrically connected to the common electrode and extends in a second direction.

4. A display device, characterized in that: include: a first active pattern disposed on a substrate; a first data line disposed on the first active pattern and electrically connected to the first active pattern; a first shielding portion disposed on the first data line, at least partially overlapping the first data line in a plan view, and shielding the first data line; as well as A common electrode is disposed on the first shielding portion.

5. The display device according to claim 4, wherein: Further including: a second active pattern disposed on the substrate; a second data line disposed on the second active pattern, spaced apart from the first data line in a first direction, and electrically connected to the second active pattern; as well as A second shielding portion is disposed on the second active pattern, at least partially overlaps the second data line in a plan view, and shields the second data line.

6. The display device according to claim 5, wherein: Further including: a first pixel electrode disposed on the first data line and electrically connected to the first active pattern; as well as a second pixel electrode disposed on the second data line and electrically connected to the second active pattern, The first pixel electrode and the second pixel electrode are arranged in a stripe structure.

7. The display device according to claim 6, wherein: in, The first pixel electrode overlaps at least a portion of the first data line in a plan view and shields the first data line.

8. The display device according to claim 7, wherein: in, The first data line, the first pixel electrode, the first shielding portion, and the common electrode overlap with each other.

9. The display device according to claim 6, wherein: in, The first shielding portion is disposed below the first pixel electrode in a cross-sectional view.

10. The display device according to claim 6, wherein Further including: a pixel defining layer, the pixel defining layer being arranged between the first pixel electrode and the second pixel electrode, The first shielding portion is arranged on the pixel defining layer.

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