Chip IP architecture for decoding rotary transformer

Abstract

The utility model relates to the technical field of automobile chips, in particular to a chip IP architecture for decoding a rotary transformer, which comprises an excitation generator, an angle conversion mode 0 module and an angle conversion mode 1 module. The excitation generator is used for outputting an excitation PWM signal; the angle conversion mode 0 module and the angle conversion mode 1 module are two kinds of heterogeneous redundancy mode modules and are both used for rotary transformer redundancy decoding to conduct excitation period decoding to update angles, and the angle conversion mode 1 module provides a safety mechanism to conduct safety diagnosis on input signals and decoding angles. According to the architecture, the hardware decoding chip IP is integrated in the MCU of the inverter system for driving the motor, so that decoding chips are reduced, and the cost is saved; meanwhile, compared with soft decoding or other chip decoding IPs, the hardware digital decoding chip IP is internally provided with an AD sampling module, the interface is simple, two paths of redundancy decoding can be applied to the purpose of functional safety, and compensation of angle and current sampling is completed in the IP.

Description

Technical Field

[0001] The utility model relates to the technical field of automobile chips, in particular to a chip IP architecture for rotary transformer decoding. Background Art

[0002] With the rapid growth of new energy vehicles in recent years, resolvers are being used in their motor drive inverter systems to detect the motor rotor position in real time. Current resolver decoding methods include hardware decoding using a decoding chip, which increases costs; soft decoding solutions, which involve excitation output, SDADC or VADC sampling, and software acquisition of the envelope and angle calculation, which increases CPU load; and chip decoding IP, which outputs excitation and obtains SDADC or VADC input signals for analysis and angle output. These methods either require external ADC sampling, resulting in complex interfaces, or only output one angle without redundancy, or fail to account for delay compensation with current sampling. To address these issues, we propose a chip IP architecture for resolver decoding. Utility Model Content

[0003] The purpose of the present invention is to provide a chip IP architecture for resolver decoding to solve the problems raised in the above background technology.

[0004] To achieve the above objectives, the present invention provides the following technical solutions:

[0005] The chip IP architecture for resolver decoding includes an excitation generator, an angle conversion mode 0 module, and an angle conversion mode 1 module.

[0006] The excitation generator is used to output an excitation PWM signal;

[0007] The angle conversion mode 0 module and the angle conversion mode 1 module are two modules of heterogeneous redundant modes, both of which are used for redundant decoding of the rotary transformer to perform excitation cycle decoding and update the angle, and the angle conversion mode 1 module provides a safety mechanism to perform safety diagnosis on the input signal and decoding angle.

[0008] Preferably, the angle conversion mode 0 module includes:

[0009] SDADC is used to sample the excitation recovery differential signal and the resolver feedback differential signal to obtain the excitation recovery differential sampling value and the resolver feedback differential sampling value;

[0010] Excitation phase synchronizer 0 is used to extract the resolver feedback differential sampling value and synchronize the zero-crossing signal 0;

[0011] The input shaper / integrator performs shaping and integration based on the synchronous zero-crossing signal 0 output by the excitation phase synchronizer 0 at multiple sampling points within an excitation cycle to obtain envelope sampling values ​​and output position timestamp trigger 0;

[0012] Input correction module 0, used to correct the amplitude and phase of the resolver envelope sampling value;

[0013] Inverse tangent table lookup module 0 calculates inverse tangent angle 0 based on the corrected resolver feedback sampling value;

[0014] The estimated angle between the arc tangent angle 0 and the PID / integrator output The difference is input into the PID and integrator in sequence as an error reference, and the output observer angle is 0 and the speed is 0;

[0015] Angle compensation module 0 is used to perform delay compensation on observer angle 0 to obtain compensated observer angle 0.

[0016] Preferably, the angle conversion mode 1 module includes:

[0017] SARDADC is used to sample the excitation recovery differential signal and the resolver feedback differential signal to obtain the excitation recovery differential sampling value and the resolver feedback differential sampling value; at the same time, it samples the SARADC core diagnostic reference voltage to diagnose common cause failures of the SARADC sampling core;

[0018] Sampling trigger, used to trigger synchronous sampling of each channel of SARDADC;

[0019] An excitation phase synchronizer 1 is used to extract the resolver feedback differential sampling value and the synchronous zero-crossing signal 1, and simultaneously extract the original excitation zero-crossing signal 1 in the excitation;

[0020] Input the peak and trough selector, obtain the sampling value of the resolver feedback differential sampling value at the peak and trough of the synchronous excitation wave based on the synchronous zero-crossing signal 1 output by the excitation phase synchronizer 1, and output the position timestamp trigger 1; and obtain the sampling value of the excitation recovery differential sampling value at the peak and trough of the original excitation wave based on the original excitation zero-crossing signal 1;

[0021] Input correction module 1, used to correct the amplitude and phase of the resolver feedback differential sampling value;

[0022] The inverse tangent table lookup module 1 calculates the inverse tangent angle 1 based on the corrected resolver feedback differential sampling value;

[0023] The speed calculator triggers 1 based on the position timestamp and calculates the speed;

[0024] Angle compensation module 1 is used to perform delay compensation on arc tangent angle 1 and observer angle 0 to obtain two compensation angles aligned with current sampling time 1, namely compensated arc tangent angle 1 and compensated observer angle 1;

[0025] The fault detection module diagnoses short-circuit faults, amplitude faults, and open-circuit faults of the resolver feedback differential signal input and the excitation differential signal input based on the peak and trough sampling values ​​of the excitation and resolver feedback waves; calculates the square sum of the envelope sampling values ​​and diagnoses amplitude faults; compares the compensation arc tangent angle 1 and the compensation observer angle 1 to diagnose faults of the two redundant decoding angles; diagnoses the synchronous zero-crossing signal 1 and the original excitation zero-crossing signal 1; judges the SARADC core diagnostic reference voltage and diagnoses common cause failures of the SARADC core; and outputs the fault status.

[0026] Compared with the existing technology, the beneficial effects of the present invention are: the chip IP architecture of the rotary transformer decoding, the hardware decoding chip IP is integrated into the MCU of the inverter system for motor drive, reducing the decoding chip and saving costs; at the same time, compared with soft decoding or other chip decoding IP, the hardware digital decoding chip IP of the present invention has a built-in AD sampling module and a simple interface. At the same time, the two-way redundant decoding can be applied to the purpose of functional safety, and the compensation of angle and current sampling is completed within the IP. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is the overall structural diagram of the utility model;

[0028] Figure 2 For this utility model Figure 1 Angle conversion mode 0 module structure diagram;

[0029] Figure 3 For this utility model Figure 2 The structural block diagram of the angle conversion mode 1 module in . DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0031] See also Figure 1 As shown, the utility model provides a technical solution:

[0032] A chip IP architecture for resolver decoding, including an excitation generator, an angle conversion mode 0 module, and an angle conversion mode 1 module;

[0033] The excitation generator is used to output an excitation PWM signal positive Exc_P and a signal negative Exc_N;

[0034] The angle conversion mode 0 module and the angle conversion mode 1 module are two modules with heterogeneous redundancy modes, both of which are used for redundant decoding of the rotary transformer to perform excitation cycle decoding and update angle, and provide a safety mechanism to perform safety diagnosis on the input signal and decoding angle.

[0035] Specifically, such as Figure 2 As shown, the angle conversion mode 0 module includes:

[0036] SDADC is used to sample the excitation recovery differential signals R1 and R2 and the resolver feedback differential signals Sin_P, Sin_N, Cos_P, and Cos_N to obtain the excitation recovery differential sampling value f(t) and the resolver feedback differential sampling value f(t')×Sinθ0 and f(t')×Cosθ0;

[0037] Excite phase synchronizer 0 and extract synchronous zero-crossing signal 0 of the excitation f(t') component in the resolver feedback differential sampling values ​​f(t')×Sinθ0 and f(t')×Cosθ0;

[0038] The input shaper / integrator performs shaping and integration based on the synchronous zero-crossing signal 0 output by the excitation phase synchronizer 0 at multiple sampling points within an excitation cycle to obtain the envelope sampling values ​​Sinθ0 and Cosθ0, and outputs the position timestamp trigger 0;

[0039] Input correction module 0, correct the amplitude and phase of the resolver envelope sampling values ​​Sinθ0 and Cosθ0;

[0040] The inverse tangent table lookup module 0 calculates the inverse tangent angle 0 based on the corrected resolver feedback sampling values ​​Sinθ0 and Cosθ0;

[0041] The estimated angle between the arc tangent angle 0 and the PID / integrator output The difference is input into the PID and integrator in sequence as an error reference, and the output observer angle is 0 and the speed is 0;

[0042] Angle compensation module 0, used to perform delay compensation on observer angle 0 to obtain compensated observer angle 0;

[0043] Specifically, such as Figure 3 As shown, the angle conversion mode 1 module includes:

[0044] SARDADC is used to sample the excitation recovery differential signals R1 and R2 and the resolver feedback differential signals Sin_P, Sin_N, Cos_P, and Cos_N to obtain the excitation recovery differential sampling value f(t) and the resolver feedback differential sampling value f(t')×Sinθ1 and f(t')×Cosθ1; at the same time, it samples the SARADC core diagnostic reference voltage to diagnose common cause failures of the SARADC sampling core;

[0045] Sampling trigger, used to trigger synchronous sampling of each channel of SARDADC, the sampling frequency is configurable;

[0046] An excitation phase synchronizer 1 is used to extract the excitation f(t') component synchronization zero-crossing signal 1 from the resolver feedback differential sampling values ​​f(t')×Sinθ1 and f(t')×Cosθ1, and simultaneously extract the original excitation zero-crossing signal 1 from the excitation f(t);

[0047] Input the peak and trough selector, obtain the sampling values ​​Sinθ1 and Cosθ1 of the resolver feedback differential sampling values ​​f(t')×Sinθ1 and f(t')×Cosθ1 at the peak and trough of the synchronous excitation wave based on the synchronous zero-crossing signal 1 output by the excitation phase synchronizer 1, and output the position timestamp trigger 1; and obtain the sampling value of the excitation recovery differential sampling value f(t) at the peak and trough of the original excitation wave based on the original excitation zero-crossing signal 1;

[0048] Input correction module 1 is used to correct the amplitude and phase of the resolver feedback differential sampling values ​​Sinθ1 and Cosθ1;

[0049] The inverse tangent table lookup module 1 calculates the inverse tangent angle 1 based on the corrected resolver feedback differential sampling values ​​Sinθ1 and Cosθ1;

[0050] The speed calculator triggers 1 according to the position timestamp, calculates the angle difference Δθ and the time difference Δt, and calculates the speed ω through the angle difference Δθ and the time difference Δt;

[0051] Angle compensation 1 module is used to perform delay compensation on the arc tangent angle 1 and the observer angle 0, and obtain two compensation angles aligned with the current sampling time 1, namely the compensated arc tangent angle 1 and the compensated observer angle 1;

[0052] The fault detection module diagnoses short-circuit faults, amplitude faults, and open-circuit faults of the resolver feedback differential signal input and the excitation differential signal input based on the peak and trough sampling values ​​of the excitation and resolver feedback waves; calculates the square sum of Sinθ1 and Cosθ1 and diagnoses amplitude faults; compares the compensated inverse tangent angle 1 and the compensated observer angle 1 to diagnose faults of the two redundant decoding angles; diagnoses the synchronous zero-crossing signal 1 and the original excitation zero-crossing signal 1; judges the SARADC core diagnostic reference voltage and diagnoses common cause failures of the SARADC core; and outputs the fault status, which can be used to make a safe response based on the fault when applied.

[0053] The resolver decoding chip IP architecture of this embodiment features two heterogeneous redundant modes: Angle Conversion Mode 0 and Angle Conversion Mode 1, each with a built-in SDADC and SARADC for sampling the resolver input. Both Angle Conversion Mode 0 and Angle Conversion Mode 1 modules update the angle during the excitation cycle. This architecture, integrated within the MCU of the motor drive inverter system, reduces the number of decoding chips and saves costs. Compared to software decoding or other chip decoding IPs, this hardware digital decoding chip IP features a built-in AD sampling module and a simple interface. Its dual-channel redundant decoding enables functional safety, and compensation between angle and current sampling is implemented within the IP.

[0054] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. The chip IP architecture of the resolver decoding is characterized by: Including excitation generator, angle conversion mode 0 module, angle conversion mode 1 module; The excitation generator is used to output an excitation PWM signal; The angle conversion mode 0 module and the angle conversion mode 1 module are two modules of heterogeneous redundant modes, both of which are used for redundant decoding of the rotary transformer to perform excitation cycle decoding and update the angle, and the angle conversion mode 1 module provides a safety mechanism to perform safety diagnosis on the input signal and decoding angle.

2. The chip IP architecture for resolver decoding according to claim 1, characterized in that: The angle conversion mode 0 module includes: SDADC is used to sample the excitation recovery differential signal and the resolver feedback differential signal to obtain the excitation recovery differential sampling value and the resolver feedback differential sampling value; Excitation phase synchronizer 0 is used to extract the resolver feedback differential sampling value and synchronize the zero-crossing signal 0; The input shaper / integrator performs shaping and integration based on the synchronous zero-crossing signal 0 output by the excitation phase synchronizer 0 at multiple sampling points within an excitation cycle to obtain envelope sampling values ​​and output position timestamp trigger 0; Input correction module 0, used to correct the amplitude and phase of the resolver envelope sampling value; Inverse tangent table lookup module 0 calculates inverse tangent angle 0 based on the corrected resolver feedback sampling value; The estimated angle between the arc tangent angle 0 and the PID / integrator output The difference is input into the PID and integrator in sequence as an error reference, and the output observer angle is 0 and the speed is 0; Angle compensation module 0 is used to perform delay compensation on observer angle 0 to obtain compensated observer angle 0.

3. The chip IP architecture for resolver decoding according to claim 2, characterized in that: The angle conversion mode 1 module includes: SARDADC is used to sample the excitation recovery differential signal and the resolver feedback differential signal to obtain the excitation recovery differential sampling value and the resolver feedback differential sampling value; at the same time, it samples the SARADC core diagnostic reference voltage to diagnose common cause failures of the SARADC sampling core; Sampling trigger, used to trigger synchronous sampling of each channel of SARDADC; An excitation phase synchronizer 1 is used to extract the resolver feedback differential sampling value and the synchronous zero-crossing signal 1, and simultaneously extract the original excitation zero-crossing signal 1 in the excitation; Input the peak and trough selector, obtain the sampling value of the resolver feedback differential sampling value at the peak and trough of the synchronous excitation wave based on the synchronous zero-crossing signal 1 output by the excitation phase synchronizer 1, and output the position timestamp trigger 1; and obtain the sampling value of the excitation recovery differential sampling value at the peak and trough of the original excitation wave based on the original excitation zero-crossing signal 1; Input correction module 1, used to correct the amplitude and phase of the resolver feedback differential sampling value; The inverse tangent table lookup module 1 calculates the inverse tangent angle 1 based on the corrected resolver feedback differential sampling value; The speed calculator triggers 1 based on the position timestamp and calculates the speed; Angle compensation module 1 is used to perform delay compensation on arc tangent angle 1 and observer angle 0 to obtain two compensation angles aligned with current sampling time 1, namely compensated arc tangent angle 1 and compensated observer angle 1; The fault detection module diagnoses short-circuit faults, amplitude faults, and open-circuit faults of the resolver feedback differential signal input and the excitation differential signal input based on the peak and trough sampling values ​​of the excitation and resolver feedback waves; calculates the square sum of the envelope sampling values ​​and diagnoses amplitude faults; compares the compensation arc tangent angle 1 and the compensation observer angle 1 to diagnose faults of the two redundant decoding angles; diagnoses the synchronous zero-crossing signal 1 and the original excitation zero-crossing signal 1; judges the SARADC core diagnostic reference voltage and diagnoses common cause failures of the SARADC core; and outputs the fault status.

Images