Semiconductor packaging structure

Abstract

Some embodiments of the present application provide a semiconductor package structure including: a circuit structure including a passivation layer and a moisture barrier layer covering the passivation layer; a first electronic component disposed over the circuit structure; and an underfill disposed between the first electronic component and the moisture barrier layer, in which an adhesion between the moisture barrier layer and the underfill is greater than an adhesion between the passivation layer and the underfill. The moisture barrier layer is used for blocking moisture permeation, so that the moisture diffusion degree can be greatly reduced by more than 80%.

Description

Technical Field

[0001] The present application relates to the technical field of power devices, and more specifically, to a semiconductor packaging structure. Background Art

[0002] In silicon photonics (SiPH) packaging structures, reliability tests failed due to moisture. The failure mode was primarily due to excessive moisture absorption during pre-conditioning testing at MSL3 (Moisture Sensitivity Level 3) (30°C / 60% RH / 192 hours). This resulted in a rapid temperature increase to 260°C (over 100°C above the boiling point of water) during the three subsequent reflow cycles. This prevented moisture / water vapor from escaping quickly within the package structure, causing the PA (polyamide) / PI (polyimide) layers to popcorn.

[0003] Specifically, see Figures 1A to 1I , Figure 1A A perspective view of the silicon photonic packaging structure 10 is shown. Figure 1A As can be seen in FIG, an interconnection structure 102 is formed on the substrate 101, and a die 103 such as a PIC (Photonic Integrated Circuit Die) is bonded to the interconnection structure 102 in a manner surrounding the switch 12, thereby being attached to the substrate 101. In addition, Figure 1B The heat sink 11 is shown above the tube core 103, and Figure 1C The die 103 is shown disposed around the switch 12. Further, Figure 1D Shown along Figure 1A A cross-sectional view of section AA, and Figure 1E Shown Figure 1D An enlarged view of region A of the silicon photonic package structure 10. Figure 1D and Figure 1E As can be seen in FIG, the tube core 103 is attached to the substrate 101 through the interconnection structure 102, and a tube core 105 such as an EIC (electronic integrated circuit tube core) is embedded between the substrate 101 and the interconnection structure 102, which is connected to the interconnection structure 102 through the through hole 104 above it, and the tube core 105 is surrounded by a conductive column 107 and sealed by a sealant 106 such as a molding compound. Further, the tube core 103 is bonded to the interconnection structure 102 through a bump 108 and an underfill 109 surrounding the bump 108. Figures 1D to 1E In the structure shown, a large area of ​​the top of the interconnect structure 102 is exposed to the passivation layer 102s, such as a PA or PI layer, which causes a serious moisture absorption problem and thus leads to failure in related reliability tests. Figure 1F and Figure 1G Shown Figure 1E The scanned image of the portion of the silicon photonic package structure 10 is shown. Figure 1F and Figure 1G As can be seen in the figure, in the pre-conditioning test, under MSL3 (30°C / 60% RH / 192hr) conditions, due to excessive moisture absorption, the temperature was rapidly raised to 260°C (exceeding the boiling point of water by more than 100°C) during the subsequent three reflows, resulting in the water vapor / water vapor in the middle of the packaging structure not having time to dissipate. As a result, the water vapor escaped into the silicon photonic packaging structure 10, causing the interface strength of the passivation layer 102S on the top of the PA / PI to deteriorate, thereby causing the passivation layer 102S on the top of the PA / PI to popcorn. In addition, Figure 1H and Figure 1I The figure shows a formation process of the existing interconnect structure 102, that is, a redistribution layer (redistribution layer) RDL3 is formed on the PI 3 layer (third PI layer) formed by PI, and then a PI 4 layer is formed on the RDL3, that is, the last layer on the top is PI material, so that the top passivation layer 102s, thereby causing the top passivation layer 102S such as PA / PI to popcorn.

[0004] In summary, currently there is no special measure to isolate the exposed portion of the passivation layer 102s on the top of PA / PI from moisture, and therefore, technology to prevent moisture penetration needs to be considered. Utility Model Content

[0005] In order to overcome the above defects, the present application utilizes a moisture barrier layer to prevent moisture penetration.

[0006] Some embodiments of the present application provide a semiconductor packaging structure, comprising: a circuit structure, including a passivation layer and a moisture barrier layer covering the passivation layer; a first electronic component, arranged above the circuit structure; and a bottom filler, arranged between the first electronic component and the moisture barrier layer, wherein the adhesion between the moisture barrier layer and the bottom filler is greater than the adhesion between the passivation layer and the bottom filler.

[0007] In some embodiments, the moisture barrier layer is connected to and in direct contact with the passivation layer.

[0008] In some embodiments, the first electronic component is connected to the moisture barrier layer via solder bumps.

[0009] In some embodiments, the solder bumps extend through and are sealed by the underfill.

[0010] In some embodiments, the moisture barrier layer defines a receiving space for accommodating the solder bump.

[0011] In some embodiments, the solder bump extends into the accommodating space.

[0012] In some embodiments, the circuit structure further includes:

[0013] a redistribution layer, disposed between the moisture barrier layer and the passivation layer,

[0014] Wherein, the redistribution layer directly contacts the moisture barrier layer.

[0015] In some embodiments, a portion of an upper surface of the moisture barrier layer is exposed through the first electronic component.

[0016] In some embodiments, the moisture barrier layer and the first electronic component are laterally offset in a direction in which the moisture barrier layer and the first electronic component are stacked.

[0017] In some embodiments, the thickness of the moisture barrier layer is greater than 30 nm.

[0018] In some embodiments, the semiconductor package structure further includes:

[0019] a second electronic component; and

[0020] a sealing layer covering the second electronic component,

[0021] The second electronic component is separated from the first electronic component by the moisture barrier layer.

[0022] In some embodiments, the circuit structure further includes a redistribution layer between the moisture barrier layer and the passivation layer.

[0023] Wherein, the second electronic component is electrically connected to the first electronic component through the redistribution layer.

[0024] In some embodiments, the first electronic component comprises a photonic integrated circuit for connecting to an optical component.

[0025] In some embodiments, the second electronic component comprises an electronic integrated circuit.

[0026] In some embodiments, the device further includes a first conductive column disposed around the second electronic component and a second conductive column disposed above the second electronic component.

[0027] The bottom of the first conductive column extends below the bottom of the second conductive column.

[0028] In some embodiments, the first conductive pillar extends through the sealing layer.

[0029] In some embodiments, a top surface of the first conductive pillar is flush with a top surface of the second conductive pillar.

[0030] Some other embodiments of the present application provide a semiconductor package structure, characterized by comprising:

[0031] substrate;

[0032] a first electronic component disposed above the substrate; and

[0033] a second electronic component disposed between the substrate and the first electronic component and separated from the first electronic component by a circuit structure and an underfill disposed above the circuit structure;

[0034] The circuit structure includes a passivation layer and a moisture barrier layer covering the passivation layer, and the adhesion between the moisture barrier layer and the underfill is greater than the adhesion between the passivation layer and the underfill.

[0035] In some embodiments, the moisture barrier layer is connected to and in direct contact with the passivation layer.

[0036] In some embodiments, the circuit structure further includes:

[0037] a redistribution layer, disposed between the moisture barrier layer and the passivation layer,

[0038] Wherein, the redistribution layer directly contacts the moisture barrier layer.

[0039] The present application uses a moisture barrier layer to block water vapor penetration, thereby significantly reducing the degree of water vapor diffusion by more than 80%. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figures 1A to 1I The figure shows a silicon photonic packaging structure in the prior art.

[0042] Figure 2 、 Figures 2A to 2B The semiconductor package structure of some embodiments of the present application is shown.

[0043] Figures 3A to 5B The performance test results of the semiconductor package structures of some embodiments of the present application are shown.

[0044] Figures 6A to 6B as well as 7A to 7C The process flow of the semiconductor packaging structure of the present application is shown. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field fall within the scope of protection of this application. In addition, when "approximately", "about", "substantial", "basic" and the like are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0046] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0047] The present application utilizes a moisture barrier layer to block moisture penetration. Specifically, the last top passivation layer can be changed into a moisture barrier layer, or a moisture barrier layer can be added on the last top passivation layer. Figures 2 to 2B , Figure 2 A semiconductor package structure 200 according to some embodiments of the present application is shown. The semiconductor package structure 200 includes: a circuit structure 202 including a passivation layer 202s and a moisture barrier layer 202r covering the passivation layer 202s; a first electronic component 203 disposed above the circuit structure 202; and an underfill 209 disposed between the first electronic component 203 and the moisture barrier layer 202r. In the present application, the adhesion between the moisture barrier layer 202r and the underfill 209 is greater than the adhesion between the passivation layer 202s and the underfill 209, thereby improving the connection strength between the first electronic component 203 and the circuit structure 202.

[0048] from Figure 2AAs can be seen in FIG, the moisture barrier layer 202r replaces the previous top passivation layer 202s and is directly disposed on the redistribution layer 202RDL. Figure 2A In the embodiment shown, the last top passivation layer 202s is changed to a moisture barrier layer 202r. Figure 2B It can be seen from FIG that the moisture barrier layer 202r is disposed on the last top passivation layer 202s, that is, the moisture barrier layer 202r is added on the last top passivation layer 202s. Figure 2B In the illustrated embodiment, the moisture barrier layer 202r is connected to and in direct contact with the passivation layer 202s.

[0049] Back reference Figure 2 , the first electronic component 203 is connected to the moisture barrier layer 202r via a solder bump 208, and the solder bump 208 extends through the bottom filler 209 and is sealed by the bottom filler 209. In some embodiments, the moisture barrier layer 202r defines a receiving space 208v for accommodating the solder bump 208, and the solder bump 208 extends into the receiving space 208v. In some other embodiments, the solder bump 208 extends into the receiving space 208v and further contacts the metal line or pad 202rp in the moisture barrier layer 202r. Further, see Figure 2A and Figure 2B The circuit structure further includes a redistribution layer (RDL) 202RDL between the moisture barrier layer 202r and the passivation layer 202s. In a further embodiment, the RDL 202RDL directly contacts the moisture barrier layer 202r.

[0050] Continue to refer to Figure 2 ,from Figure 2 As can be seen from FIG, a portion of the upper surface 202rs of the moisture barrier layer 202r is exposed through the first electronic component 203. Further, in the stacking direction D of the moisture barrier layer 202r and the first electronic component 203, the moisture barrier layer 202r and the first electronic component 203 are laterally offset, as shown in FIG. Figure 2 As shown, a portion of the first electronic component 203 is suspended above the moisture barrier layer 202r, and as described above, a portion of the upper surface 202rs of the moisture barrier layer 202r is exposed through the first electronic component 203. In some specific embodiments, the thickness of the moisture barrier layer 202r is greater than 30 nm, and further, can be in the range of 30 nm to 150 nm, and the thickness of the passivation layer 202s is in the range of 7 μm to 10 μm. In some embodiments, the thickness of the moisture barrier layer 202r is less than the thickness of the redistribution layer 202RDL.

[0051] In addition, see Figure 2The semiconductor package structure 200 further includes: a second electronic component 205; and a sealing layer 206 covering the second electronic component 205, wherein the second electronic component 205 is separated from the first electronic component 203 by the moisture barrier layer 202r. As described above, the circuit structure 202 includes a redistribution layer 202RDL between the moisture barrier layer 202r and the passivation layer 202s, and the second electronic component 205 is electrically connected to the first electronic component 203 through the redistribution layer 202RDL. In some embodiments, the semiconductor package structure 200 further includes a first conductive pillar 207 disposed around the second electronic component 205, and a second conductive pillar 204 disposed above the second electronic component 205, as shown in FIG. Figure 2 As shown, the bottom 207d of the first conductive pillar 207 extends below the bottom 204d of the second conductive pillar 204. In addition, the first conductive pillar 207 extends through the sealing layer 206, and the top surface 207t of the first conductive pillar 207 is flush with the top surface 204t of the second conductive pillar 204. In some embodiments, as Figure 2 As shown, the second electronic component 205 is disposed on the redistribution layer (RDL) 201 .

[0052] In some specific embodiments, the first electronic component 203 includes a photonic integrated circuit (PIC) for connecting optical components. The second electronic component includes an electronic integrated circuit (EIC). In some embodiments, the moisture barrier layer 202r is mainly composed of a low water vapor permeability material, including but not limited to SiOx or SiNx. In some embodiments, the sealing layer 206 includes a compound such as a molding compound. In some embodiments, the passivation layer 202s may include but not limited to PA, PI, etc. The redistribution layer 202RDL has corresponding dielectric layers and metal lines such as copper embedded in the corresponding dielectric layers. In some other embodiments, the redistribution layer 202RDL can be made of a metal such as copper. In some embodiments, the metal lines or pads 202rp, the first conductive pillars 207, and the second conductive pillars 204 may include but not limited to metals or metal alloys such as copper, silver, and gold.

[0053] See also Figures 2 to 2BOther embodiments of the present application further provide a semiconductor package structure 200, the semiconductor package structure 200 comprising: a substrate (a redistribution layer 201 is disposed on the substrate); a first electronic component 203 disposed above the substrate; and a second electronic component 205 disposed between the substrate and the first electronic component 203 and separated from the first electronic component 203 by a circuit structure 202 and an underfill 209 disposed above the circuit structure 202. In some embodiments, the circuit structure comprises a passivation layer 202s and a moisture barrier layer 202r covering the passivation layer 202s, wherein the adhesion between the moisture barrier layer 202r and the underfill 209 is greater than the adhesion between the passivation layer 202s and the underfill 209. In some embodiments, see Figure 2B , the moisture barrier layer 202r is connected to the passivation layer 202s and is in direct contact with the passivation layer 202s. Figure 2A The circuit structure 202 further includes a redistribution layer 202RDL disposed between the moisture barrier layer 202r and the passivation layer 202s, wherein the redistribution layer 202RDL directly contacts the moisture barrier layer 202r.

[0054] The moisture resistance of the moisture barrier layer 202r when it is SiOx or SiNx is measured below. Specifically, the moisture resistance of the moisture barrier layer 202r provided on the passivation layer 202s of a PC (polycarbonate) substrate (PC Sub) is measured. The measurement results are shown in FIG. Figure 3A and Figure 3B .

[0055] Figure 3A The water vapor transmission rate (WVTR) and oxygen transmission rate (OTR) when the moisture barrier layer 202r is SiOx are shown. Figure 3A It can be seen that when the thickness of SiOx is greater than 120nm, its WVTR can reach 10 -4 ~10 -6 g / m 2 / day level.

[0056] Figure 3B The water vapor transmission rate (WVTR) and oxygen transmission rate (OTR) when the moisture barrier layer 202r is SiNx are shown. Figure 3A It can be seen that when the thickness of SiOx is greater than 30nm, its WVTR can reach 10 -4 ~10 -6g / m 2 / day level.

[0057] It should be noted that graphene-related materials fall around 10 -3 g / m 2 It can be seen that the moisture barrier layer 202r provided in the present application provides a lower water vapor permeability rate (WVTR) when SiOx or SiNx is used, with SiNx being the best choice and being operable on a machine.

[0058] See also Figures 4A to 5B , taking MSL3 (30℃ / 60%RH / 192hr) as an example, Figures 4A to 4B The following diagram shows that without the moisture barrier layer 202r, a large area of ​​the top passivation layer 102s is exposed (such as PI is directly exposed to the environment). Figure 1A The water vapor permeability of the silicon photonic packaging structure 10 shown in FIG. 1 is shown in FIG. 1 . Figure 4A The passivation layer 102s is shown exposed. Figure 1A The initial water vapor permeation of the silicon photonic package structure 10 is shown, and Figure 4B The passivation layer 102s is shown exposed. Figure 1A The silicon photonic package structure 10 is subjected to a 192-hour water vapor permeation test for comparative purposes. Figure 4A and Figure 4B It can be seen from the figure that the water vapor will penetrate into the interior of the silicon photonic packaging structure 10 within 192 hours.

[0059] Figures 5A to 5B FIG. 2 shows the water vapor permeation of the semiconductor package structure 200 in the case where the top passivation layer 202s is covered by the moisture barrier layer 202r of the present application. It should be noted that Figure 5A FIG. 2 shows the initial water vapor permeation of the semiconductor package structure 200 when the top passivation layer 202s is covered by the moisture barrier layer 202r, and FIG. Figure 5B The water vapor permeation of the semiconductor package structure 200 with the top passivation layer 202s covered by the moisture barrier layer 202r after 192 hours is shown for comparison. Figure 5A and Figure 5B It can be seen that when the top passivation layer 202s is covered by a moisture barrier layer 202r made of a low moisture permeability barrier material, such as SiNx, moisture remains close to zero even after 192 hours, significantly reducing moisture diffusion by over 80%. Therefore, in this application, the moisture permeation performance is demonstrated through a 192-hour control experiment to demonstrate that when the top passivation layer 202s is covered by the moisture barrier layer 202r, moisture permeation of the semiconductor package structure 200 can be significantly reduced.

[0060] In summary, the present application uses the moisture barrier layer 202r to prevent water vapor from penetrating into the passivation layer 202s such as PA / PI, thereby significantly reducing the degree of water vapor diffusion by more than 80%.

[0061] Figures 6A to 6B as well as 7A to 7C The process of forming the circuit structure 202 with the moisture barrier layer 202 r of the present application is shown.

[0062] See also Figures 6A to 6B After forming a redistribution layer 202RDL on the passivation layer 202s such as PI by a method commonly used in the art, a moisture barrier layer 202r is directly formed on the redistribution layer 202RDL.

[0063] See also 7A to 7C After forming a passivation layer 202s on the redistribution layer 202RDL, a moisture barrier layer 202r is formed on the passivation layer 202s.

[0064] In summary, if Figures 6A to 6B Finally, a moisture barrier layer 202r is formed to replace the passivation layer 202s, as shown in FIG. 7A to 7B , adding a moisture barrier layer 202r on the passivation layer 202s, can be done using a limited machine. Then, the first electronic component 203 is attached and the bottom filler 209 is formed by the common methods in the art. Figure 2 A semiconductor package structure 200 is shown.

[0065] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: A circuit structure comprising a passivation layer and a moisture barrier layer covering the passivation layer; a first electronic component, disposed above the circuit structure; as well as a bottom filler disposed between the first electronic component and the moisture barrier layer, The adhesion between the moisture barrier layer and the bottom filler is greater than the adhesion between the passivation layer and the bottom filler.

2. The semiconductor package structure according to claim 1, wherein: The moisture barrier layer is connected to the passivation layer and is in direct contact with the passivation layer.

3. The semiconductor package structure according to claim 1, wherein: The first electronic component is connected to the moisture barrier layer through solder bumps, and the solder bumps extend through and are sealed by the underfill.

4. The semiconductor package structure according to claim 3, wherein: The moisture barrier layer defines an accommodating space for accommodating the solder bump, and the solder bump extends into the accommodating space.

5. The semiconductor package structure according to claim 1, wherein: The circuit structure further includes: a redistribution layer, disposed between the moisture barrier layer and the passivation layer, Wherein, the redistribution layer directly contacts the moisture barrier layer.

6. The semiconductor package structure according to claim 1, wherein: The thickness of the moisture barrier layer is greater than 30 nm.

7. The semiconductor package structure according to claim 1, wherein: Also includes: a second electronic component; as well as a sealing layer covering the second electronic component, The second electronic component is separated from the first electronic component by the moisture barrier layer.

8. The semiconductor package structure according to claim 7, wherein: The circuit structure further includes a redistribution layer between the moisture barrier layer and the passivation layer, Wherein, the second electronic component is electrically connected to the first electronic component through the redistribution layer.

9. The semiconductor package structure according to claim 1, wherein: The first electronic component includes a photonic integrated circuit for connecting to an optical component.

10. The semiconductor package structure according to claim 7, wherein: The device further includes a first conductive column disposed around the second electronic component and a second conductive column disposed above the second electronic component. Wherein, a bottom portion of the first conductive pillar extends below a bottom portion of the second conductive pillar, and wherein the first conductive pillar extends through the sealing layer.

Images