Package structure

Abstract

Some embodiments of the present application provide a package structure comprising: an upper wafer; feeding a wafer; the connecting structure is arranged between the upper wafer and the lower wafer and is used for connecting the upper wafer and the lower wafer, the connecting structure comprises an optical channel and an electric channel, the electric channel covers the optical channel, the optical channel of the connecting structure comprises a first part and a second part, and in a top view, the first part and the second part are connected. A vertical projection range of the first portion is different from a vertical projection range of the second portion. According to the invention, the connection structure comprising the optical channel and the electric channel is utilized to realize the transmission of photoelectric signals at the same time, and a redistribution layer does not need to be used. Specifically, the optical channel is used as one of optical signal transmission structures, so that the step of converting optical signals into electric signals is reduced, a redistribution layer process is not needed, the reject ratio of the packaging structure is further reduced, and the yield of the corresponding packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the technical field of power devices, and more specifically, to a packaging structure. Background Art

[0002] In existing technologies for silicon photonics (SiPh) applications, optical sensors must be used to convert transmission from optical signals to electrical signals, requiring a redistribution layer (RDL). The RDL layer is expensive to manufacture and has a complex structure. Specifically, Figure 1 As shown, for the current silicon photonics (SiPh) packaging structure 10, the conversion of optical signals into electrical signals must pass through the optical sensor conversion 16 and then be transmitted through the redistribution (RDL) layer 20, that is, a redistribution layer 20 is set between the photon pad 15 set in the wafer / chip 11 and the photon pad 15' set in the wafer / chip 11'. The redistribution layer 20 is provided with dielectric layers 12 and 12' and dielectric layers 13 and 13', an adhesive layer 14 and an adhesive layer 14 that connects the dielectric layers 13 and 13' in the redistribution layer 20, wherein conductive pads / vias 17 are provided in the dielectric layers 12 and 12' and the dielectric layers 13 and 13'.

[0003] Therefore, there are high costs, affected yields and long C / T (dielectric / transmission) in the process. In addition, the redistribution (RDL) layer 20 has higher power consumption and higher resistance. It can be seen that the manufacturing process of the redistribution (RDL) layer 20 is complex, low yield and low yield, which makes its cost high. Therefore, a connection structure that can transmit optical and electrical signals at the same time is needed. However, to date, there is no suitable technology to provide direct optical transmission interconnection between the two terminals (photonic pads 15 and 15'). Therefore, there is an urgent need to create a direct waveguide bump bonding technology to achieve a faster communication solution that combines waveguides and electrical interconnections. Utility Model Content

[0004] To overcome these shortcomings, a connection structure that can simultaneously transmit optical and electrical signals is needed. This application utilizes waveguide bumps (waveguide material) for top and bottom bonding, and a metal wall structure surrounding the bumps. This structure can simultaneously transmit optical and electrical signals without the need for a redistribution layer.

[0005] Some embodiments of the present application provide a packaging structure, comprising: an upper chip; a lower chip; a connecting structure, located between the upper chip and the lower chip and connecting the upper chip and the lower chip, wherein the connecting structure comprises an optical channel and an electrical channel, and the electrical channel covers the optical channel, and wherein the optical channel of the connecting structure comprises a first part and a second part, wherein, in a top view, a vertical projection range of the first part is different from a vertical projection range of the second part.

[0006] In some embodiments, the optical channel of the connecting structure includes a first portion and a second portion, wherein, in a top view, a vertical projection range of the first portion is larger than a vertical projection range of the second portion.

[0007] In some embodiments, the sidewalls of the connecting structure form a stepped structure.

[0008] In some embodiments, the upper wafer has a first optical terminal, and the lower wafer has a second optical terminal, wherein the first optical terminal and the second optical terminal are connected to each other through the optical channel of the connection structure.

[0009] In some embodiments, a gap exists at the interface between the first portion and the second portion.

[0010] In some embodiments, the package structure further includes: a seed layer disposed at an interface between the first portion and the electrical channel and at an interface between the second portion and the electrical channel.

[0011] In some embodiments, a top surface of the second portion contacts the electrical via.

[0012] In some embodiments, a bottom surface of the first portion contacts the electrical via.

[0013] In some embodiments, the packaging structure further includes: a bottom filling layer filled between the upper chip and the lower chip.

[0014] In some embodiments, the underfill layer is spaced apart from the light channel.

[0015] In some embodiments, the seed layer is further disposed at an interface between the upper wafer and the connection structure and an interface between the lower wafer and the connection structure.

[0016] In some embodiments, the electrical channel includes a first electrical channel covering the first portion and a second electrical channel covering the second portion, wherein the first electrical channel and the second electrical channel have the same shape.

[0017] In some embodiments, the electrical channel includes a first electrical channel covering the first portion and a second electrical channel covering the second portion, wherein the first electrical channel and the second electrical channel have different shapes.

[0018] In some embodiments, a single first optical terminal is connected to a plurality of the connection structures, wherein the electrical channels of the plurality of connection structures cover the optical channels, and the electrical channels and the optical channels are alternately arranged.

[0019] In some embodiments, a single first optical terminal is connected to a plurality of second optical terminals via a plurality of the connection structures.

[0020] In some embodiments, the optical channel of the connecting structure includes a first part, a second part, and a third part between the first part and the second part, wherein, in a top view, the vertical projection range of the first part is the same as the vertical projection range of the second part, and different from the vertical projection range of the third part.

[0021] Other embodiments of the present application provide a packaging structure, comprising: a lower chip; a connecting structure arranged above the lower chip; and an upper chip arranged above the connecting structure, wherein the connecting structure is provided with an optical channel and an electrical channel surrounding the optical channel, the lower chip is electrically and optically connected to the upper chip through the connecting structure, and wherein the sidewalls of the connecting structure form a stepped structure.

[0022] In some embodiments, the optical channel of the connecting structure includes a first portion and a second portion, wherein, in a top view, a vertical projection range of the first portion is different from a vertical projection range of the second portion.

[0023] In some embodiments, the package structure further includes: a seed layer disposed at an interface between the first portion and the electrical channel and at an interface between the second portion and the electrical channel.

[0024] The present application utilizes a connection structure including an optical channel and an electrical channel to simultaneously realize the transmission of optical and electrical signals without the need for a redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 The figure shows a packaging structure in the prior art.

[0027] Figure 2 、 Figures 2A to 2D 、 Figures 3 to 9 and FIG. 10A to FIG. 10B The package structure according to some embodiments of the present application is shown.

[0028] Figures 11 to 23 The process flow of the packaging structure of the present application according to some embodiments is shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field fall within the scope of protection of this application. In addition, when "approximately", "about", "substantial", "basic" and the like are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0030] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0031] The present application provides a shortest optical path application for SiPh packages through waveguide bump bonding, which provides a good performance design.

[0032] Some embodiments of the present application provide a packaging structure 100, referring to Figure 2 The packaging structure 100 includes: an upper chip 101; a lower chip 102; a connecting structure 103, which is located between the upper chip 101 and the lower chip 102 and connects the upper chip 101 and the lower chip 102. Figure 2 As can be seen in FIG, the connection structure 103 includes an optical channel 103A (waveguide bump) and an electrical channel 103B (reflection ring / metal structure / metal ring / metal wall), and see Figure 2A shown Figure 2 The top view of the connection structure 103 at the left area L of the package structure 100 is shown in FIG. 1 . From the top view, it can be seen that the electrical channel 103B covers the optical channel 103A. Further, the optical channel 103A of the connection structure 103 includes a first portion 103A1 and a second portion 103A2, and Figure 2 The package structure 100 and Figure 2AIn the top view shown, the vertical projection range S1 of the first portion 103A1 is different from the vertical projection range S2 of the second portion 103A2. Figure 2 The left area L of the package structure 100 shown in FIG. Figure 2A In the top view shown, the vertical projection range S1 of the first portion 103A1 is larger than the vertical projection range S2 of the second portion 103A2. In this case, the bottom surface 103A1d of the first portion 103A1 contacts the electrical channel 103B. However, in some other embodiments, such as Figure 2 In the right region R of the package structure 100 shown, the vertical projection range S1 of the first portion 103A1 is smaller than the vertical projection range S2 of the second portion 103A2. In this case, the top surface 103A2t of the second portion 103A2 contacts the electrical channel 103B. This can be set according to actual conditions. Figure 3 , Figure 3 FIG. 2 shows a package structure 200 according to some other embodiments of the present application. Figure 3 The package structure 200 shown is Figure 2 The package structure 100 is similar to the package structure 100 shown in FIG. 1 , but the difference is that, as can be seen from the package structure 200, in the connection structure 103 of the package structure 200, the vertical projection range S1 of the first portion 103A1 is smaller than the vertical projection range S2 of the second portion 103A2, that is, the first portion 103A1 and the second portion 103A2 are Figure 3 The cross-sectional views shown have different sizes, and the sizes of the first portion 103A1 to the second portion 103A2 are from large to small. Figure 4 In the packaging structure 300 shown, in the connection structure 103 of the packaging structure 300, the vertical projection range S1 of the first part 103A1 is equal to the vertical projection range S2 of the second part 103A2, that is, the first part 103A1 of the optical channel 103A and the second part 103A2 of the optical channel 103A have the same size, and the optical channel 103A has a basically vertical side wall.

[0033] Further references Figure 2 , the upper wafer 101 has a first optical terminal 104, and the lower wafer 102 has a second optical terminal 105, and the first optical terminal 104 and the second optical terminal 105 are connected to each other through the optical channel 103A of the connection structure 103. Specifically, the first portion 103A1 of the optical channel 103A contacts the first optical terminal 104, and the second portion 103A2 of the optical channel 103A contacts the second optical terminal 105. In addition, Figure 2B Shown Figure 2 An enlarged view of region A of the package structure 100, from Figure 2BAs can be seen from FIG, the sidewall 103S of the connection structure 103 forms a stepped structure. Figure 2B It can be further seen that there is a gap at the interface V between the first portion 103A1 and the second portion 103A2 of the light channel 103A. Figure 2 The package structure 100 shown forms a stepped structure. Figure 3 The packaging structure 200 shown also forms a stepped structure, that is, when the sizes of the first portion 103A1 and the second portion 103A2 of the optical channel 103A are not equal, the sidewalls 103S of the connection structure 103 may form a stepped structure.

[0034] Furthermore, the electrical channel 103B includes a first electrical channel 103B1 covering a first portion 103A1 of the optical channel 103A and a second electrical channel 103B2 covering a second portion 103A2 of the optical channel 103A, wherein Figure 2 As shown, the first electrical channel 103B1 and the second electrical channel 103B2 have the same shape. Figure 3 The first electrical channel 103B1 and the second electrical channel 103B2 in the package structure 300 shown in FIG. 3 also have the same shape. Figure 5 The package structure 400 shown is Figure 6 The package structure 500 shown in FIG. Figure 2 The package structure 100 shown is similar, except that Figure 5 The package structure 400 shown is Figure 6 In the package structure 500 shown, the first electrical channel 103B1 and the second electrical channel 103B2 have different shapes. Figure 5 In the package structure 400 shown, the first electrical channel 103B1 and the second electrical channel 103B2 may both have inclined sidewalls, such as being inclined in different directions. Specifically, the sidewalls of the first electrical channel 103B1 are inclined from the upper wafer 101 toward the direction away from the first portion 103A1 of the optical channel 103A, while the sidewalls of the second electrical channel 103B2 are inclined from the lower wafer 102 toward the direction away from the second portion 103A2 of the optical channel 103A. Figure 6 In the package structure 500 shown, the first electrical channel 103B1 may have a substantially vertical sidewall (substantially perpendicular to the upper wafer 101 or the lower wafer 102), and the second electrical channel 103B2 may have an inclined sidewall. Specifically, the second electrical channel 103B2 is inclined from the lower wafer 102 toward the direction away from the second portion 103A2 of the optical channel 103A. Figure 5 and Figure 6 In the illustrated embodiment, the first electrical channel 103B1 and the second electrical channel 103B2 have different sizes in the cross-sectional view.

[0035] Return to reference Figure 2 , the package structure 100 further includes a seed layer 106, which is disposed at the interface between the first portion 103A1 of the optical channel 103A and the electrical channel 103B, and at the interface between the second portion 103A2 and the electrical channel 103B. Furthermore, the seed layer 106 is further disposed at the interface between the upper wafer 101 and the connection structure 103, and at the interface between the lower wafer 102 and the connection structure 103. However, there is no seed layer at the interface V between the first portion 103A1 and the second portion 103A2, and there is no seed layer 106 at the interface between the first electrical channel 103B1 and the second electrical channel 103B2. In addition, from Figure 2 As can be seen from FIG, the package structure 100 further includes a bottom filling layer 107 filled between the upper wafer 101 and the lower wafer 102. Figure 2 As shown, the bottom filling layer 107 is separated from the optical channel 103A. Specifically, the bottom filling layer 107 is separated from the optical channel 103A by the electrical channel 103B. In some embodiments, a plating layer 108 is further provided between the seed layer 106 and the first portion 103A1 and the second portion 103A2 as well as the upper wafer 101 and the lower wafer 102. Figure 2 As shown, the seed layer 106 is lined with a plating layer 108 .

[0036] Next, see Figure 7 and Figure 8 , Figure 7 and Figure 8 The package structure 600 and the package structure 700 according to some embodiments of the present application are shown respectively. Figure 7 The package structure 600 shown in FIG. Figure 8 In the package structure 700 shown, a single first optical terminal 104 is connected to a plurality of connection structures 103. Furthermore, while the electrical channels 103B of the plurality of connection structures 103 cover the optical channels 103A, the electrical channels 103B and the optical channels 103A are alternately arranged. In addition, the single first optical terminal 104 is connected to a plurality of second optical terminals 105 via the bumps of the plurality of connection structures 103. Specifically, Figure 7 In the package structure 600 shown, a single first optical terminal 104 is connected to two second optical terminals 105 via two optical channels 103A, and the sizes of the first portion 103A1 and the second portion 103A2 of the two optical channels 103A change in opposite directions, that is, the size of one of the two optical channels 103A changes from large to small in the direction from the first optical terminal 104 to the second optical terminal 105, while the size of the other of the two optical channels 103A changes from small to large in the direction from the first optical terminal 104 to the second optical terminal 105. Similarly, in Figure 8In the packaging structure 800 shown, a single first optical terminal 104 is connected to three second optical terminals 105 through three optical channels 103A, and the size change trends of the first part 103A1 and the second part 103A2 in the three optical channels 103A are also different, that is, the sizes of the two optical channels 103A at the ends of the three optical channels 103A change from large to small in the direction from the first optical terminal 104 to the second optical terminal 105, while the size of the middle optical channel 103A among the three optical channels 103A changes from small to large in the direction from the first optical terminal 104 to the second optical terminal 105.

[0037] Afterwards, see Figure 9 , Figure 9 The package structure 800 according to some embodiments of the present application is shown. Figure 9 In the package structure 800 shown, the optical channel 103A of the connection structure 103 includes a first portion 103A1, a second portion 103A2, and a third portion 103A3 between the first portion 103A1 and the second portion 103A2. In a top view, the vertical projection range S1 of the first portion 103A1 is the same as the vertical projection range S2 of the second portion 103A2, and is different from the vertical projection range S3 of the third portion 103A3. Figure 9 In the package structure 800 shown, the vertical projection range S3 of the third portion 103A3 is larger than the vertical projection range S1 of the first portion 103A1 and the vertical projection range S2 of the second portion 103A2. Figure 9 In the package structure 800 shown, the electrical channel 103B includes not only a first electrical channel 103B1 covering the first portion 103A1 of the optical channel 103A, and a second electrical channel 103B2 covering the second portion 103A2 of the optical channel 103A, but also a third electrical channel 103B3 covering the third portion 103A3. It is worth noting that a seed layer 106 is present at the interface between the third electrical channel 103B3 and the first electrical channel 103B1.

[0038] In the above embodiment, the first portion 103A1, second portion 103A2, and third portion 103A3 (if present) of the optical channel 103A, as well as the underfill layer 107, include, but are not limited to, non-metallic materials such as polyimide, epoxy resin, ABF (Ajinomoto Build-up Film), polypropylene, and / or acrylic. In some embodiments, the underfill layer 107 may also include molding compound. In some embodiments, the underfill layer 107 may be filled with fillers, such as inorganic fillers such as silica fillers. In some embodiments, the first portion 103A1, second portion 103A2, and third portion 103A3 (if present) of the optical channel 103A, as well as the underfill layer 107, include, but are not limited to, organic photosensitive and / or non-photosensitive liquids and / or dry film materials. In some embodiments, the seed layer 106, the starting layer 108, and the first, second, and possibly third electrical channels 103B1, 103B2, and 103B3 of the electrical channels 103B may include, but are not limited to, copper, gold, silver, aluminum, palladium, platinum, nickel, and alloys thereof. In the above-mentioned packaging structure 100-800, each bump formed by the connection structure 103 may be composed of a central waveguide material surrounded by a metal reflective ring, that is, the optical channel 103A may be composed of a central waveguide material, and the electrical channel 103B may be composed of metal.

[0039] Next, return to the reference Figure 2 and Figure 2C , Figure 2C Shown Figure 2 The dimensions of the various components of the package structure 100 are shown in FIG. Figure 2CAs shown, the spacing SBP between the outermost sidewalls of the connection structure 103 of the package structure 100 is in the range of 1 μm to 30 μm. In some embodiments, in the right region R of the package structure 100, the diameter (TWD) of the first portion 103A1 of the optical channel 103A is in the range of 1 μm to 30 μm, and the diameter (BWD) of the second portion 103A2 of the optical channel 103A is in the range of 1 μm to 30 μm. In further embodiments, the thickness (SLT) of the seed layer 106 is in the range of 0.1 μm to 5 μm, and the thickness (SPT) of the starting layer 108 is in the range of 0.5 μm to 10 μm. Furthermore, in some embodiments, the width (RW) of the first electrical channel 103B1 (as well as the second electrical channel 103B2 and the third electrical channel 103B3) is in the range of 1 μm to 20 μm, and the thickness (RT) of the first electrical channel 103B1 (as well as the second electrical channel 103B2 and the third electrical channel 103B3) is in the range of 1 μm to 20 μm. In addition, the thickness (CT) of the upper wafer 101 (and possibly the lower wafer 102) is in the range of 10 μm to 100 μm, and the gap (GBC) between the upper wafer 101 and the lower wafer 102 (i.e., the thickness of the bottom fill layer 107) is in the range of 10 μm to 50 μm.

[0040] Afterwards, see the Figure 2D , Figure 2D Shown Figure 2 The light transmission path L of the package structure 100 is shown. Figure 2D ,exist Figure 2D In the left area L of the package structure 100 shown, the light of the second optical terminal 105 is reflected by the second portion 103A2 of the optical channel 103A and transmitted through the first portion 103A1 before being transmitted to the first optical terminal 104. Figure 2D In the right region R of the package structure 100 shown in FIG, the light of the first optical terminal 104 is reflected by the first portion 103A1 of the optical channel 103A and transmitted through the second portion 103A2, and then transmitted to the second optical terminal 105. Figure 2 In the optical transmission path L shown, light can be transmitted from the first portion 103A1 to the second portion 103A2, or from the second portion 103A2 to the first portion 103A1. In some embodiments, light can be transmitted from the first portion 103A1 / second portion 103A2 with a smaller coverage area to the second portion 103A2 / 103A1 with a larger coverage area. However, it should be understood that Figure 2D The optical transmission path L shown is exemplary and can be transmitted according to actual conditions.

[0041] Continue to refer to Figures 2 to 2BSome other embodiments of the present application provide a packaging structure 100, which includes a lower wafer 102, a connection structure 103 disposed above the lower wafer 102, and an upper wafer 101 disposed above the connection structure 103, wherein the connection structure 103 is provided with an optical channel 103A and an electrical channel 103B surrounding the optical channel 103A, the lower wafer 102 is electrically and optically connected to the upper wafer 101 through the connection structure 103, and wherein the sidewall 103S of the connection structure 103 forms a stepped structure. Further, in some embodiments, the optical channel 103A of the connection structure 103 includes a first portion 103A1 and a second portion 103A2, wherein Figure 2A In the cross-sectional view shown and in Figure 2B In the top view shown, the vertical projection range S1 of the first portion 103A1 is different from the vertical projection range S2 of the second portion 103A2. Figure 2 In the left area L shown, the vertical projection range S1 of the first part 103A1 is larger than the vertical projection range S2 of the second part 103A2, and Figure 2 In the right region R shown, the vertical projection range S1 of the first portion 103A1 is smaller than the vertical projection range S2 of the second portion 103A2. Furthermore, in some embodiments, the package structure 100 further includes a seed layer 106 disposed at the interface between the first portion 103A1 of the optical channel 103A and the electrical channel 103B, and at the interface between the second portion 103A2 and the electrical channel 103B. The seed layer 106 is not present at the interface V between the first portion 103A1 and the second portion 103A2.

[0042] In addition, see Figure 10A and Figure 10B , Figure 10A and Figure 10B A carrier 109 is shown for carrying chips such as an upper wafer 101 and / or a lower wafer 102. Figure 10A and Figure 10B As can be seen from FIG, the carrier 109 can be of any suitable shape, such as Figure 10A The square shape shown and Figure 10B The circular shape shown may also be any suitable shape, such as but not limited to a rectangular shape, a diamond shape, etc.

[0043] In summary, the package structure 100-800 provided in this application provides a superior performance design, enabling unprecedented shortest optical path applications for package structures such as SiPh by utilizing waveguide bump bonding of the connection structure 103. In this package structure 100-800, each bump formed by the connection structure 103 can be composed of a central waveguide material (optical channel 103A) surrounded by a metal reflective ring (electrical channel 103B). Furthermore, the optical signal / optical path interconnection of the package structure 100-800 can directly provide more efficient communication, such as faster transmission speeds for phonetic symbols (the speed of phonetic symbols is >2 times that of electricity). Further, in the connection structure 103, the difference in size (such as vertical coverage) between the first part 103A1 (top bump) and the second part 103A2 (bottom bump) of the optical channel 103A is advantageous in that it allows a larger wafer / chip bonding offset, and a larger receiving end Rx terminator (such as the first optical terminal 104 or the second optical terminal 105) can cover all smaller transmitter Tx terminators (such as the second optical terminal 105 or the first optical terminal 104).

[0044] In addition, the bonding interface of the connection structure 103 is formed by the reflective ring (electrical channel 103B) and the waveguide bump (optical channel 103A), which together form an interconnection for electrical and optical signal communication. Furthermore, the reflective ring (electrical channel 103B) provides at least two functions: a conductive path and a metal bonding medium, and the waveguide bump (optical channel 103A) provides at least two functions: an optical transmission path and a bonding strength medium. As can be seen, the present application utilizes the waveguide bump (optical channel 103A) for top and bottom bonding, and has a metal wall structure (electrical channel 103B) around it. This structure can simultaneously transmit light and electrical signals without the use of RDL. That is, in the present application, the metal structure (electrical channel 103B) surrounds the waveguide bump (optical channel 103A) and is used for the transmission of both electrical and optical signals. In the present application, waveguide bumps (optical channels 103A) are used as one of the structures for optical signal transmission, which not only reduces the steps of converting optical signals into electrical signals, but also eliminates the need for RDL process, further reducing the defective rate of the corresponding packaging structure and improving the yield of the corresponding packaging structure.

[0045] Refer to the following Figures 11 to 23 To introduce Figure 2 The process of forming the package structure 100 is shown.

[0046] Reference Figure 11 , providing a lower wafer 102, and forming a second optical terminal 105, such as a pad, on the surface of the lower wafer 102. In some embodiments, the second optical terminal 105 can be used as an optical signal area, and the lower wafer 102 can be an optical signal chip. Figure 12, a waveguide film 1001 is formed on the surface of the lower wafer 102 where the second photonic pad 105 is formed, such as by lamination. In some embodiments, the waveguide film 1001 can be manufactured using organic photosensitive or / and non-photosensitive liquid or / and dry film materials. Further, a portion of the waveguide film 1001 is removed by photolithography and exposure process P1, thereby forming Figure 13 The light channel 103A shown (see Figure 2 )’s second part 103A2.

[0047] Next, see Figure 14 and Figure 15 , a plating layer 108' such as titanium (Ti) is manufactured by PVD (physical vapor deposition process) or the like, and a seed layer 106' such as copper (Cu) is also manufactured by PVD or the like. Figure 16 A photoresist layer 1002 is formed by a lamination process, and then an opening 1002 exposing the second portion 103A2 of the optical channel 103A is formed on the photoresist layer 1002 by a photolithography, exposure and development process P2. Figure 17 See further Figure 17 After forming the opening 1002, a metal layer 103B2′, such as a copper layer, is deposited in the opening 1002 and over the second portion 103A2 of the optical channel 103A. In some embodiments, a plating process such as electroplating or electroless plating can be used. In some embodiments, a manufacturing process such as PVD, plating, electroless plating, printing, or potting metal can be used to form the metal layer 103B2′, the starting layer 108′, and the seed layer 106′.

[0048] See also Figure 18 , remove the photoresist layer 1002, and remove the seed layer 106' and the portion of the plating layer 108' not covered by the metal layer 103B2' by an etching process such as wet etching. Figure 18 The metal layer 103B2', the seed layer 106' and the plating layer 108' on the second portion 103A2 of the optical channel 103A are removed by a grinding process P3 using a grinding wheel, thereby forming Figure 20 The second electrical channel 103B2 of the electrical channel 103B is shown along with the seed layer 106 and the starting layer 108 .

[0049] repeat Figures 11 to 18 The process is performed to form the upper wafer 101 and the corresponding first portion 103A1 of the optical channel 103A and the first electrical channel 103B1 of the electrical channel 103B and the corresponding seed layer 106 and plating layer 108.

[0050] Afterwards, see Figure 21, the upper wafer 101 is placed on the lower wafer 102, and when placed, the first portion 103A1 of the optical channel 103A is aligned with the second portion 103A2. Figure 22 After placement, an ultrasonic (US) fusion bonding process P4 is used to bond the first portion 103A1 and the second portion 103A2 of the optical channel 103A and the first portion 103B1 and the second portion 103B2 of the electrical channel 103B. Figure 23 The bottom filling layer 107 is formed by an adhesive molding manufacturing process such as a bottom filling process. In some embodiments, the bottom filling layer 107 is an adhesive layer. In some embodiments, the bottom filling layer 107 is a molding compound. After forming the bottom filling layer 107, the bottom filling layer 107 is obtained. Figure 2 The package structure 100 is shown.

[0051] for Figures 3 to 8 The packaging structures 200 to 700 are formed by methods similar to the packaging structure 100 and are not described in detail here.

[0052] for Figure 9 The package structure 800 shown in FIG. Figure 18 After the corresponding structure of the lower wafer 102 is formed, the third portion 103A3 of the optical channel 103A is bonded to the second portion 103A2 through a carrier and then the corresponding carrier is removed. Finally, the upper wafer 101 formed with the second portion 103A2 of the optical channel 103A is bonded to the third portion 103A3 of the optical channel 103A, thereby forming Figure 9 The package structure 800 shown in FIG. 800 . In the package structure 800 , due to the formation of the third portion 103A3 of the optical channel 103A, the bottom filling layer 107 can be better filled with corresponding baseless fillers, such as silica fillers, etc., which can enhance the corresponding strength of the package structure 800 .

[0053] In the above manufacturing process, photolithography and plating are first used to form a waveguide bump (the first portion 103A1 or the second portion 103A2 of the optical channel 103A) around a reflective ring (the first electrical channel 103B1 and the second electrical channel 103B2 of the electrical channel 103B) on the surface of the PNL (panel-level packaging) (or WL (wafer-level packaging) / chip / RDL) through photolithography and plating. The waveguide bump (the first portion 103A1 or the second portion 103A2 of the optical channel 103A) is then connected upward to the optical signal area (the second optical terminal 105). A plating process is then used to form the reflective ring (the first electrical channel 103B1 and the second electrical channel 103B2 of the electrical channel 103B) using a seed layer 106' and a plating layer 108'. Next, a grinding wheel grinding process is used to expose the top of the waveguide bump (the first portion 103A1 or the second portion 103A2 of the optical channel 103A) and thin the reflective ring (the first electrical channel 103B1 and the second electrical channel 103B2 of the electrical channel 103B).

[0054] Next, the top and bottom waveguide bumps (i.e., the first portion 103A1 and the second portion 103A2 of the optical channel 103A) are bonded together using an ultrasonic (US) fusion bonding process. Finally, an underfill layer 107, such as an adhesive material, is filled into the gap between the upper wafer 101 and the lower wafer 102, such as a chip, to form a package structure 100 with a waveguide bump bonding structure.

[0055] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A packaging structure, characterized in that: include: Wafer loading; Lower chip; a connecting structure, interposed between the upper wafer and the lower wafer and connecting the upper wafer and the lower wafer, The connection structure includes an optical channel and an electrical channel, and the electrical channel covers the optical channel. The optical channel of the connection structure includes a first part and a second part. In the top view, the vertical projection range of the first part is different from the vertical projection range of the second part.

2. The packaging structure according to claim 1, wherein: The optical channel of the connecting structure includes a first part and a second part, In the top view, the vertical projection range of the first part is larger than the vertical projection range of the second part.

3. The packaging structure according to claim 2, wherein: The sidewall of the connecting structure forms a stepped structure.

4. The packaging structure according to claim 1, wherein: The upper wafer has a first optical terminal, and the lower wafer has a second optical terminal. The first optical terminal and the second optical terminal are connected to each other through the optical channel of the connection structure.

5. The packaging structure according to claim 1, wherein: There is a gap at the interface between the first part and the second part.

6. The packaging structure according to claim 1, wherein: Also includes: A seed layer is provided at an interface between the first portion and the electrical channel and at an interface between the second portion and the electrical channel.

7. The packaging structure according to claim 1, wherein: A top surface of the second portion contacts the electrical via.

8. The packaging structure according to claim 1, wherein: Also includes: A bottom filling layer is filled between the upper wafer and the lower wafer.

9. The packaging structure according to claim 8, wherein: The underfill layer is spaced apart from the light channel.

10. The packaging structure according to claim 6, wherein: The seed layer is further disposed at an interface between the upper wafer and the connection structure and an interface between the lower wafer and the connection structure.

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