Circuit board structure for optimizing high-speed signal quality and wiring channel

Abstract

The utility model discloses a circuit board structure for optimizing high-speed signal quality and wiring channels, which comprises an FBGA (fiber bragg grating array) chip area, a peripheral interface area and AC (alternating current) coupling capacitors. An upper bonding pad of each pair of differential AC coupling capacitors is connected with a first differential hole in an upper FBGA chip area through a first differential wire, and a lower bonding pad of each pair of differential AC coupling capacitors is connected with a second differential hole in a lower peripheral interface area through a second differential wire. According to the utility model, the sum of the length of the first differential wire and the length of the second differential wire of each pair of differential AC coupling capacitors is the same, so that the lengths of the outer-layer wires are equal, and the signal quality is improved; the AC coupling capacitors in the upper row and the lower row are staggered with each other, and the first differential wires and the second differential wires smoothly pass through the adjacent AC coupling capacitors, so that other signal channels in an FBGA chip area are not affected.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit boards, and more particularly to a circuit board structure for optimizing high-speed signal quality and wiring channels. Background Art

[0002] A differential signal is two signals with equal amplitudes and opposite directions, and the pair of traces that carry the differential signal is called a differential trace. Differential signals are increasingly used in high-speed circuit design. The most critical signals in the circuit often adopt differential structure design. Compared with ordinary single-ended signal traces, differential signal lines have the following advantages: (1) In the same circuit, the single-ended trace refers to the ground plane, and the performance of the interference received from the outside world and the same interference received on the ground plane is very different, resulting in the interference of the single-ended trace and the interference in the return path cannot cancel each other out. However, since the signals of the differential trace are equal in size and opposite in direction, the coupling between the two differential traces is very good, and the impedance transformation is more matched. The external noise signal will basically be coupled to the two lines at the same time, and the receiving end Only the difference between the two signals is considered, so the external common-mode noise can be completely eliminated, improving the signal transmission quality. (2) The two differential signals have opposite polarities, and their radiated electromagnetic fields to the outside world can cancel each other out, ensuring that the two lines are only coupled. The tighter the coupling, the more magnetic induction lines that cancel each other out, and the less radiated signals are released to the outside world, improving the stability of system transmission and effectively suppressing EMI. (3) The switching change of the differential signal is located at the intersection of the two signals, unlike ordinary single-ended signals that rely on high and low threshold voltages for judgment. Therefore, it is less affected by process and temperature, can reduce timing errors, and is also more suitable for circuits with low amplitude signals. Differential signals play an irreplaceable role in high-speed signal transmission.

[0003] When processing high-speed FBGA signals, many differential signals require AC coupling capacitors at the FBGA end to eliminate DC offset, isolate ground potential differences, and provide high-frequency filtering in the signal path. One end of the AC coupling capacitor is connected to the FBGA, and the other end is connected to the peripheral interface. However, the differential signal traces between the existing AC coupling capacitors, the FBGA, and the peripheral interface are often inconsistent in length. This length difference causes different signal delays during transmission, resulting in inconsistent signal transmission rates, which in turn affects overall signal quality. Utility Model Content

[0004] In order to overcome the problem that the differential signal trace lengths between the existing AC coupling capacitors and the FBGA and peripheral interfaces are often inconsistent, the length difference will cause the signal to experience different delays during transmission, which in turn causes inconsistent signal transmission rates, thereby affecting the overall signal quality. The utility model provides a circuit board structure that optimizes high-speed signal quality and wiring channels.

[0005] The technical solution of this utility model is as follows:

[0006] A circuit board structure for optimizing high-speed signal quality and wiring channels includes an FBGA chip area, a peripheral interface area, and several AC coupling capacitors. The AC coupling capacitors are distributed in two rows and staggered up and down. The upper pads of each pair of differential AC coupling capacitors are connected to a first differential hole in the upper FBGA chip area via a first differential trace, and the first differential hole is located at the upper left of the AC coupling capacitors. The lower pads of each pair of differential AC coupling capacitors are connected to a second differential hole in the lower peripheral interface area via a second differential trace, and the second differential hole is located at the lower right of the AC coupling capacitors.

[0007] According to the above solution of the present invention, the spacing between the upper pads of the same pair of differential AC coupling capacitors is X, and the spacing between the lower pads of the same pair of differential AC coupling capacitors is Y, and X and Y are equal.

[0008] According to the above solution of the present invention, both X and Y are 35 mil.

[0009] According to the above solution of the present invention, the spacing between two adjacent pairs of the first differential holes is equal to the spacing between two adjacent pairs of the second differential holes.

[0010] According to the above solution of the present invention, the horizontal distance between the first AC coupling capacitor in the upper row and the first AC coupling capacitor in the lower row is equal to the horizontal distance between two adjacent pairs of the first differential holes, both being A.

[0011] According to the above solution of the present invention, A is equal to 55 mil.

[0012] According to the above solution of the present invention, the spacing between adjacent differential AC coupling capacitors in each row is 2A.

[0013] According to the above solution of the present invention, the first differential hole and the second differential hole are aligned in the vertical direction.

[0014] According to the above solution of the present invention, the spacing between each pair of the first differential holes is equal to the spacing between each pair of the second differential holes, both being B.

[0015] According to the above solution of the present invention, B is 30 mil.

[0016] According to the above solution of the present invention, the first differential hole is provided with a first via hole in the vertical direction, and the second differential hole is provided with a second via hole in the vertical direction.

[0017] According to the above solution of the present invention, the first via hole and the second via hole have the same size.

[0018] The beneficial effect of the present invention according to the above scheme is that the present invention divides the AC coupling capacitors into two rows, one above the other, and arranges them in an offset manner. The differential signal in the direction of the FBGA chip area is connected to the first differential hole in the upper left corner, and the differential signal in the direction of the peripheral interface area is connected to the second differential hole in the lower right corner. This can ensure that the length of the first differential trace and the length of the second differential trace of each pair of differential AC coupling capacitors are the same, thereby achieving equal length of outer layer traces and improving signal quality. The upper and lower rows of AC coupling capacitors are staggered with each other, which has little impact on the channel during high-speed interconnection, allowing the first differential trace and the second differential trace to pass smoothly between adjacent AC coupling capacitors, ensuring that other signal channels in the FBGA chip area are not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural diagram of the present utility model.

[0020] In the drawings, the reference numerals are as follows:

[0021] 100, circuit board; 11, FBGA chip area; 111, first differential hole; 112, first differential trace; 113, first via; 12, AC coupling capacitor; 121, upper pad; 122, lower pad; 13, peripheral interface area; 131, second differential hole; 132, second differential trace; 133, second via. DETAILED DESCRIPTION

[0022] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0023] It should be noted that the terms "including" and "having," as well as any variations thereof, in the specification and claims of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or device. Terms such as "disposed" should be interpreted broadly, for example, and may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, internal connections between two elements, or interactions between two elements, unless otherwise expressly defined. Terms such as "upper," "lower," "left," "right," "front," "back," and "bottom" indicate directions or positions based on those shown in the accompanying drawings. These are for ease of description only and should not be construed as limitations on the present invention.

[0024] It's important to note that when processing high-speed FBGA signals, many differential signals require AC coupling capacitors at the FBGA end to eliminate DC offset, isolate ground potential differences, and provide high-frequency filtering in the signal path. One end of the AC coupling capacitor is connected to the FBGA, and the other end is connected to the peripheral interface. However, the differential signal traces between the existing AC coupling capacitors and the FBGA and peripheral interface are often of inconsistent length. This length difference causes different signal delays during transmission, leading to inconsistent signal transmission rates. These inconsistent transmission rates can cause phase deviations or timing errors when the signals reach the receiver, leading to degraded signal quality such as increased signal jitter and eye closure. This not only affects the correct reception of data but can also adversely affect the overall performance of the system.

[0025] like Figure 1 As shown, this embodiment provides a circuit board structure that optimizes high-speed signal quality and wiring channels, and arranges AC coupling capacitors 12 in two rows in an upper and lower staggered manner. The differential signal in the direction of the FBGA chip area 11 is connected to the first differential hole 111 in the upper left corner, and the differential signal in the direction of the peripheral interface area 13 is connected to the second differential hole 131 in the lower right corner. This can achieve that the length of the first differential trace 112 and the length of the second differential trace 132 of each pair of differential AC coupling capacitors 12 are the same, thereby achieving equal length of outer layer traces and improving signal quality. The upper and lower rows of AC coupling capacitors 12 are staggered with each other, and during high-speed interconnection, the impact on the channel is small, allowing the first differential trace 112 and the second differential trace 132 to pass smoothly between adjacent AC coupling capacitors 12, ensuring that other signal channels in the FBGA chip area 11 are not affected.

[0026] Specifically, the circuit board structure that optimizes high-speed signal quality and wiring channels includes an FBGA chip area 11, a peripheral interface area 13 and several AC coupling capacitors 12. The several AC coupling capacitors 12 are distributed in two rows and staggered up and down. The upper pads 121 of each pair of differential AC coupling capacitors 12 are connected to the first differential holes 111 in the upper FBGA chip area 11 through the first differential trace 112. The first differential hole 111 is located in the upper left of the AC coupling capacitor 12. The lower pads 122 of each pair of differential AC coupling capacitors 12 are connected to the second differential holes 131 in the lower peripheral interface area 13 through the second differential trace 132. The second differential hole 131 is located in the lower right of the AC coupling capacitor 12.

[0027] The staggered arrangement of the AC coupling capacitors 12 not only saves space on the circuit board 100, but also avoids signal interference problems that may be caused by the close arrangement of capacitors, allowing differential signal lines to pass smoothly between adjacent capacitors, reducing the additional inductance and capacitance generated by crossing or detouring lines, and helping to maintain the purity and integrity of the signal.

[0028] The upper pad 121 of the AC coupling capacitor 12 is connected to the first differential hole 111 located in the upper left corner, and the lower pad 122 of the AC coupling capacitor 12 is connected to the second differential hole 131 located in the lower right corner, ensuring that the sum of the lengths of the first differential trace 112 and the second differential trace 132 are equal, ensuring that the differential signals experience the same delay during transmission, thereby eliminating the problem of inconsistent transmission rates caused by differences in trace lengths.

[0029] In one embodiment, the spacing between the upper pads 121 of the same pair of differential AC coupling capacitors 12 is X, and the spacing between the lower pads 122 of the same pair of differential AC coupling capacitors 12 is Y. X and Y are equal, ensuring symmetry of the differential signal on both sides of the capacitors and reducing signal distortion caused by asymmetry. X and Y are both 35 mils. The 35 mil spacing is neither too tight to increase manufacturing difficulties nor too loose to waste space or increase unnecessary parasitic effects.

[0030] The first differential hole 111 and the second differential hole 131 are vertically aligned. Because the holes are in a line, the impact on the channel is minimal during high-speed interconnection, allowing the differential to pass smoothly between the two holes, ensuring that other signal channels in the FBGA are not affected.

[0031] In one embodiment, the spacing between two adjacent pairs of first differential holes 111 is equal to the spacing between two adjacent pairs of second differential holes 131 , ensuring the balance of differential signals during transmission and avoiding differences in signal transmission speeds caused by inconsistent hole spacing.

[0032] The horizontal distance between the first AC coupling capacitor 12 in the upper row and the first AC coupling capacitor 12 in the lower row is equal to the horizontal distance between two adjacent pairs of first differential holes 111, both being A. A is equal to 55 mil.

[0033] The spacing between adjacent differential AC coupling capacitors 12 in each row is 2A. This spacing provides sufficient space for the first differential trace 112 and the second differential trace 132 to smoothly pass between adjacent AC coupling capacitors 12 without worrying about signal crossing or additional inductance and capacitance caused by detours.

[0034] By precisely controlling the spacing between the differential AC coupling capacitors 12 and their associated traces and vias, the differential signal transmission path is balanced and consistent, significantly improving signal quality. This reduces signal distortion, attenuation, and interference caused by inconsistent trace lengths, improper spacing, or chaotic layouts.

[0035] In one embodiment, the spacing between each pair of first differential vias 111 is equal to the spacing between each pair of second differential vias 131, both being B. B is 30 mils. Maintaining consistent spacing between each pair of differential vias helps ensure that each pair of differential signals experiences a similar electrical environment and path delay during transmission, thereby reducing signal phase and amplitude differences that may result from inconsistent spacing and maintaining differential signal consistency.

[0036] In one embodiment, the first differential hole 111 is provided with a first via 113 in the vertical direction, and the second differential hole 131 is provided with a second via 133 in the vertical direction. The first via 113 and the second via 133 are of equal size. By adjusting the diameter of the via and the size of the pad, the impedance of the via can be made as close as possible to the impedance of the signal line, thereby reducing signal reflection and loss at the via and improving signal transmission efficiency and quality.

[0037] The diameters of first via 113 and second via 133 are both 8 mils. Smaller via diameters help reduce parasitic capacitance and inductance, thereby reducing signal distortion and attenuation at the vias. The diameters of the pads for first via 113 and second via 133 are both 16 mils, helping to ensure a good connection between the pad and the via while providing sufficient area to accommodate soldering materials and address manufacturing tolerances.

[0038] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the claims attached to this utility model.

[0039] The above is an exemplary description of the present utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the present utility model patent is not limited to the above-mentioned method. As long as various improvements are made using the method concept and technical solution of the present utility model patent, or the concept and technical solution of the present utility model patent are directly applied to other occasions without improvement, they are all within the scope of protection of the present utility model.

Claims

1. A circuit board structure that optimizes high-speed signal quality and wiring channels, characterized in that: It includes an FBGA chip area, a peripheral interface area and several AC coupling capacitors. The several AC coupling capacitors are distributed in two rows and staggered up and down. The upper pads of each pair of differential AC coupling capacitors are connected to the first differential hole in the upper FBGA chip area through a first differential trace. The first differential hole is located in the upper left of the AC coupling capacitor. The lower pads of each pair of differential AC coupling capacitors are connected to the second differential hole in the lower peripheral interface area through a second differential trace. The second differential hole is located in the lower right of the AC coupling capacitor.

2. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 1, characterized in that: The distance between the upper pads of the same pair of differential AC coupling capacitors is X, and the distance between the lower pads of the same pair of differential AC coupling capacitors is Y, and X and Y are equal.

3. A circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 1 or 2, characterized in that: The spacing between two adjacent pairs of the first differential holes is equal to the spacing between two adjacent pairs of the second differential holes.

4. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 3, characterized in that: The horizontal distance between the first AC coupling capacitor in the upper row and the first AC coupling capacitor in the lower row is equal to the horizontal distance between two adjacent pairs of the first differential holes, both being A.

5. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 4, characterized in that: The spacing between adjacent differential AC coupling capacitors in each row is 2A.

6. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 1, characterized in that: The first differential hole is aligned with the second differential hole in a vertical direction.

7. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 1, characterized in that: The distance between each pair of the first differential holes is equal to the distance between each pair of the second differential holes, both being B.

8. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 1, characterized in that: B is 30mil.

9. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 1, characterized in that: The first differential hole is provided with a first via hole in a vertical direction, and the second differential hole is provided with a second via hole in a vertical direction.

10. The circuit board structure for optimizing high-speed signal quality and wiring channels according to claim 9, characterized in that: The first via hole and the second via hole have the same size.

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