Packaging structure

Abstract

The embodiment of the utility model discloses a packaging structure. Comprising a wafer, a first surface of the wafer is provided with a first power chip and a second power chip, and a groove with an opening facing the first surface is arranged between the first power chip and the second power chip; the first surface is provided with a plurality of first power chip connection bonding pads and second power chip connection bonding pads; the driving chip is located in the groove; the first surface is also provided with a plurality of driving chip connection bonding pads; the rewiring layer is located on the sides, away from the first surface, of the first power chip connecting bonding pad, the second power chip connecting bonding pad and the driving chip connecting bonding pad, and interconnection of the first power chip and the second power chip is achieved through the first power chip connecting bonding pad, the second power chip connecting bonding pad and the driving chip connecting bonding pad. According to the technical scheme provided by the embodiment of the utility model, by arranging the packaging structure, the packaging cost is reduced, the packaging size is reduced, the signal routing path is reduced, and the parasitic parameters on the signal transmission line are further reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a packaging structure. Background Art

[0002] Semiconductor devices are widely used in a variety of fields such as aerospace systems, radio frequency systems, and telecommunications devices. Semiconductor chips such as metal oxide semiconductor field effect transistors and insulated gate bipolar transistors are packaged together with other electronic components or integrated circuits to form a packaging structure. The formed packaging structure is used to provide electrical connection, heat dissipation, and mechanical support for the chips and other built-in components.

[0003] Conventional packaging employs encapsulation molding, which involves introducing a substrate, attaching the chip to one side of the substrate, applying glue, and then encapsulating the chip. However, conventional packaging structures often result in large package sizes, high packaging costs, and long signal routing paths. Utility Model Content

[0004] The utility model provides a packaging structure to solve the problems of high packaging cost, large packaging size and long signal routing path.

[0005] According to one aspect of the present invention, a packaging structure is provided, comprising:

[0006] A wafer comprising a first surface and a second surface arranged opposite to each other, wherein a first power chip and a second power chip are arranged on the first surface of the wafer, a groove is arranged between the first power chip and the second power chip, and an opening of the groove faces the first surface; a plurality of first power chip connection pads and a plurality of second power chip connection pads arranged at intervals are arranged on the first surface; the first power chip connection pad is electrically connected to the first power chip, and the second power chip connection pad is electrically connected to the second power chip;

[0007] A driver chip is located in the groove; the first surface is further provided with a plurality of driver chip connection pads arranged at intervals; the driver chip connection pads are electrically connected to the driver chip;

[0008] The redistribution layer is located on a side of the first power chip connection pad, the second power chip connection pad, and the driver chip connection pad away from the first surface, and the first power chip and the second power chip are interconnected through the first power chip connection pad, the second power chip connection pad, and the driver chip connection pad.

[0009] Optionally, the first power chip is a gallium nitride chip, and the second power chip is a gallium nitride chip.

[0010] Optionally, a first insulating layer is provided on the bottom and sidewalls of the groove, the first insulating layer on the bottom of the groove is located on the second surface, and the first insulating layer is used to insulate the driving chip from the first power chip, and to insulate the driving chip from the second power chip.

[0011] Optionally, the redistribution layer includes a second insulating layer, a first redistribution layer, a second redistribution layer, and a third redistribution layer; the redistribution layer includes a third surface and a fourth surface that are oppositely disposed, and the third surface and the first surface are oppositely disposed;

[0012] The second insulating layer is located on the third surface and is located between the plurality of first power chip connection pads, between the plurality of second power chip connection pads, between the first power chip connection pads and the driver chip connection pads, and between the second power chip connection pads and the driver chip connection pads; the second insulating layer extends from the third surface into the redistribution layer;

[0013] The first redistribution layer is used to connect the first power chip connection pad and the first part of the driver chip connection pad;

[0014] The second redistribution layer is used to connect the second power chip connection pad and the second part of the driver chip connection pad;

[0015] The third redistribution layer is used to connect a third portion of the connection pads of the driver chip.

[0016] Optionally, the redistribution layer further includes a third insulating layer and a fourth insulating layer.

[0017] The third insulating layer is located between the first redistribution layer and the third redistribution layer, and is used to insulate the first redistribution layer from the third redistribution layer;

[0018] The fourth insulating layer is located between the second redistribution layer and the third redistribution layer and is used to insulate the second redistribution layer from the third redistribution layer.

[0019] Optionally, the packaging structure further includes: a first conductive bump, a second conductive bump, and a third conductive bump;

[0020] The first conductive bump extends from the fourth surface to the first redistribution layer;

[0021] The second conductive bump extends from the fourth surface to the second redistribution layer;

[0022] The third conductive bump extends from the fourth surface to the third redistribution layer.

[0023] Optionally, the packaging structure further includes: a first metal layer, a second metal layer and a third metal layer;

[0024] The first metal layer is located between the first conductive bump and the first redistribution layer;

[0025] The second metal layer is located between the second conductive bump and the second redistribution layer;

[0026] The third metal layer is located between the third conductive bump and the third redistribution layer.

[0027] Optionally, the first metal layer includes a first nickel metal layer, the second metal layer includes a second nickel metal layer, and the third metal layer includes a third nickel metal layer.

[0028] Optionally, the second insulating layer includes a first polyimide insulating layer, the third insulating layer includes a second polyimide insulating layer, and the fourth insulating layer includes a third polyimide insulating layer.

[0029] Optionally, the size of the groove is larger than the size of the driving chip.

[0030] The technical solution of the embodiment of the utility model can save space and achieve a more compact chip layout by providing a groove between the first power chip and the second power chip in the wafer, and placing the driver chip in the groove, thereby reducing the package size and saving packaging costs. Moreover, by placing the driver chip in the groove between the first power chip and the second power chip, the electrical connection between the first power chip, the second power chip and the driver chip can be better achieved, thereby improving the integration and performance of the entire chip system. By providing a redistribution layer, the original connection lines of the chip can be rearranged and planned to meet different functional requirements, so that the signal routing path is short and the parasitic parameters on the signal transmission line are small.

[0031] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 is a cross-sectional schematic diagram of a packaging structure provided according to an embodiment of the present utility model;

[0034] Figure 2 This is a schematic top view of a packaging structure provided according to an embodiment of the present utility model;

[0035] Figure 3Schematic diagram of a wafer with a wide scribe line area introduced according to an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of the groove provided according to an embodiment of the present utility model;

[0037] Figure 5 This is a schematic diagram of a structure in which a driver chip is arranged in a groove according to an embodiment of the present utility model;

[0038] Figure 6 It is a structural diagram of setting a redistribution layer according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0039] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] To address the problems of high packaging cost, large packaging size, and long signal routing paths, the present invention provides the following technical solutions: Figure 1 It is a cross-sectional schematic diagram of a packaging structure provided according to an embodiment of the present utility model. Figure 2 Schematic diagram of a top view of a packaging structure provided according to an embodiment of the present utility model. Figure 1 and Figure 2As shown, the packaging structure includes: a wafer 10, including a first surface 101 and a second surface 102 arranged opposite to each other, the first surface 101 of the wafer 10 is provided with a first power chip 103 and a second power chip 104, a groove 105 is provided between the first power chip 103 and the second power chip 104, and the opening of the groove 105 faces the first surface 101; the first surface 101 is provided with a plurality of first power chip connection pads 106 and a plurality of second power chip connection pads 107 arranged at intervals; the first power chip connection pad 106 is electrically connected to the first power chip 103, and the second power chip connection pad 107 is electrically connected to the second power chip 103. The power chip 104 is electrically connected; the driver chip 20, the driver chip 20 is located in the groove 105; the first surface 101 is also provided with a plurality of driver chip connection pads 201 arranged at intervals; the driver chip connection pads 201 are electrically connected to the driver chip 20; the redistribution layer 30 is located on the side of the first power chip connection pad 106, the second power chip connection pad 107 and the driver chip connection pad 201 away from the first surface 101, and the first power chip 103 and the second power chip 104 are interconnected through the first power chip connection pad 106, the second power chip connection pad 107 and the driver chip connection pad 201.

[0042] In an embodiment of the present invention, two-dimensional packaging is performed for wafer-level chips. The first power chip 103, the second power chip 104, and the driver chip 20 together constitute a power device, specifically a power device (Driver-MOSFET, DrMOS) that integrates a drive circuit and a metal-oxide-semiconductor field-effect transistor (MOSFET). DrMOS meets high-performance and high-power density power conversion requirements. In DrMOS, the first power chip 103 can be an upper tube, and the second power chip 104 can be a lower tube.

[0043] By modifying the photolithography mask and other manufacturing processes, the scribe line area between the first power chip 103 and the second power chip 104 is widened. The purpose of widening is to form a groove 105 in this widened area through processes such as photolithography and etching, and to place a driver chip 20 within the groove 105. For example, the driver chip 20 can be a silicon driver integrated circuit. This saves space, achieves a more compact chip layout, reduces package size, and saves packaging costs. If the scribe line area between the first power chip 103 and the second power chip 104 is not utilized, a separate placement location for the driver chip 20 on the circuit board would be required, which would occupy more area and increase the length of the wiring between the chips, thereby affecting performance such as signal transmission speed and quality. By placing the driver chip 20 within the groove 105 between the first power chip 103 and the second power chip 104, better electrical connections can be achieved between the first power chip 103, the second power chip 104, and the driver chip 20, improving the integration and performance of the entire chip system.

[0044] The redistribution layer 30 is provided. During the wafer-level chip packaging process, one or more layers of metal wiring structures are constructed on the surfaces of the first power chip 103, the second power chip 104, and the driver chip 20 where pads are provided. This allows the original connection lines of the chips to be rearranged and planned to meet different functional requirements. The signals of the first power chip 103, the second power chip 104, and the driver chip 20 are interconnected through the redistribution layer 30, the first power chip connection pads 106, the second power chip connection pads 107, and the driver chip connection pads 201, thereby shortening the signal routing path and minimizing the parasitic parameters on the signal transmission lines.

[0045] The technical solution of the embodiment of the present invention can save space and achieve a more compact chip layout by setting a groove 105 between the first power chip 103 and the second power chip 104 in the wafer 10, and placing the driver chip 20 in the groove 105, thereby reducing the package size and saving packaging costs. Moreover, by placing the driver chip 20 in the groove 105 between the first power chip 103 and the second power chip 104, the electrical connection between the first power chip 103, the second power chip 104 and the driver chip 20 can be better achieved, thereby improving the integration and performance of the entire chip system. By setting the redistribution layer 30, the original connection lines of the chip can be rearranged and planned to meet different functional requirements, so that the signal routing path is short and the parasitic parameters on the signal transmission line are small.

[0046] In an optional embodiment of the present invention, reference Figure 1 The first power chip 103 is a gallium nitride chip, and the second power chip 104 is a gallium nitride chip.

[0047] In the embodiment of the utility model, the first power chip 103 and the second power chip 104 are both gallium nitride chips. The gallium nitride chip is an integrated circuit chip made of gallium nitride material, has the characteristics of high power density, high frequency performance and wide energy band gap, and is widely used in the fields of communication, consumer electronics and automotive electronics. The first power chip 103, the second power chip 104 and the driving chip 20 in the embodiment of the utility model jointly constitute a DrMOS, wherein the gallium nitride chip as the first power chip 103 is an upper tube, the gallium nitride chip as the second power chip 104 is a lower tube, the upper tube and the lower tube are connected with the driving chip 20, and jointly constitute a DrMOS.

[0048] On the basis of the above-mentioned utility model embodiment technical scheme, reference is made to Figure 1 Optionally, the bottom surface and the side wall of the groove 105 are provided with a first insulating layer 202, the first insulating layer 202 of the bottom surface of the groove 105 is located on the second surface 102, and the first insulating layer 202 is used to insulate the driving chip 20 from the first power chip 103 and insulate the driving chip 20 from the second power chip 104.

[0049] In the embodiment of the utility model, the first insulating layer 202 can be insulating glue. The first insulating layer 202 located on the side wall of the groove 105 is used to insulate the driving chip 20 from the first power chip 103 and insulate the driving chip 20 from the second power chip 104, and the first insulating layer 202 located on the bottom of the groove 105 is used to insulate the first power chip 103 from the second power chip 104. Since the signal networks on the back surfaces of the first power chip 103 and the second power chip 104 are different, the first insulating layer 202 at the bottom of the groove 105 is used to insulate the first power chip 103 from the second power chip 104, so as to prevent the signal network connection on the back surfaces of the first power chip 103 and the second power chip 104 from being wrong.

[0050] On the basis of the above-mentioned utility model embodiment technical scheme, reference is made to Figure 1Optionally, the re-wiring layer 30 comprises a second insulating layer 303, a first re-wiring layer 306, a second re-wiring layer 307 and a third re-wiring layer 308; the re-wiring layer 30 comprises a third surface 301 and a fourth surface 302 oppositely arranged, and the third surface 301 is oppositely arranged with the first surface 101; the second insulating layer 303 is located on the third surface 301 and between the plurality of first power chip connection pads 106, between the plurality of second power chip connection pads 107, between the first power chip connection pads 106 and the driving chip connection pads 201, and between the second power chip connection pads 107 and the driving chip connection pads 201; the second insulating layer 303 extends from the third surface 301 to the re-wiring layer 30; the first re-wiring layer 306 is used to connect the first part of the pads 2011 of the driving chip connection pads 201; the second re-wiring layer 307 is used to connect the second part of the pads 2012 of the driving chip connection pads 201; and the third re-wiring layer 308 is used to connect the third part of the pads 2013 of the driving chip connection pads 201.

[0051] In the embodiment of the utility model, the second insulating layer 303 is arranged between the plurality of first power chip connection pads 106, between the plurality of second power chip connection pads 107, between the first power chip connection pads 106 and the driving chip connection pads 201, and between the second power chip connection pads 107 and the driving chip connection pads 201, so as to avoid the adhesion between the plurality of connection pads and form unnecessary electrical connection, and improve the reliability of the packaging structure. The first re-wiring layer 306 is used to wire-connect the first part of the pads 2011 of the driving chip connection pads 201. The second re-wiring layer 307 is used to wire-connect the second part of the pads 2012 of the driving chip connection pads 201. The third re-wiring layer 308 is used to wire-connect the third part of the pads 2013 of the driving chip connection pads 201. By arranging the first re-wiring layer 306, the second re-wiring layer 307 and the third re-wiring layer 308, the line connection between the first power chip 103 and the driving chip 20, between the second power chip 104 and the driving chip 20, and the driving chip 20 is clearer, the connection path is reduced, and thus the parasitic parameters on the signal transmission line are reduced.

[0052] On the basis of the above-mentioned utility model embodiment technical scheme, reference Figure 1Optionally, the re-wiring layer 30 further comprises a third insulating layer 304 and a fourth insulating layer 305, the third insulating layer 304 is located between the first re-wiring layer 306 and the third re-wiring layer 308, and is used for insulating the first re-wiring layer 306 and the third re-wiring layer 308; the fourth insulating layer 305 is located between the second re-wiring layer 307 and the third re-wiring layer 308, and is used for insulating the second re-wiring layer 307 and the third re-wiring layer 308.

[0053] In the embodiment of the utility model, the third insulating layer 304 is arranged between the first re-wiring layer 306 and the third re-wiring layer 308, so that line confusion between the first re-wiring layer 306 and the third re-wiring layer 308 is avoided. Similarly, the fourth insulating layer 305 is arranged between the second re-wiring layer 307 and the third re-wiring layer 308, so that line confusion between the second re-wiring layer 307 and the third re-wiring layer 308 is avoided. The signal wire connection in the packaging structure is clearer, the signal wire path is reduced, and the reliability of the packaging structure is improved. The third insulating layer 304 and the fourth insulating layer 305 are arranged, so that the first re-wiring layer 306, the second re-wiring layer 307 and the third re-wiring layer 308 are protected from oxidation, and the problem of re-wiring layer 30 electromigration is prevented.

[0054] Based on the technical scheme of the above-mentioned utility model embodiment, reference is made to Figure 1 Optionally, the packaging structure further comprises: a first conductive bump 401, a second conductive bump 402 and a third conductive bump 403; the first conductive bump 401 extends from the fourth surface 302 to the first re-wiring layer 306; the second conductive bump 402 extends from the fourth surface 302 to the second re-wiring layer 307; and the third conductive bump 403 extends from the fourth surface 302 to the third re-wiring layer 308.

[0055] In the embodiment of the utility model, the first conductive bump 401, the second conductive bump 402 and the third conductive bump 403 are arranged, and are used for connecting the first power chip 103, the second power chip 104 and the driving chip 20 with external circuits. The material of the first conductive bump 401, the second conductive bump 402 and the third conductive bump 403 can be tin.

[0056] Based on the technical scheme of the above-mentioned utility model embodiment, reference is made to Figure 1 Optionally, the packaging structure further comprises: a first metal layer 501, a second metal layer 502 and a third metal layer 503; the first metal layer 501 is located between the first conductive bump 401 and the first re-wiring layer 306; the second metal layer 502 is located between the second conductive bump 402 and the second re-wiring layer 307; and the third metal layer 503 is located between the third conductive bump 403 and the third re-wiring layer 308.

[0057] In an embodiment of the present invention, a first metal layer 501, a second metal layer 502 and a third metal layer 503 are respectively arranged between the first conductive bump 401 and the first redistribution layer 306, between the second conductive bump 402 and the second redistribution layer 307, and between the third conductive bump 403 and the third redistribution layer 308, so as to prevent the formation of Kirkendall voids between the solder bump and the metal layer under the bump, thereby improving the reliability of the circuit connection.

[0058] On the basis of the above-mentioned technical solution of the utility model embodiment, Figure 1 Optionally, the first metal layer 501 includes a first nickel metal layer, the second metal layer 502 includes a second nickel metal layer, and the third metal layer 503 includes a third nickel metal layer.

[0059] In the embodiment of the present invention, nickel is used to form the first metal layer 501, the second metal layer 502 and the third metal layer 503, which can prevent the formation of Kirkendall voids between the tin bumps and the under-bump metallization layer made of copper, thereby avoiding poor circuit contact and affecting signal transmission.

[0060] On the basis of the above-mentioned technical solution of the utility model embodiment, Figure 1 Optionally, the second insulating layer 303 includes a first polyimide insulating layer, the third insulating layer 304 includes a second polyimide insulating layer, and the fourth insulating layer 305 includes a third polyimide insulating layer.

[0061] In the embodiments of the present invention, polyimide has thermal stability, good mechanical properties such as high strength and good toughness, and superior electrical properties, making it an excellent insulating material. The first, second, and third polyimide insulating layers are formed as the second insulating layer 303, the third insulating layer 304, and the fourth insulating layer 305, respectively, to provide good insulation.

[0062] On the basis of the above-mentioned technical solution of the utility model embodiment, Figure 1 Optionally, the size of the groove 105 is larger than the size of the driving chip 20 .

[0063] In the embodiment of the present invention, the size of the groove 105 is larger than that of the driver chip 20 , so that the driver chip 20 is placed in the groove 105 , saving packaging space and reducing the package size.

[0064] In an optional embodiment of the present invention, the cross-sectional views corresponding to the various stages of forming the packaging structure include the following: Figure 3 Schematic diagram of a wafer with a wide scribe line area introduced according to an embodiment of the present invention. Figure 3As shown, it includes a first surface 101 and a second surface 102 arranged opposite to each other, a first power chip 103, a second power chip 104, and a plurality of first power chip connection pads 106 electrically connected to the first power chip 103 and a second power chip connection pad 107 electrically connected to the second power chip 104 arranged on the first surface 101. Figure 4 This is a schematic diagram of the structure of the groove provided according to the embodiment of the utility model. Figure 4 As shown, in Figure 3 On the basis of the structure shown, a groove 105 is provided between the first power chip 103 and the second power chip 104 in the scribe line area of ​​the wafer by photolithography and etching processes. Figure 5 This is a schematic diagram of the structure of the driver chip provided in the groove according to the embodiment of the present utility model. Figure 5 As shown, in Figure 4 Based on the structure shown, a first insulating layer 202 is provided in the groove 105, and the driver chip 20 is placed in the groove 105. A driver chip connection pad 201 is provided on the first surface 101, including a first pad 2011, a second pad 2012 and a third pad 2013. Figure 6 This is a schematic diagram of the structure of the redistribution layer provided according to an embodiment of the present utility model. Figure 6 As shown, in Figure 5 On the basis of the structure shown in FIG, a redistribution layer 30 is provided, including a third surface 301 and a fourth surface 302 arranged opposite to each other, a second insulating layer 303, a third insulating layer 304, a fourth insulating layer 305, a first redistribution layer 306, a second redistribution layer 307 and a third redistribution layer 308, as well as a first conductive bump 401, a second conductive bump 402, a third conductive bump 403, a first metal layer 501, a second metal layer 502 and a third metal layer 503. Figure 6 Based on the structure shown in the figure, the wafer is polished to form Figure 1 The packaging structure shown. Since the second surfaces 102 of the first power chip 103 and the second power chip 104 are connected to different signal networks, the second surfaces 102 of the first power chip 103 and the second power chip 104 are ground, and the first insulating layer 202 is exposed to ensure that the second surfaces 102 of the first power chip 103 and the second power chip 104 are separated, and it is convenient to cut the wafer. When grinding the wafer, a tape protection is provided on the bottom of the wafer to avoid damage to the first power chip 103 and the second power chip 104. The packaging structure formed by the embodiment of the present utility model is mainly used for sealing wafer-level chip packaging (WLCSP).

[0065] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this utility model can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this utility model can be achieved. This is not limited herein.

[0066] The above specific embodiments do not limit the scope of protection of this utility model. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model shall be included within the scope of protection of this utility model.

Claims

1. A packaging structure, characterized in that: include: A wafer comprising a first surface and a second surface arranged opposite to each other, wherein a first power chip and a second power chip are arranged on the first surface of the wafer, a groove is arranged between the first power chip and the second power chip, and an opening of the groove faces the first surface; a plurality of first power chip connection pads and a plurality of second power chip connection pads are arranged at intervals on the first surface; the first power chip connection pad is electrically connected to the first power chip, and the second power chip connection pad is electrically connected to the second power chip; A driver chip is located in the groove; the first surface is further provided with a plurality of driver chip connection pads arranged at intervals; the driver chip connection pads are electrically connected to the driver chip; The redistribution layer is located on the side of the first power chip connection pad, the second power chip connection pad and the driver chip connection pad away from the first surface, and the first power chip and the second power chip are interconnected through the first power chip connection pad, the second power chip connection pad and the driver chip connection pad.

2. The packaging structure according to claim 1, wherein: The first power chip is a gallium nitride chip, and the second power chip is a gallium nitride chip.

3. The packaging structure according to claim 1, wherein: The bottom surface and sidewalls of the groove are provided with a first insulating layer. The first insulating layer on the bottom surface of the groove is located on the second surface. The first insulating layer is used to insulate the driver chip from the first power chip, and to insulate the driver chip from the second power chip.

4. The packaging structure according to claim 1, wherein: The redistribution layer includes a second insulating layer, a first redistribution layer, a second redistribution layer and a third redistribution layer; the redistribution layer includes a third surface and a fourth surface arranged opposite to each other, and the third surface and the first surface are arranged opposite to each other; The second insulating layer is located on the third surface and is located between the plurality of first power chip connection pads, between the plurality of second power chip connection pads, between the first power chip connection pads and the driver chip connection pads, and between the second power chip connection pads and the driver chip connection pads; the second insulating layer extends from the third surface into the redistribution layer; The first redistribution layer is used to connect the first power chip connection pad and a first portion of the driver chip connection pad; The second redistribution layer is used to connect the second power chip connection pad and a second portion of the driver chip connection pad; The third redistribution layer is used to connect a third portion of the driver chip connection pads.

5. The packaging structure according to claim 4, wherein: The redistribution layer further includes a third insulating layer and a fourth insulating layer, wherein the third insulating layer is located between the first redistribution layer and the third redistribution layer and is used to insulate the first redistribution layer from the third redistribution layer; The fourth insulating layer is located between the second redistribution layer and the third redistribution layer, and is used to insulate the second redistribution layer from the third redistribution layer.

6. The packaging structure according to claim 4, wherein: Also includes: a first conductive bump, a second conductive bump, and a third conductive bump; The first conductive bump extends from the fourth surface to the first redistribution layer; The second conductive bump extends from the fourth surface to the second redistribution layer; The third conductive bump extends from the fourth surface to the third redistribution layer.

7. The packaging structure according to claim 6, wherein: Also includes: a first metal layer, a second metal layer, and a third metal layer; The first metal layer is located between the first conductive bump and the first redistribution layer; The second metal layer is located between the second conductive bump and the second redistribution layer; The third metal layer is located between the third conductive bump and the third redistribution layer.

8. The packaging structure according to claim 7, wherein: The first metal layer includes a first nickel metal layer, the second metal layer includes a second nickel metal layer, and the third metal layer includes a third nickel metal layer.

9. The packaging structure according to claim 5, wherein: The second insulating layer includes a first polyimide insulating layer, the third insulating layer includes a second polyimide insulating layer, and the fourth insulating layer includes a third polyimide insulating layer.

10. The packaging structure according to claim 1, wherein: The size of the groove is larger than that of the driving chip.

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